esp32c3/efuse/
clk.rs

1#[doc = "Register `CLK` reader"]
2pub type R = crate::R<CLK_SPEC>;
3#[doc = "Register `CLK` writer"]
4pub type W = crate::W<CLK_SPEC>;
5#[doc = "Field `EFUSE_MEM_FORCE_PD` reader - Set this bit to force eFuse SRAM into power-saving mode."]
6pub type EFUSE_MEM_FORCE_PD_R = crate::BitReader;
7#[doc = "Field `EFUSE_MEM_FORCE_PD` writer - Set this bit to force eFuse SRAM into power-saving mode."]
8pub type EFUSE_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MEM_CLK_FORCE_ON` reader - Set this bit and force to activate clock signal of eFuse SRAM."]
10pub type MEM_CLK_FORCE_ON_R = crate::BitReader;
11#[doc = "Field `MEM_CLK_FORCE_ON` writer - Set this bit and force to activate clock signal of eFuse SRAM."]
12pub type MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EFUSE_MEM_FORCE_PU` reader - Set this bit to force eFuse SRAM into working mode."]
14pub type EFUSE_MEM_FORCE_PU_R = crate::BitReader;
15#[doc = "Field `EFUSE_MEM_FORCE_PU` writer - Set this bit to force eFuse SRAM into working mode."]
16pub type EFUSE_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `EN` reader - Set this bit and force to enable clock signal of eFuse memory."]
18pub type EN_R = crate::BitReader;
19#[doc = "Field `EN` writer - Set this bit and force to enable clock signal of eFuse memory."]
20pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - Set this bit to force eFuse SRAM into power-saving mode."]
23    #[inline(always)]
24    pub fn efuse_mem_force_pd(&self) -> EFUSE_MEM_FORCE_PD_R {
25        EFUSE_MEM_FORCE_PD_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Set this bit and force to activate clock signal of eFuse SRAM."]
28    #[inline(always)]
29    pub fn mem_clk_force_on(&self) -> MEM_CLK_FORCE_ON_R {
30        MEM_CLK_FORCE_ON_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - Set this bit to force eFuse SRAM into working mode."]
33    #[inline(always)]
34    pub fn efuse_mem_force_pu(&self) -> EFUSE_MEM_FORCE_PU_R {
35        EFUSE_MEM_FORCE_PU_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 16 - Set this bit and force to enable clock signal of eFuse memory."]
38    #[inline(always)]
39    pub fn en(&self) -> EN_R {
40        EN_R::new(((self.bits >> 16) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CLK")
47            .field("efuse_mem_force_pd", &self.efuse_mem_force_pd())
48            .field("mem_clk_force_on", &self.mem_clk_force_on())
49            .field("efuse_mem_force_pu", &self.efuse_mem_force_pu())
50            .field("en", &self.en())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bit 0 - Set this bit to force eFuse SRAM into power-saving mode."]
56    #[inline(always)]
57    pub fn efuse_mem_force_pd(&mut self) -> EFUSE_MEM_FORCE_PD_W<CLK_SPEC> {
58        EFUSE_MEM_FORCE_PD_W::new(self, 0)
59    }
60    #[doc = "Bit 1 - Set this bit and force to activate clock signal of eFuse SRAM."]
61    #[inline(always)]
62    pub fn mem_clk_force_on(&mut self) -> MEM_CLK_FORCE_ON_W<CLK_SPEC> {
63        MEM_CLK_FORCE_ON_W::new(self, 1)
64    }
65    #[doc = "Bit 2 - Set this bit to force eFuse SRAM into working mode."]
66    #[inline(always)]
67    pub fn efuse_mem_force_pu(&mut self) -> EFUSE_MEM_FORCE_PU_W<CLK_SPEC> {
68        EFUSE_MEM_FORCE_PU_W::new(self, 2)
69    }
70    #[doc = "Bit 16 - Set this bit and force to enable clock signal of eFuse memory."]
71    #[inline(always)]
72    pub fn en(&mut self) -> EN_W<CLK_SPEC> {
73        EN_W::new(self, 16)
74    }
75}
76#[doc = "eFuse clock configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`clk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct CLK_SPEC;
78impl crate::RegisterSpec for CLK_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`clk::R`](R) reader structure"]
82impl crate::Readable for CLK_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"]
84impl crate::Writable for CLK_SPEC {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets CLK to value 0x02"]
90impl crate::Resettable for CLK_SPEC {
91    const RESET_VALUE: u32 = 0x02;
92}
esp32c3/efuse/clk.rs

esp32c3/efuse/
clk.rs
