esp32c3/dma/
misc_conf.rs

1#[doc = "Register `MISC_CONF` reader"]
2pub type R = crate::R<MISC_CONF_SPEC>;
3#[doc = "Register `MISC_CONF` writer"]
4pub type W = crate::W<MISC_CONF_SPEC>;
5#[doc = "Field `AHBM_RST_INTER` reader - Set this bit, then clear this bit to reset the internal ahb FSM."]
6pub type AHBM_RST_INTER_R = crate::BitReader;
7#[doc = "Field `AHBM_RST_INTER` writer - Set this bit, then clear this bit to reset the internal ahb FSM."]
8pub type AHBM_RST_INTER_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ARB_PRI_DIS` reader - Set this bit to disable priority arbitration function."]
10pub type ARB_PRI_DIS_R = crate::BitReader;
11#[doc = "Field `ARB_PRI_DIS` writer - Set this bit to disable priority arbitration function."]
12pub type ARB_PRI_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CLK_EN` reader - reg_clk_en"]
14pub type CLK_EN_R = crate::BitReader;
15#[doc = "Field `CLK_EN` writer - reg_clk_en"]
16pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - Set this bit, then clear this bit to reset the internal ahb FSM."]
19    #[inline(always)]
20    pub fn ahbm_rst_inter(&self) -> AHBM_RST_INTER_R {
21        AHBM_RST_INTER_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 2 - Set this bit to disable priority arbitration function."]
24    #[inline(always)]
25    pub fn arb_pri_dis(&self) -> ARB_PRI_DIS_R {
26        ARB_PRI_DIS_R::new(((self.bits >> 2) & 1) != 0)
27    }
28    #[doc = "Bit 3 - reg_clk_en"]
29    #[inline(always)]
30    pub fn clk_en(&self) -> CLK_EN_R {
31        CLK_EN_R::new(((self.bits >> 3) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("MISC_CONF")
38            .field("ahbm_rst_inter", &self.ahbm_rst_inter())
39            .field("arb_pri_dis", &self.arb_pri_dis())
40            .field("clk_en", &self.clk_en())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bit 0 - Set this bit, then clear this bit to reset the internal ahb FSM."]
46    #[inline(always)]
47    pub fn ahbm_rst_inter(&mut self) -> AHBM_RST_INTER_W<MISC_CONF_SPEC> {
48        AHBM_RST_INTER_W::new(self, 0)
49    }
50    #[doc = "Bit 2 - Set this bit to disable priority arbitration function."]
51    #[inline(always)]
52    pub fn arb_pri_dis(&mut self) -> ARB_PRI_DIS_W<MISC_CONF_SPEC> {
53        ARB_PRI_DIS_W::new(self, 2)
54    }
55    #[doc = "Bit 3 - reg_clk_en"]
56    #[inline(always)]
57    pub fn clk_en(&mut self) -> CLK_EN_W<MISC_CONF_SPEC> {
58        CLK_EN_W::new(self, 3)
59    }
60}
61#[doc = "DMA_MISC_CONF_REG.\n\nYou can [`read`](crate::Reg::read) this register and get [`misc_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct MISC_CONF_SPEC;
63impl crate::RegisterSpec for MISC_CONF_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`misc_conf::R`](R) reader structure"]
67impl crate::Readable for MISC_CONF_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`misc_conf::W`](W) writer structure"]
69impl crate::Writable for MISC_CONF_SPEC {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73}
74#[doc = "`reset()` method sets MISC_CONF to value 0"]
75impl crate::Resettable for MISC_CONF_SPEC {
76    const RESET_VALUE: u32 = 0;
77}
esp32c3/dma/misc_conf.rs

esp32c3/dma/
misc_conf.rs
