esp32c3/extmem/
icache_autoload_sct0_addr.rs

1#[doc = "Register `ICACHE_AUTOLOAD_SCT0_ADDR` reader"]
2pub type R = crate::R<ICACHE_AUTOLOAD_SCT0_ADDR_SPEC>;
3#[doc = "Register `ICACHE_AUTOLOAD_SCT0_ADDR` writer"]
4pub type W = crate::W<ICACHE_AUTOLOAD_SCT0_ADDR_SPEC>;
5#[doc = "Field `ICACHE_AUTOLOAD_SCT0_ADDR` reader - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
6pub type ICACHE_AUTOLOAD_SCT0_ADDR_R = crate::FieldReader<u32>;
7#[doc = "Field `ICACHE_AUTOLOAD_SCT0_ADDR` writer - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
8pub type ICACHE_AUTOLOAD_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
11    #[inline(always)]
12    pub fn icache_autoload_sct0_addr(&self) -> ICACHE_AUTOLOAD_SCT0_ADDR_R {
13        ICACHE_AUTOLOAD_SCT0_ADDR_R::new(self.bits)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("ICACHE_AUTOLOAD_SCT0_ADDR")
20            .field(
21                "icache_autoload_sct0_addr",
22                &self.icache_autoload_sct0_addr(),
23            )
24            .finish()
25    }
26}
27impl W {
28    #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
29    #[inline(always)]
30    pub fn icache_autoload_sct0_addr(
31        &mut self,
32    ) -> ICACHE_AUTOLOAD_SCT0_ADDR_W<ICACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
33        ICACHE_AUTOLOAD_SCT0_ADDR_W::new(self, 0)
34    }
35}
36#[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_autoload_sct0_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_autoload_sct0_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
37pub struct ICACHE_AUTOLOAD_SCT0_ADDR_SPEC;
38impl crate::RegisterSpec for ICACHE_AUTOLOAD_SCT0_ADDR_SPEC {
39    type Ux = u32;
40}
41#[doc = "`read()` method returns [`icache_autoload_sct0_addr::R`](R) reader structure"]
42impl crate::Readable for ICACHE_AUTOLOAD_SCT0_ADDR_SPEC {}
43#[doc = "`write(|w| ..)` method takes [`icache_autoload_sct0_addr::W`](W) writer structure"]
44impl crate::Writable for ICACHE_AUTOLOAD_SCT0_ADDR_SPEC {
45    type Safety = crate::Unsafe;
46}
47#[doc = "`reset()` method sets ICACHE_AUTOLOAD_SCT0_ADDR to value 0"]
48impl crate::Resettable for ICACHE_AUTOLOAD_SCT0_ADDR_SPEC {}
esp32c3/extmem/icache_autoload_sct0_addr.rs

esp32c3/extmem/
icache_autoload_sct0_addr.rs
