1#[doc = "Register `TX_CONF` reader"]
2pub type R = crate::R<TX_CONF_SPEC>;
3#[doc = "Register `TX_CONF` writer"]
4pub type W = crate::W<TX_CONF_SPEC>;
5#[doc = "Field `TX_RESET` writer - Set this bit to reset transmitter"]
6pub type TX_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `TX_FIFO_RESET` writer - Set this bit to reset Tx AFIFO"]
8pub type TX_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TX_START` reader - Set this bit to start transmitting data"]
10pub type TX_START_R = crate::BitReader;
11#[doc = "Field `TX_START` writer - Set this bit to start transmitting data"]
12pub type TX_START_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TX_SLAVE_MOD` reader - Set this bit to enable slave transmitter mode"]
14pub type TX_SLAVE_MOD_R = crate::BitReader;
15#[doc = "Field `TX_SLAVE_MOD` writer - Set this bit to enable slave transmitter mode"]
16pub type TX_SLAVE_MOD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TX_MONO` reader - Set this bit to enable transmitter in mono mode"]
18pub type TX_MONO_R = crate::BitReader;
19#[doc = "Field `TX_MONO` writer - Set this bit to enable transmitter in mono mode"]
20pub type TX_MONO_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TX_CHAN_EQUAL` reader - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."]
22pub type TX_CHAN_EQUAL_R = crate::BitReader;
23#[doc = "Field `TX_CHAN_EQUAL` writer - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."]
24pub type TX_CHAN_EQUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TX_BIG_ENDIAN` reader - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
26pub type TX_BIG_ENDIAN_R = crate::BitReader;
27#[doc = "Field `TX_BIG_ENDIAN` writer - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
28pub type TX_BIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TX_UPDATE` reader - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."]
30pub type TX_UPDATE_R = crate::BitReader;
31#[doc = "Field `TX_UPDATE` writer - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."]
32pub type TX_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `TX_MONO_FST_VLD` reader - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
34pub type TX_MONO_FST_VLD_R = crate::BitReader;
35#[doc = "Field `TX_MONO_FST_VLD` writer - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
36pub type TX_MONO_FST_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TX_PCM_CONF` reader - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
38pub type TX_PCM_CONF_R = crate::FieldReader;
39#[doc = "Field `TX_PCM_CONF` writer - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
40pub type TX_PCM_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
41#[doc = "Field `TX_PCM_BYPASS` reader - Set this bit to bypass Compress/Decompress module for transmitted data."]
42pub type TX_PCM_BYPASS_R = crate::BitReader;
43#[doc = "Field `TX_PCM_BYPASS` writer - Set this bit to bypass Compress/Decompress module for transmitted data."]
44pub type TX_PCM_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `TX_STOP_EN` reader - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"]
46pub type TX_STOP_EN_R = crate::BitReader;
47#[doc = "Field `TX_STOP_EN` writer - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"]
48pub type TX_STOP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `TX_LEFT_ALIGN` reader - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."]
50pub type TX_LEFT_ALIGN_R = crate::BitReader;
51#[doc = "Field `TX_LEFT_ALIGN` writer - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."]
52pub type TX_LEFT_ALIGN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `TX_24_FILL_EN` reader - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"]
54pub type TX_24_FILL_EN_R = crate::BitReader;
55#[doc = "Field `TX_24_FILL_EN` writer - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"]
56pub type TX_24_FILL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `TX_WS_IDLE_POL` reader - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."]
58pub type TX_WS_IDLE_POL_R = crate::BitReader;
59#[doc = "Field `TX_WS_IDLE_POL` writer - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."]
60pub type TX_WS_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `TX_BIT_ORDER` reader - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."]
62pub type TX_BIT_ORDER_R = crate::BitReader;
63#[doc = "Field `TX_BIT_ORDER` writer - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."]
64pub type TX_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `TX_TDM_EN` reader - 1: Enable I2S TDM Tx mode . 0: Disable."]
66pub type TX_TDM_EN_R = crate::BitReader;
67#[doc = "Field `TX_TDM_EN` writer - 1: Enable I2S TDM Tx mode . 0: Disable."]
68pub type TX_TDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `TX_PDM_EN` reader - 1: Enable I2S PDM Tx mode . 0: Disable."]
70pub type TX_PDM_EN_R = crate::BitReader;
71#[doc = "Field `TX_PDM_EN` writer - 1: Enable I2S PDM Tx mode . 0: Disable."]
72pub type TX_PDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `TX_CHAN_MOD` reader - I2S transmitter channel mode configuration bits."]
74pub type TX_CHAN_MOD_R = crate::FieldReader;
75#[doc = "Field `TX_CHAN_MOD` writer - I2S transmitter channel mode configuration bits."]
76pub type TX_CHAN_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
77#[doc = "Field `SIG_LOOPBACK` reader - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."]
78pub type SIG_LOOPBACK_R = crate::BitReader;
79#[doc = "Field `SIG_LOOPBACK` writer - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."]
80pub type SIG_LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>;
81impl R {
82 #[doc = "Bit 2 - Set this bit to start transmitting data"]
83 #[inline(always)]
84 pub fn tx_start(&self) -> TX_START_R {
85 TX_START_R::new(((self.bits >> 2) & 1) != 0)
86 }
87 #[doc = "Bit 3 - Set this bit to enable slave transmitter mode"]
88 #[inline(always)]
89 pub fn tx_slave_mod(&self) -> TX_SLAVE_MOD_R {
90 TX_SLAVE_MOD_R::new(((self.bits >> 3) & 1) != 0)
91 }
92 #[doc = "Bit 5 - Set this bit to enable transmitter in mono mode"]
93 #[inline(always)]
94 pub fn tx_mono(&self) -> TX_MONO_R {
95 TX_MONO_R::new(((self.bits >> 5) & 1) != 0)
96 }
97 #[doc = "Bit 6 - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."]
98 #[inline(always)]
99 pub fn tx_chan_equal(&self) -> TX_CHAN_EQUAL_R {
100 TX_CHAN_EQUAL_R::new(((self.bits >> 6) & 1) != 0)
101 }
102 #[doc = "Bit 7 - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
103 #[inline(always)]
104 pub fn tx_big_endian(&self) -> TX_BIG_ENDIAN_R {
105 TX_BIG_ENDIAN_R::new(((self.bits >> 7) & 1) != 0)
106 }
107 #[doc = "Bit 8 - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."]
108 #[inline(always)]
109 pub fn tx_update(&self) -> TX_UPDATE_R {
110 TX_UPDATE_R::new(((self.bits >> 8) & 1) != 0)
111 }
112 #[doc = "Bit 9 - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
113 #[inline(always)]
114 pub fn tx_mono_fst_vld(&self) -> TX_MONO_FST_VLD_R {
115 TX_MONO_FST_VLD_R::new(((self.bits >> 9) & 1) != 0)
116 }
117 #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
118 #[inline(always)]
119 pub fn tx_pcm_conf(&self) -> TX_PCM_CONF_R {
120 TX_PCM_CONF_R::new(((self.bits >> 10) & 3) as u8)
121 }
122 #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for transmitted data."]
123 #[inline(always)]
124 pub fn tx_pcm_bypass(&self) -> TX_PCM_BYPASS_R {
125 TX_PCM_BYPASS_R::new(((self.bits >> 12) & 1) != 0)
126 }
127 #[doc = "Bit 13 - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"]
128 #[inline(always)]
129 pub fn tx_stop_en(&self) -> TX_STOP_EN_R {
130 TX_STOP_EN_R::new(((self.bits >> 13) & 1) != 0)
131 }
132 #[doc = "Bit 15 - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."]
133 #[inline(always)]
134 pub fn tx_left_align(&self) -> TX_LEFT_ALIGN_R {
135 TX_LEFT_ALIGN_R::new(((self.bits >> 15) & 1) != 0)
136 }
137 #[doc = "Bit 16 - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"]
138 #[inline(always)]
139 pub fn tx_24_fill_en(&self) -> TX_24_FILL_EN_R {
140 TX_24_FILL_EN_R::new(((self.bits >> 16) & 1) != 0)
141 }
142 #[doc = "Bit 17 - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."]
143 #[inline(always)]
144 pub fn tx_ws_idle_pol(&self) -> TX_WS_IDLE_POL_R {
145 TX_WS_IDLE_POL_R::new(((self.bits >> 17) & 1) != 0)
146 }
147 #[doc = "Bit 18 - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."]
148 #[inline(always)]
149 pub fn tx_bit_order(&self) -> TX_BIT_ORDER_R {
150 TX_BIT_ORDER_R::new(((self.bits >> 18) & 1) != 0)
151 }
152 #[doc = "Bit 19 - 1: Enable I2S TDM Tx mode . 0: Disable."]
153 #[inline(always)]
154 pub fn tx_tdm_en(&self) -> TX_TDM_EN_R {
155 TX_TDM_EN_R::new(((self.bits >> 19) & 1) != 0)
156 }
157 #[doc = "Bit 20 - 1: Enable I2S PDM Tx mode . 0: Disable."]
158 #[inline(always)]
159 pub fn tx_pdm_en(&self) -> TX_PDM_EN_R {
160 TX_PDM_EN_R::new(((self.bits >> 20) & 1) != 0)
161 }
162 #[doc = "Bits 24:26 - I2S transmitter channel mode configuration bits."]
163 #[inline(always)]
164 pub fn tx_chan_mod(&self) -> TX_CHAN_MOD_R {
165 TX_CHAN_MOD_R::new(((self.bits >> 24) & 7) as u8)
166 }
167 #[doc = "Bit 27 - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."]
168 #[inline(always)]
169 pub fn sig_loopback(&self) -> SIG_LOOPBACK_R {
170 SIG_LOOPBACK_R::new(((self.bits >> 27) & 1) != 0)
171 }
172}
173#[cfg(feature = "impl-register-debug")]
174impl core::fmt::Debug for R {
175 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
176 f.debug_struct("TX_CONF")
177 .field("tx_start", &self.tx_start())
178 .field("tx_slave_mod", &self.tx_slave_mod())
179 .field("tx_mono", &self.tx_mono())
180 .field("tx_chan_equal", &self.tx_chan_equal())
181 .field("tx_big_endian", &self.tx_big_endian())
182 .field("tx_update", &self.tx_update())
183 .field("tx_mono_fst_vld", &self.tx_mono_fst_vld())
184 .field("tx_pcm_conf", &self.tx_pcm_conf())
185 .field("tx_pcm_bypass", &self.tx_pcm_bypass())
186 .field("tx_stop_en", &self.tx_stop_en())
187 .field("tx_left_align", &self.tx_left_align())
188 .field("tx_24_fill_en", &self.tx_24_fill_en())
189 .field("tx_ws_idle_pol", &self.tx_ws_idle_pol())
190 .field("tx_bit_order", &self.tx_bit_order())
191 .field("tx_tdm_en", &self.tx_tdm_en())
192 .field("tx_pdm_en", &self.tx_pdm_en())
193 .field("tx_chan_mod", &self.tx_chan_mod())
194 .field("sig_loopback", &self.sig_loopback())
195 .finish()
196 }
197}
198impl W {
199 #[doc = "Bit 0 - Set this bit to reset transmitter"]
200 #[inline(always)]
201 pub fn tx_reset(&mut self) -> TX_RESET_W<TX_CONF_SPEC> {
202 TX_RESET_W::new(self, 0)
203 }
204 #[doc = "Bit 1 - Set this bit to reset Tx AFIFO"]
205 #[inline(always)]
206 pub fn tx_fifo_reset(&mut self) -> TX_FIFO_RESET_W<TX_CONF_SPEC> {
207 TX_FIFO_RESET_W::new(self, 1)
208 }
209 #[doc = "Bit 2 - Set this bit to start transmitting data"]
210 #[inline(always)]
211 pub fn tx_start(&mut self) -> TX_START_W<TX_CONF_SPEC> {
212 TX_START_W::new(self, 2)
213 }
214 #[doc = "Bit 3 - Set this bit to enable slave transmitter mode"]
215 #[inline(always)]
216 pub fn tx_slave_mod(&mut self) -> TX_SLAVE_MOD_W<TX_CONF_SPEC> {
217 TX_SLAVE_MOD_W::new(self, 3)
218 }
219 #[doc = "Bit 5 - Set this bit to enable transmitter in mono mode"]
220 #[inline(always)]
221 pub fn tx_mono(&mut self) -> TX_MONO_W<TX_CONF_SPEC> {
222 TX_MONO_W::new(self, 5)
223 }
224 #[doc = "Bit 6 - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."]
225 #[inline(always)]
226 pub fn tx_chan_equal(&mut self) -> TX_CHAN_EQUAL_W<TX_CONF_SPEC> {
227 TX_CHAN_EQUAL_W::new(self, 6)
228 }
229 #[doc = "Bit 7 - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
230 #[inline(always)]
231 pub fn tx_big_endian(&mut self) -> TX_BIG_ENDIAN_W<TX_CONF_SPEC> {
232 TX_BIG_ENDIAN_W::new(self, 7)
233 }
234 #[doc = "Bit 8 - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."]
235 #[inline(always)]
236 pub fn tx_update(&mut self) -> TX_UPDATE_W<TX_CONF_SPEC> {
237 TX_UPDATE_W::new(self, 8)
238 }
239 #[doc = "Bit 9 - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
240 #[inline(always)]
241 pub fn tx_mono_fst_vld(&mut self) -> TX_MONO_FST_VLD_W<TX_CONF_SPEC> {
242 TX_MONO_FST_VLD_W::new(self, 9)
243 }
244 #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
245 #[inline(always)]
246 pub fn tx_pcm_conf(&mut self) -> TX_PCM_CONF_W<TX_CONF_SPEC> {
247 TX_PCM_CONF_W::new(self, 10)
248 }
249 #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for transmitted data."]
250 #[inline(always)]
251 pub fn tx_pcm_bypass(&mut self) -> TX_PCM_BYPASS_W<TX_CONF_SPEC> {
252 TX_PCM_BYPASS_W::new(self, 12)
253 }
254 #[doc = "Bit 13 - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"]
255 #[inline(always)]
256 pub fn tx_stop_en(&mut self) -> TX_STOP_EN_W<TX_CONF_SPEC> {
257 TX_STOP_EN_W::new(self, 13)
258 }
259 #[doc = "Bit 15 - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."]
260 #[inline(always)]
261 pub fn tx_left_align(&mut self) -> TX_LEFT_ALIGN_W<TX_CONF_SPEC> {
262 TX_LEFT_ALIGN_W::new(self, 15)
263 }
264 #[doc = "Bit 16 - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"]
265 #[inline(always)]
266 pub fn tx_24_fill_en(&mut self) -> TX_24_FILL_EN_W<TX_CONF_SPEC> {
267 TX_24_FILL_EN_W::new(self, 16)
268 }
269 #[doc = "Bit 17 - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."]
270 #[inline(always)]
271 pub fn tx_ws_idle_pol(&mut self) -> TX_WS_IDLE_POL_W<TX_CONF_SPEC> {
272 TX_WS_IDLE_POL_W::new(self, 17)
273 }
274 #[doc = "Bit 18 - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."]
275 #[inline(always)]
276 pub fn tx_bit_order(&mut self) -> TX_BIT_ORDER_W<TX_CONF_SPEC> {
277 TX_BIT_ORDER_W::new(self, 18)
278 }
279 #[doc = "Bit 19 - 1: Enable I2S TDM Tx mode . 0: Disable."]
280 #[inline(always)]
281 pub fn tx_tdm_en(&mut self) -> TX_TDM_EN_W<TX_CONF_SPEC> {
282 TX_TDM_EN_W::new(self, 19)
283 }
284 #[doc = "Bit 20 - 1: Enable I2S PDM Tx mode . 0: Disable."]
285 #[inline(always)]
286 pub fn tx_pdm_en(&mut self) -> TX_PDM_EN_W<TX_CONF_SPEC> {
287 TX_PDM_EN_W::new(self, 20)
288 }
289 #[doc = "Bits 24:26 - I2S transmitter channel mode configuration bits."]
290 #[inline(always)]
291 pub fn tx_chan_mod(&mut self) -> TX_CHAN_MOD_W<TX_CONF_SPEC> {
292 TX_CHAN_MOD_W::new(self, 24)
293 }
294 #[doc = "Bit 27 - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."]
295 #[inline(always)]
296 pub fn sig_loopback(&mut self) -> SIG_LOOPBACK_W<TX_CONF_SPEC> {
297 SIG_LOOPBACK_W::new(self, 27)
298 }
299}
300#[doc = "I2S TX configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
301pub struct TX_CONF_SPEC;
302impl crate::RegisterSpec for TX_CONF_SPEC {
303 type Ux = u32;
304}
305#[doc = "`read()` method returns [`tx_conf::R`](R) reader structure"]
306impl crate::Readable for TX_CONF_SPEC {}
307#[doc = "`write(|w| ..)` method takes [`tx_conf::W`](W) writer structure"]
308impl crate::Writable for TX_CONF_SPEC {
309 type Safety = crate::Unsafe;
310 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
311 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
312}
313#[doc = "`reset()` method sets TX_CONF to value 0xb200"]
314impl crate::Resettable for TX_CONF_SPEC {
315 const RESET_VALUE: u32 = 0xb200;
316}