esp32c3/rtc_cntl/
clk_conf.rs

1#[doc = "Register `CLK_CONF` reader"]
2pub type R = crate::R<CLK_CONF_SPEC>;
3#[doc = "Register `CLK_CONF` writer"]
4pub type W = crate::W<CLK_CONF_SPEC>;
5#[doc = "Field `EFUSE_CLK_FORCE_GATING` reader - efuse_clk_force_gating"]
6pub type EFUSE_CLK_FORCE_GATING_R = crate::BitReader;
7#[doc = "Field `EFUSE_CLK_FORCE_GATING` writer - efuse_clk_force_gating"]
8pub type EFUSE_CLK_FORCE_GATING_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `EFUSE_CLK_FORCE_NOGATING` reader - efuse_clk_force_nogating"]
10pub type EFUSE_CLK_FORCE_NOGATING_R = crate::BitReader;
11#[doc = "Field `EFUSE_CLK_FORCE_NOGATING` writer - efuse_clk_force_nogating"]
12pub type EFUSE_CLK_FORCE_NOGATING_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CK8M_DIV_SEL_VLD` reader - used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel"]
14pub type CK8M_DIV_SEL_VLD_R = crate::BitReader;
15#[doc = "Field `CK8M_DIV_SEL_VLD` writer - used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel"]
16pub type CK8M_DIV_SEL_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CK8M_DIV` reader - CK8M_D256_OUT divider. 00: div128"]
18pub type CK8M_DIV_R = crate::FieldReader;
19#[doc = "Field `CK8M_DIV` writer - CK8M_D256_OUT divider. 00: div128"]
20pub type CK8M_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `ENB_CK8M` reader - disable CK8M and CK8M_D256_OUT"]
22pub type ENB_CK8M_R = crate::BitReader;
23#[doc = "Field `ENB_CK8M` writer - disable CK8M and CK8M_D256_OUT"]
24pub type ENB_CK8M_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ENB_CK8M_DIV` reader - 1: CK8M_D256_OUT is actually CK8M"]
26pub type ENB_CK8M_DIV_R = crate::BitReader;
27#[doc = "Field `ENB_CK8M_DIV` writer - 1: CK8M_D256_OUT is actually CK8M"]
28pub type ENB_CK8M_DIV_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DIG_XTAL32K_EN` reader - enable CK_XTAL_32K for digital core (no relationship with RTC core)"]
30pub type DIG_XTAL32K_EN_R = crate::BitReader;
31#[doc = "Field `DIG_XTAL32K_EN` writer - enable CK_XTAL_32K for digital core (no relationship with RTC core)"]
32pub type DIG_XTAL32K_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DIG_CLK8M_D256_EN` reader - enable CK8M_D256_OUT for digital core (no relationship with RTC core)"]
34pub type DIG_CLK8M_D256_EN_R = crate::BitReader;
35#[doc = "Field `DIG_CLK8M_D256_EN` writer - enable CK8M_D256_OUT for digital core (no relationship with RTC core)"]
36pub type DIG_CLK8M_D256_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DIG_CLK8M_EN` reader - enable CK8M for digital core (no relationship with RTC core)"]
38pub type DIG_CLK8M_EN_R = crate::BitReader;
39#[doc = "Field `DIG_CLK8M_EN` writer - enable CK8M for digital core (no relationship with RTC core)"]
40pub type DIG_CLK8M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CK8M_DIV_SEL` reader - divider = reg_ck8m_div_sel + 1"]
42pub type CK8M_DIV_SEL_R = crate::FieldReader;
43#[doc = "Field `CK8M_DIV_SEL` writer - divider = reg_ck8m_div_sel + 1"]
44pub type CK8M_DIV_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
45#[doc = "Field `XTAL_FORCE_NOGATING` reader - XTAL force no gating during sleep"]
46pub type XTAL_FORCE_NOGATING_R = crate::BitReader;
47#[doc = "Field `XTAL_FORCE_NOGATING` writer - XTAL force no gating during sleep"]
48pub type XTAL_FORCE_NOGATING_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `CK8M_FORCE_NOGATING` reader - CK8M force no gating during sleep"]
50pub type CK8M_FORCE_NOGATING_R = crate::BitReader;
51#[doc = "Field `CK8M_FORCE_NOGATING` writer - CK8M force no gating during sleep"]
52pub type CK8M_FORCE_NOGATING_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `CK8M_DFREQ` reader - CK8M_DFREQ"]
54pub type CK8M_DFREQ_R = crate::FieldReader;
55#[doc = "Field `CK8M_DFREQ` writer - CK8M_DFREQ"]
56pub type CK8M_DFREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
57#[doc = "Field `CK8M_FORCE_PD` reader - CK8M force power down"]
58pub type CK8M_FORCE_PD_R = crate::BitReader;
59#[doc = "Field `CK8M_FORCE_PD` writer - CK8M force power down"]
60pub type CK8M_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `CK8M_FORCE_PU` reader - CK8M force power up"]
62pub type CK8M_FORCE_PU_R = crate::BitReader;
63#[doc = "Field `CK8M_FORCE_PU` writer - CK8M force power up"]
64pub type CK8M_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `XTAL_GLOBAL_FORCE_GATING` reader - force enable xtal clk gating"]
66pub type XTAL_GLOBAL_FORCE_GATING_R = crate::BitReader;
67#[doc = "Field `XTAL_GLOBAL_FORCE_GATING` writer - force enable xtal clk gating"]
68pub type XTAL_GLOBAL_FORCE_GATING_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `XTAL_GLOBAL_FORCE_NOGATING` reader - force bypass xtal clk gating"]
70pub type XTAL_GLOBAL_FORCE_NOGATING_R = crate::BitReader;
71#[doc = "Field `XTAL_GLOBAL_FORCE_NOGATING` writer - force bypass xtal clk gating"]
72pub type XTAL_GLOBAL_FORCE_NOGATING_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `FAST_CLK_RTC_SEL` reader - fast_clk_rtc sel. 0: XTAL div 4"]
74pub type FAST_CLK_RTC_SEL_R = crate::BitReader;
75#[doc = "Field `FAST_CLK_RTC_SEL` writer - fast_clk_rtc sel. 0: XTAL div 4"]
76pub type FAST_CLK_RTC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `ANA_CLK_RTC_SEL` reader - slelect rtc slow clk"]
78pub type ANA_CLK_RTC_SEL_R = crate::FieldReader;
79#[doc = "Field `ANA_CLK_RTC_SEL` writer - slelect rtc slow clk"]
80pub type ANA_CLK_RTC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
81impl R {
82    #[doc = "Bit 1 - efuse_clk_force_gating"]
83    #[inline(always)]
84    pub fn efuse_clk_force_gating(&self) -> EFUSE_CLK_FORCE_GATING_R {
85        EFUSE_CLK_FORCE_GATING_R::new(((self.bits >> 1) & 1) != 0)
86    }
87    #[doc = "Bit 2 - efuse_clk_force_nogating"]
88    #[inline(always)]
89    pub fn efuse_clk_force_nogating(&self) -> EFUSE_CLK_FORCE_NOGATING_R {
90        EFUSE_CLK_FORCE_NOGATING_R::new(((self.bits >> 2) & 1) != 0)
91    }
92    #[doc = "Bit 3 - used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel"]
93    #[inline(always)]
94    pub fn ck8m_div_sel_vld(&self) -> CK8M_DIV_SEL_VLD_R {
95        CK8M_DIV_SEL_VLD_R::new(((self.bits >> 3) & 1) != 0)
96    }
97    #[doc = "Bits 4:5 - CK8M_D256_OUT divider. 00: div128"]
98    #[inline(always)]
99    pub fn ck8m_div(&self) -> CK8M_DIV_R {
100        CK8M_DIV_R::new(((self.bits >> 4) & 3) as u8)
101    }
102    #[doc = "Bit 6 - disable CK8M and CK8M_D256_OUT"]
103    #[inline(always)]
104    pub fn enb_ck8m(&self) -> ENB_CK8M_R {
105        ENB_CK8M_R::new(((self.bits >> 6) & 1) != 0)
106    }
107    #[doc = "Bit 7 - 1: CK8M_D256_OUT is actually CK8M"]
108    #[inline(always)]
109    pub fn enb_ck8m_div(&self) -> ENB_CK8M_DIV_R {
110        ENB_CK8M_DIV_R::new(((self.bits >> 7) & 1) != 0)
111    }
112    #[doc = "Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)"]
113    #[inline(always)]
114    pub fn dig_xtal32k_en(&self) -> DIG_XTAL32K_EN_R {
115        DIG_XTAL32K_EN_R::new(((self.bits >> 8) & 1) != 0)
116    }
117    #[doc = "Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)"]
118    #[inline(always)]
119    pub fn dig_clk8m_d256_en(&self) -> DIG_CLK8M_D256_EN_R {
120        DIG_CLK8M_D256_EN_R::new(((self.bits >> 9) & 1) != 0)
121    }
122    #[doc = "Bit 10 - enable CK8M for digital core (no relationship with RTC core)"]
123    #[inline(always)]
124    pub fn dig_clk8m_en(&self) -> DIG_CLK8M_EN_R {
125        DIG_CLK8M_EN_R::new(((self.bits >> 10) & 1) != 0)
126    }
127    #[doc = "Bits 12:14 - divider = reg_ck8m_div_sel + 1"]
128    #[inline(always)]
129    pub fn ck8m_div_sel(&self) -> CK8M_DIV_SEL_R {
130        CK8M_DIV_SEL_R::new(((self.bits >> 12) & 7) as u8)
131    }
132    #[doc = "Bit 15 - XTAL force no gating during sleep"]
133    #[inline(always)]
134    pub fn xtal_force_nogating(&self) -> XTAL_FORCE_NOGATING_R {
135        XTAL_FORCE_NOGATING_R::new(((self.bits >> 15) & 1) != 0)
136    }
137    #[doc = "Bit 16 - CK8M force no gating during sleep"]
138    #[inline(always)]
139    pub fn ck8m_force_nogating(&self) -> CK8M_FORCE_NOGATING_R {
140        CK8M_FORCE_NOGATING_R::new(((self.bits >> 16) & 1) != 0)
141    }
142    #[doc = "Bits 17:24 - CK8M_DFREQ"]
143    #[inline(always)]
144    pub fn ck8m_dfreq(&self) -> CK8M_DFREQ_R {
145        CK8M_DFREQ_R::new(((self.bits >> 17) & 0xff) as u8)
146    }
147    #[doc = "Bit 25 - CK8M force power down"]
148    #[inline(always)]
149    pub fn ck8m_force_pd(&self) -> CK8M_FORCE_PD_R {
150        CK8M_FORCE_PD_R::new(((self.bits >> 25) & 1) != 0)
151    }
152    #[doc = "Bit 26 - CK8M force power up"]
153    #[inline(always)]
154    pub fn ck8m_force_pu(&self) -> CK8M_FORCE_PU_R {
155        CK8M_FORCE_PU_R::new(((self.bits >> 26) & 1) != 0)
156    }
157    #[doc = "Bit 27 - force enable xtal clk gating"]
158    #[inline(always)]
159    pub fn xtal_global_force_gating(&self) -> XTAL_GLOBAL_FORCE_GATING_R {
160        XTAL_GLOBAL_FORCE_GATING_R::new(((self.bits >> 27) & 1) != 0)
161    }
162    #[doc = "Bit 28 - force bypass xtal clk gating"]
163    #[inline(always)]
164    pub fn xtal_global_force_nogating(&self) -> XTAL_GLOBAL_FORCE_NOGATING_R {
165        XTAL_GLOBAL_FORCE_NOGATING_R::new(((self.bits >> 28) & 1) != 0)
166    }
167    #[doc = "Bit 29 - fast_clk_rtc sel. 0: XTAL div 4"]
168    #[inline(always)]
169    pub fn fast_clk_rtc_sel(&self) -> FAST_CLK_RTC_SEL_R {
170        FAST_CLK_RTC_SEL_R::new(((self.bits >> 29) & 1) != 0)
171    }
172    #[doc = "Bits 30:31 - slelect rtc slow clk"]
173    #[inline(always)]
174    pub fn ana_clk_rtc_sel(&self) -> ANA_CLK_RTC_SEL_R {
175        ANA_CLK_RTC_SEL_R::new(((self.bits >> 30) & 3) as u8)
176    }
177}
178#[cfg(feature = "impl-register-debug")]
179impl core::fmt::Debug for R {
180    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
181        f.debug_struct("CLK_CONF")
182            .field("efuse_clk_force_gating", &self.efuse_clk_force_gating())
183            .field("efuse_clk_force_nogating", &self.efuse_clk_force_nogating())
184            .field("ck8m_div_sel_vld", &self.ck8m_div_sel_vld())
185            .field("ck8m_div", &self.ck8m_div())
186            .field("enb_ck8m", &self.enb_ck8m())
187            .field("enb_ck8m_div", &self.enb_ck8m_div())
188            .field("dig_xtal32k_en", &self.dig_xtal32k_en())
189            .field("dig_clk8m_d256_en", &self.dig_clk8m_d256_en())
190            .field("dig_clk8m_en", &self.dig_clk8m_en())
191            .field("ck8m_div_sel", &self.ck8m_div_sel())
192            .field("xtal_force_nogating", &self.xtal_force_nogating())
193            .field("ck8m_force_nogating", &self.ck8m_force_nogating())
194            .field("ck8m_dfreq", &self.ck8m_dfreq())
195            .field("ck8m_force_pd", &self.ck8m_force_pd())
196            .field("ck8m_force_pu", &self.ck8m_force_pu())
197            .field("xtal_global_force_gating", &self.xtal_global_force_gating())
198            .field(
199                "xtal_global_force_nogating",
200                &self.xtal_global_force_nogating(),
201            )
202            .field("fast_clk_rtc_sel", &self.fast_clk_rtc_sel())
203            .field("ana_clk_rtc_sel", &self.ana_clk_rtc_sel())
204            .finish()
205    }
206}
207impl W {
208    #[doc = "Bit 1 - efuse_clk_force_gating"]
209    #[inline(always)]
210    pub fn efuse_clk_force_gating(&mut self) -> EFUSE_CLK_FORCE_GATING_W<CLK_CONF_SPEC> {
211        EFUSE_CLK_FORCE_GATING_W::new(self, 1)
212    }
213    #[doc = "Bit 2 - efuse_clk_force_nogating"]
214    #[inline(always)]
215    pub fn efuse_clk_force_nogating(&mut self) -> EFUSE_CLK_FORCE_NOGATING_W<CLK_CONF_SPEC> {
216        EFUSE_CLK_FORCE_NOGATING_W::new(self, 2)
217    }
218    #[doc = "Bit 3 - used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel"]
219    #[inline(always)]
220    pub fn ck8m_div_sel_vld(&mut self) -> CK8M_DIV_SEL_VLD_W<CLK_CONF_SPEC> {
221        CK8M_DIV_SEL_VLD_W::new(self, 3)
222    }
223    #[doc = "Bits 4:5 - CK8M_D256_OUT divider. 00: div128"]
224    #[inline(always)]
225    pub fn ck8m_div(&mut self) -> CK8M_DIV_W<CLK_CONF_SPEC> {
226        CK8M_DIV_W::new(self, 4)
227    }
228    #[doc = "Bit 6 - disable CK8M and CK8M_D256_OUT"]
229    #[inline(always)]
230    pub fn enb_ck8m(&mut self) -> ENB_CK8M_W<CLK_CONF_SPEC> {
231        ENB_CK8M_W::new(self, 6)
232    }
233    #[doc = "Bit 7 - 1: CK8M_D256_OUT is actually CK8M"]
234    #[inline(always)]
235    pub fn enb_ck8m_div(&mut self) -> ENB_CK8M_DIV_W<CLK_CONF_SPEC> {
236        ENB_CK8M_DIV_W::new(self, 7)
237    }
238    #[doc = "Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)"]
239    #[inline(always)]
240    pub fn dig_xtal32k_en(&mut self) -> DIG_XTAL32K_EN_W<CLK_CONF_SPEC> {
241        DIG_XTAL32K_EN_W::new(self, 8)
242    }
243    #[doc = "Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)"]
244    #[inline(always)]
245    pub fn dig_clk8m_d256_en(&mut self) -> DIG_CLK8M_D256_EN_W<CLK_CONF_SPEC> {
246        DIG_CLK8M_D256_EN_W::new(self, 9)
247    }
248    #[doc = "Bit 10 - enable CK8M for digital core (no relationship with RTC core)"]
249    #[inline(always)]
250    pub fn dig_clk8m_en(&mut self) -> DIG_CLK8M_EN_W<CLK_CONF_SPEC> {
251        DIG_CLK8M_EN_W::new(self, 10)
252    }
253    #[doc = "Bits 12:14 - divider = reg_ck8m_div_sel + 1"]
254    #[inline(always)]
255    pub fn ck8m_div_sel(&mut self) -> CK8M_DIV_SEL_W<CLK_CONF_SPEC> {
256        CK8M_DIV_SEL_W::new(self, 12)
257    }
258    #[doc = "Bit 15 - XTAL force no gating during sleep"]
259    #[inline(always)]
260    pub fn xtal_force_nogating(&mut self) -> XTAL_FORCE_NOGATING_W<CLK_CONF_SPEC> {
261        XTAL_FORCE_NOGATING_W::new(self, 15)
262    }
263    #[doc = "Bit 16 - CK8M force no gating during sleep"]
264    #[inline(always)]
265    pub fn ck8m_force_nogating(&mut self) -> CK8M_FORCE_NOGATING_W<CLK_CONF_SPEC> {
266        CK8M_FORCE_NOGATING_W::new(self, 16)
267    }
268    #[doc = "Bits 17:24 - CK8M_DFREQ"]
269    #[inline(always)]
270    pub fn ck8m_dfreq(&mut self) -> CK8M_DFREQ_W<CLK_CONF_SPEC> {
271        CK8M_DFREQ_W::new(self, 17)
272    }
273    #[doc = "Bit 25 - CK8M force power down"]
274    #[inline(always)]
275    pub fn ck8m_force_pd(&mut self) -> CK8M_FORCE_PD_W<CLK_CONF_SPEC> {
276        CK8M_FORCE_PD_W::new(self, 25)
277    }
278    #[doc = "Bit 26 - CK8M force power up"]
279    #[inline(always)]
280    pub fn ck8m_force_pu(&mut self) -> CK8M_FORCE_PU_W<CLK_CONF_SPEC> {
281        CK8M_FORCE_PU_W::new(self, 26)
282    }
283    #[doc = "Bit 27 - force enable xtal clk gating"]
284    #[inline(always)]
285    pub fn xtal_global_force_gating(&mut self) -> XTAL_GLOBAL_FORCE_GATING_W<CLK_CONF_SPEC> {
286        XTAL_GLOBAL_FORCE_GATING_W::new(self, 27)
287    }
288    #[doc = "Bit 28 - force bypass xtal clk gating"]
289    #[inline(always)]
290    pub fn xtal_global_force_nogating(&mut self) -> XTAL_GLOBAL_FORCE_NOGATING_W<CLK_CONF_SPEC> {
291        XTAL_GLOBAL_FORCE_NOGATING_W::new(self, 28)
292    }
293    #[doc = "Bit 29 - fast_clk_rtc sel. 0: XTAL div 4"]
294    #[inline(always)]
295    pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
296        FAST_CLK_RTC_SEL_W::new(self, 29)
297    }
298    #[doc = "Bits 30:31 - slelect rtc slow clk"]
299    #[inline(always)]
300    pub fn ana_clk_rtc_sel(&mut self) -> ANA_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
301        ANA_CLK_RTC_SEL_W::new(self, 30)
302    }
303}
304#[doc = "rtc configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
305pub struct CLK_CONF_SPEC;
306impl crate::RegisterSpec for CLK_CONF_SPEC {
307    type Ux = u32;
308}
309#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"]
310impl crate::Readable for CLK_CONF_SPEC {}
311#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"]
312impl crate::Writable for CLK_CONF_SPEC {
313    type Safety = crate::Unsafe;
314}
315#[doc = "`reset()` method sets CLK_CONF to value 0x1158_3218"]
316impl crate::Resettable for CLK_CONF_SPEC {
317    const RESET_VALUE: u32 = 0x1158_3218;
318}
esp32c3/rtc_cntl/clk_conf.rs

esp32c3/rtc_cntl/
clk_conf.rs
