1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `CH_TX_END(0-1)` reader - reg_ch%s_tx_end_int_ena."]
6pub type CH_TX_END_R = crate::BitReader;
7#[doc = "Field `CH_TX_END(0-1)` writer - reg_ch%s_tx_end_int_ena."]
8pub type CH_TX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CH_RX_END(2-3)` reader - reg_ch2_rx_end_int_ena."]
10pub type CH_RX_END_R = crate::BitReader;
11#[doc = "Field `CH_RX_END(2-3)` writer - reg_ch2_rx_end_int_ena."]
12pub type CH_RX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CH_TX_ERR(0-1)` reader - reg_ch%s_err_int_ena."]
14pub type CH_TX_ERR_R = crate::BitReader;
15#[doc = "Field `CH_TX_ERR(0-1)` writer - reg_ch%s_err_int_ena."]
16pub type CH_TX_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CH_RX_ERR(2-3)` reader - reg_ch2_err_int_ena."]
18pub type CH_RX_ERR_R = crate::BitReader;
19#[doc = "Field `CH_RX_ERR(2-3)` writer - reg_ch2_err_int_ena."]
20pub type CH_RX_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CH_TX_THR_EVENT(0-1)` reader - reg_ch%s_tx_thr_event_int_ena."]
22pub type CH_TX_THR_EVENT_R = crate::BitReader;
23#[doc = "Field `CH_TX_THR_EVENT(0-1)` writer - reg_ch%s_tx_thr_event_int_ena."]
24pub type CH_TX_THR_EVENT_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CH_RX_THR_EVENT(2-3)` reader - reg_ch2_rx_thr_event_int_ena."]
26pub type CH_RX_THR_EVENT_R = crate::BitReader;
27#[doc = "Field `CH_RX_THR_EVENT(2-3)` writer - reg_ch2_rx_thr_event_int_ena."]
28pub type CH_RX_THR_EVENT_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CH_TX_LOOP(0-1)` reader - reg_ch%s_tx_loop_int_ena."]
30pub type CH_TX_LOOP_R = crate::BitReader;
31#[doc = "Field `CH_TX_LOOP(0-1)` writer - reg_ch%s_tx_loop_int_ena."]
32pub type CH_TX_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34 #[doc = "reg_ch(0-1)_tx_end_int_ena."]
35 #[doc = ""]
36 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
37 #[inline(always)]
38 pub fn ch_tx_end(&self, n: u8) -> CH_TX_END_R {
39 #[allow(clippy::no_effect)]
40 [(); 2][n as usize];
41 CH_TX_END_R::new(((self.bits >> n) & 1) != 0)
42 }
43 #[doc = "Iterator for array of:"]
44 #[doc = "reg_ch(0-1)_tx_end_int_ena."]
45 #[inline(always)]
46 pub fn ch_tx_end_iter(&self) -> impl Iterator<Item = CH_TX_END_R> + '_ {
47 (0..2).map(move |n| CH_TX_END_R::new(((self.bits >> n) & 1) != 0))
48 }
49 #[doc = "Bit 0 - reg_ch0_tx_end_int_ena."]
50 #[inline(always)]
51 pub fn ch0_tx_end(&self) -> CH_TX_END_R {
52 CH_TX_END_R::new((self.bits & 1) != 0)
53 }
54 #[doc = "Bit 1 - reg_ch1_tx_end_int_ena."]
55 #[inline(always)]
56 pub fn ch1_tx_end(&self) -> CH_TX_END_R {
57 CH_TX_END_R::new(((self.bits >> 1) & 1) != 0)
58 }
59 #[doc = "reg_ch2_rx_end_int_ena."]
60 #[doc = ""]
61 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH2_RX_END` field.</div>"]
62 #[inline(always)]
63 pub fn ch_rx_end(&self, n: u8) -> CH_RX_END_R {
64 #[allow(clippy::no_effect)]
65 [(); 2][n as usize];
66 CH_RX_END_R::new(((self.bits >> (n + 2)) & 1) != 0)
67 }
68 #[doc = "Iterator for array of:"]
69 #[doc = "reg_ch2_rx_end_int_ena."]
70 #[inline(always)]
71 pub fn ch_rx_end_iter(&self) -> impl Iterator<Item = CH_RX_END_R> + '_ {
72 (0..2).map(move |n| CH_RX_END_R::new(((self.bits >> (n + 2)) & 1) != 0))
73 }
74 #[doc = "Bit 2 - reg_ch2_rx_end_int_ena."]
75 #[inline(always)]
76 pub fn ch2_rx_end(&self) -> CH_RX_END_R {
77 CH_RX_END_R::new(((self.bits >> 2) & 1) != 0)
78 }
79 #[doc = "Bit 3 - reg_ch2_rx_end_int_ena."]
80 #[inline(always)]
81 pub fn ch3_rx_end(&self) -> CH_RX_END_R {
82 CH_RX_END_R::new(((self.bits >> 3) & 1) != 0)
83 }
84 #[doc = "reg_ch(0-1)_err_int_ena."]
85 #[doc = ""]
86 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_ERR` field.</div>"]
87 #[inline(always)]
88 pub fn ch_tx_err(&self, n: u8) -> CH_TX_ERR_R {
89 #[allow(clippy::no_effect)]
90 [(); 2][n as usize];
91 CH_TX_ERR_R::new(((self.bits >> (n + 4)) & 1) != 0)
92 }
93 #[doc = "Iterator for array of:"]
94 #[doc = "reg_ch(0-1)_err_int_ena."]
95 #[inline(always)]
96 pub fn ch_tx_err_iter(&self) -> impl Iterator<Item = CH_TX_ERR_R> + '_ {
97 (0..2).map(move |n| CH_TX_ERR_R::new(((self.bits >> (n + 4)) & 1) != 0))
98 }
99 #[doc = "Bit 4 - reg_ch0_err_int_ena."]
100 #[inline(always)]
101 pub fn ch0_tx_err(&self) -> CH_TX_ERR_R {
102 CH_TX_ERR_R::new(((self.bits >> 4) & 1) != 0)
103 }
104 #[doc = "Bit 5 - reg_ch1_err_int_ena."]
105 #[inline(always)]
106 pub fn ch1_tx_err(&self) -> CH_TX_ERR_R {
107 CH_TX_ERR_R::new(((self.bits >> 5) & 1) != 0)
108 }
109 #[doc = "reg_ch2_err_int_ena."]
110 #[doc = ""]
111 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH2_RX_ERR` field.</div>"]
112 #[inline(always)]
113 pub fn ch_rx_err(&self, n: u8) -> CH_RX_ERR_R {
114 #[allow(clippy::no_effect)]
115 [(); 2][n as usize];
116 CH_RX_ERR_R::new(((self.bits >> (n + 6)) & 1) != 0)
117 }
118 #[doc = "Iterator for array of:"]
119 #[doc = "reg_ch2_err_int_ena."]
120 #[inline(always)]
121 pub fn ch_rx_err_iter(&self) -> impl Iterator<Item = CH_RX_ERR_R> + '_ {
122 (0..2).map(move |n| CH_RX_ERR_R::new(((self.bits >> (n + 6)) & 1) != 0))
123 }
124 #[doc = "Bit 6 - reg_ch2_err_int_ena."]
125 #[inline(always)]
126 pub fn ch2_rx_err(&self) -> CH_RX_ERR_R {
127 CH_RX_ERR_R::new(((self.bits >> 6) & 1) != 0)
128 }
129 #[doc = "Bit 7 - reg_ch2_err_int_ena."]
130 #[inline(always)]
131 pub fn ch3_rx_err(&self) -> CH_RX_ERR_R {
132 CH_RX_ERR_R::new(((self.bits >> 7) & 1) != 0)
133 }
134 #[doc = "reg_ch(0-1)_tx_thr_event_int_ena."]
135 #[doc = ""]
136 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
137 #[inline(always)]
138 pub fn ch_tx_thr_event(&self, n: u8) -> CH_TX_THR_EVENT_R {
139 #[allow(clippy::no_effect)]
140 [(); 2][n as usize];
141 CH_TX_THR_EVENT_R::new(((self.bits >> (n + 8)) & 1) != 0)
142 }
143 #[doc = "Iterator for array of:"]
144 #[doc = "reg_ch(0-1)_tx_thr_event_int_ena."]
145 #[inline(always)]
146 pub fn ch_tx_thr_event_iter(&self) -> impl Iterator<Item = CH_TX_THR_EVENT_R> + '_ {
147 (0..2).map(move |n| CH_TX_THR_EVENT_R::new(((self.bits >> (n + 8)) & 1) != 0))
148 }
149 #[doc = "Bit 8 - reg_ch0_tx_thr_event_int_ena."]
150 #[inline(always)]
151 pub fn ch0_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
152 CH_TX_THR_EVENT_R::new(((self.bits >> 8) & 1) != 0)
153 }
154 #[doc = "Bit 9 - reg_ch1_tx_thr_event_int_ena."]
155 #[inline(always)]
156 pub fn ch1_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
157 CH_TX_THR_EVENT_R::new(((self.bits >> 9) & 1) != 0)
158 }
159 #[doc = "reg_ch2_rx_thr_event_int_ena."]
160 #[doc = ""]
161 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH2_RX_THR_EVENT` field.</div>"]
162 #[inline(always)]
163 pub fn ch_rx_thr_event(&self, n: u8) -> CH_RX_THR_EVENT_R {
164 #[allow(clippy::no_effect)]
165 [(); 2][n as usize];
166 CH_RX_THR_EVENT_R::new(((self.bits >> (n + 10)) & 1) != 0)
167 }
168 #[doc = "Iterator for array of:"]
169 #[doc = "reg_ch2_rx_thr_event_int_ena."]
170 #[inline(always)]
171 pub fn ch_rx_thr_event_iter(&self) -> impl Iterator<Item = CH_RX_THR_EVENT_R> + '_ {
172 (0..2).map(move |n| CH_RX_THR_EVENT_R::new(((self.bits >> (n + 10)) & 1) != 0))
173 }
174 #[doc = "Bit 10 - reg_ch2_rx_thr_event_int_ena."]
175 #[inline(always)]
176 pub fn ch2_rx_thr_event(&self) -> CH_RX_THR_EVENT_R {
177 CH_RX_THR_EVENT_R::new(((self.bits >> 10) & 1) != 0)
178 }
179 #[doc = "Bit 11 - reg_ch2_rx_thr_event_int_ena."]
180 #[inline(always)]
181 pub fn ch3_rx_thr_event(&self) -> CH_RX_THR_EVENT_R {
182 CH_RX_THR_EVENT_R::new(((self.bits >> 11) & 1) != 0)
183 }
184 #[doc = "reg_ch(0-1)_tx_loop_int_ena."]
185 #[doc = ""]
186 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_LOOP` field.</div>"]
187 #[inline(always)]
188 pub fn ch_tx_loop(&self, n: u8) -> CH_TX_LOOP_R {
189 #[allow(clippy::no_effect)]
190 [(); 2][n as usize];
191 CH_TX_LOOP_R::new(((self.bits >> (n + 12)) & 1) != 0)
192 }
193 #[doc = "Iterator for array of:"]
194 #[doc = "reg_ch(0-1)_tx_loop_int_ena."]
195 #[inline(always)]
196 pub fn ch_tx_loop_iter(&self) -> impl Iterator<Item = CH_TX_LOOP_R> + '_ {
197 (0..2).map(move |n| CH_TX_LOOP_R::new(((self.bits >> (n + 12)) & 1) != 0))
198 }
199 #[doc = "Bit 12 - reg_ch0_tx_loop_int_ena."]
200 #[inline(always)]
201 pub fn ch0_tx_loop(&self) -> CH_TX_LOOP_R {
202 CH_TX_LOOP_R::new(((self.bits >> 12) & 1) != 0)
203 }
204 #[doc = "Bit 13 - reg_ch1_tx_loop_int_ena."]
205 #[inline(always)]
206 pub fn ch1_tx_loop(&self) -> CH_TX_LOOP_R {
207 CH_TX_LOOP_R::new(((self.bits >> 13) & 1) != 0)
208 }
209}
210#[cfg(feature = "impl-register-debug")]
211impl core::fmt::Debug for R {
212 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
213 f.debug_struct("INT_ENA")
214 .field("ch0_tx_end", &self.ch0_tx_end())
215 .field("ch1_tx_end", &self.ch1_tx_end())
216 .field("ch2_rx_end", &self.ch2_rx_end())
217 .field("ch3_rx_end", &self.ch3_rx_end())
218 .field("ch0_tx_err", &self.ch0_tx_err())
219 .field("ch1_tx_err", &self.ch1_tx_err())
220 .field("ch2_rx_err", &self.ch2_rx_err())
221 .field("ch3_rx_err", &self.ch3_rx_err())
222 .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
223 .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
224 .field("ch2_rx_thr_event", &self.ch2_rx_thr_event())
225 .field("ch3_rx_thr_event", &self.ch3_rx_thr_event())
226 .field("ch0_tx_loop", &self.ch0_tx_loop())
227 .field("ch1_tx_loop", &self.ch1_tx_loop())
228 .finish()
229 }
230}
231impl W {
232 #[doc = "reg_ch(0-1)_tx_end_int_ena."]
233 #[doc = ""]
234 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
235 #[inline(always)]
236 pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_ENA_SPEC> {
237 #[allow(clippy::no_effect)]
238 [(); 2][n as usize];
239 CH_TX_END_W::new(self, n)
240 }
241 #[doc = "Bit 0 - reg_ch0_tx_end_int_ena."]
242 #[inline(always)]
243 pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
244 CH_TX_END_W::new(self, 0)
245 }
246 #[doc = "Bit 1 - reg_ch1_tx_end_int_ena."]
247 #[inline(always)]
248 pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
249 CH_TX_END_W::new(self, 1)
250 }
251 #[doc = "reg_ch2_rx_end_int_ena."]
252 #[doc = ""]
253 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH2_RX_END` field.</div>"]
254 #[inline(always)]
255 pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_ENA_SPEC> {
256 #[allow(clippy::no_effect)]
257 [(); 2][n as usize];
258 CH_RX_END_W::new(self, n + 2)
259 }
260 #[doc = "Bit 2 - reg_ch2_rx_end_int_ena."]
261 #[inline(always)]
262 pub fn ch2_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
263 CH_RX_END_W::new(self, 2)
264 }
265 #[doc = "Bit 3 - reg_ch2_rx_end_int_ena."]
266 #[inline(always)]
267 pub fn ch3_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
268 CH_RX_END_W::new(self, 3)
269 }
270 #[doc = "reg_ch(0-1)_err_int_ena."]
271 #[doc = ""]
272 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_ERR` field.</div>"]
273 #[inline(always)]
274 pub fn ch_tx_err(&mut self, n: u8) -> CH_TX_ERR_W<INT_ENA_SPEC> {
275 #[allow(clippy::no_effect)]
276 [(); 2][n as usize];
277 CH_TX_ERR_W::new(self, n + 4)
278 }
279 #[doc = "Bit 4 - reg_ch0_err_int_ena."]
280 #[inline(always)]
281 pub fn ch0_tx_err(&mut self) -> CH_TX_ERR_W<INT_ENA_SPEC> {
282 CH_TX_ERR_W::new(self, 4)
283 }
284 #[doc = "Bit 5 - reg_ch1_err_int_ena."]
285 #[inline(always)]
286 pub fn ch1_tx_err(&mut self) -> CH_TX_ERR_W<INT_ENA_SPEC> {
287 CH_TX_ERR_W::new(self, 5)
288 }
289 #[doc = "reg_ch2_err_int_ena."]
290 #[doc = ""]
291 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH2_RX_ERR` field.</div>"]
292 #[inline(always)]
293 pub fn ch_rx_err(&mut self, n: u8) -> CH_RX_ERR_W<INT_ENA_SPEC> {
294 #[allow(clippy::no_effect)]
295 [(); 2][n as usize];
296 CH_RX_ERR_W::new(self, n + 6)
297 }
298 #[doc = "Bit 6 - reg_ch2_err_int_ena."]
299 #[inline(always)]
300 pub fn ch2_rx_err(&mut self) -> CH_RX_ERR_W<INT_ENA_SPEC> {
301 CH_RX_ERR_W::new(self, 6)
302 }
303 #[doc = "Bit 7 - reg_ch2_err_int_ena."]
304 #[inline(always)]
305 pub fn ch3_rx_err(&mut self) -> CH_RX_ERR_W<INT_ENA_SPEC> {
306 CH_RX_ERR_W::new(self, 7)
307 }
308 #[doc = "reg_ch(0-1)_tx_thr_event_int_ena."]
309 #[doc = ""]
310 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
311 #[inline(always)]
312 pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
313 #[allow(clippy::no_effect)]
314 [(); 2][n as usize];
315 CH_TX_THR_EVENT_W::new(self, n + 8)
316 }
317 #[doc = "Bit 8 - reg_ch0_tx_thr_event_int_ena."]
318 #[inline(always)]
319 pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
320 CH_TX_THR_EVENT_W::new(self, 8)
321 }
322 #[doc = "Bit 9 - reg_ch1_tx_thr_event_int_ena."]
323 #[inline(always)]
324 pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
325 CH_TX_THR_EVENT_W::new(self, 9)
326 }
327 #[doc = "reg_ch2_rx_thr_event_int_ena."]
328 #[doc = ""]
329 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH2_RX_THR_EVENT` field.</div>"]
330 #[inline(always)]
331 pub fn ch_rx_thr_event(&mut self, n: u8) -> CH_RX_THR_EVENT_W<INT_ENA_SPEC> {
332 #[allow(clippy::no_effect)]
333 [(); 2][n as usize];
334 CH_RX_THR_EVENT_W::new(self, n + 10)
335 }
336 #[doc = "Bit 10 - reg_ch2_rx_thr_event_int_ena."]
337 #[inline(always)]
338 pub fn ch2_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_ENA_SPEC> {
339 CH_RX_THR_EVENT_W::new(self, 10)
340 }
341 #[doc = "Bit 11 - reg_ch2_rx_thr_event_int_ena."]
342 #[inline(always)]
343 pub fn ch3_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_ENA_SPEC> {
344 CH_RX_THR_EVENT_W::new(self, 11)
345 }
346 #[doc = "reg_ch(0-1)_tx_loop_int_ena."]
347 #[doc = ""]
348 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_LOOP` field.</div>"]
349 #[inline(always)]
350 pub fn ch_tx_loop(&mut self, n: u8) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
351 #[allow(clippy::no_effect)]
352 [(); 2][n as usize];
353 CH_TX_LOOP_W::new(self, n + 12)
354 }
355 #[doc = "Bit 12 - reg_ch0_tx_loop_int_ena."]
356 #[inline(always)]
357 pub fn ch0_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
358 CH_TX_LOOP_W::new(self, 12)
359 }
360 #[doc = "Bit 13 - reg_ch1_tx_loop_int_ena."]
361 #[inline(always)]
362 pub fn ch1_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
363 CH_TX_LOOP_W::new(self, 13)
364 }
365}
366#[doc = "RMT_INT_ENA_REG.\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
367pub struct INT_ENA_SPEC;
368impl crate::RegisterSpec for INT_ENA_SPEC {
369 type Ux = u32;
370}
371#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
372impl crate::Readable for INT_ENA_SPEC {}
373#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
374impl crate::Writable for INT_ENA_SPEC {
375 type Safety = crate::Unsafe;
376 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
377 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
378}
379#[doc = "`reset()` method sets INT_ENA to value 0"]
380impl crate::Resettable for INT_ENA_SPEC {
381 const RESET_VALUE: u32 = 0;
382}