esp32c3/system/
perip_clk_en0.rs

1#[doc = "Register `PERIP_CLK_EN0` reader"]
2pub type R = crate::R<PERIP_CLK_EN0_SPEC>;
3#[doc = "Register `PERIP_CLK_EN0` writer"]
4pub type W = crate::W<PERIP_CLK_EN0_SPEC>;
5#[doc = "Field `TIMERS_CLK_EN` reader - reg_timers_clk_en"]
6pub type TIMERS_CLK_EN_R = crate::BitReader;
7#[doc = "Field `TIMERS_CLK_EN` writer - reg_timers_clk_en"]
8pub type TIMERS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SPI01_CLK_EN` reader - reg_spi01_clk_en"]
10pub type SPI01_CLK_EN_R = crate::BitReader;
11#[doc = "Field `SPI01_CLK_EN` writer - reg_spi01_clk_en"]
12pub type SPI01_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `UART_CLK_EN` reader - reg_uart_clk_en"]
14pub type UART_CLK_EN_R = crate::BitReader;
15#[doc = "Field `UART_CLK_EN` writer - reg_uart_clk_en"]
16pub type UART_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `WDG_CLK_EN` reader - reg_wdg_clk_en"]
18pub type WDG_CLK_EN_R = crate::BitReader;
19#[doc = "Field `WDG_CLK_EN` writer - reg_wdg_clk_en"]
20pub type WDG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `UART1_CLK_EN` reader - reg_uart1_clk_en"]
22pub type UART1_CLK_EN_R = crate::BitReader;
23#[doc = "Field `UART1_CLK_EN` writer - reg_uart1_clk_en"]
24pub type UART1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SPI2_CLK_EN` reader - reg_spi2_clk_en"]
26pub type SPI2_CLK_EN_R = crate::BitReader;
27#[doc = "Field `SPI2_CLK_EN` writer - reg_spi2_clk_en"]
28pub type SPI2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `I2C_EXT0_CLK_EN` reader - reg_ext0_clk_en"]
30pub type I2C_EXT0_CLK_EN_R = crate::BitReader;
31#[doc = "Field `I2C_EXT0_CLK_EN` writer - reg_ext0_clk_en"]
32pub type I2C_EXT0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `UHCI0_CLK_EN` reader - reg_uhci0_clk_en"]
34pub type UHCI0_CLK_EN_R = crate::BitReader;
35#[doc = "Field `UHCI0_CLK_EN` writer - reg_uhci0_clk_en"]
36pub type UHCI0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `RMT_CLK_EN` reader - reg_rmt_clk_en"]
38pub type RMT_CLK_EN_R = crate::BitReader;
39#[doc = "Field `RMT_CLK_EN` writer - reg_rmt_clk_en"]
40pub type RMT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `PCNT_CLK_EN` reader - reg_pcnt_clk_en"]
42pub type PCNT_CLK_EN_R = crate::BitReader;
43#[doc = "Field `PCNT_CLK_EN` writer - reg_pcnt_clk_en"]
44pub type PCNT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `LEDC_CLK_EN` reader - reg_ledc_clk_en"]
46pub type LEDC_CLK_EN_R = crate::BitReader;
47#[doc = "Field `LEDC_CLK_EN` writer - reg_ledc_clk_en"]
48pub type LEDC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `UHCI1_CLK_EN` reader - reg_uhci1_clk_en"]
50pub type UHCI1_CLK_EN_R = crate::BitReader;
51#[doc = "Field `UHCI1_CLK_EN` writer - reg_uhci1_clk_en"]
52pub type UHCI1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `TIMERGROUP_CLK_EN` reader - reg_timergroup_clk_en"]
54pub type TIMERGROUP_CLK_EN_R = crate::BitReader;
55#[doc = "Field `TIMERGROUP_CLK_EN` writer - reg_timergroup_clk_en"]
56pub type TIMERGROUP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `EFUSE_CLK_EN` reader - reg_efuse_clk_en"]
58pub type EFUSE_CLK_EN_R = crate::BitReader;
59#[doc = "Field `EFUSE_CLK_EN` writer - reg_efuse_clk_en"]
60pub type EFUSE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `TIMERGROUP1_CLK_EN` reader - reg_timergroup1_clk_en"]
62pub type TIMERGROUP1_CLK_EN_R = crate::BitReader;
63#[doc = "Field `TIMERGROUP1_CLK_EN` writer - reg_timergroup1_clk_en"]
64pub type TIMERGROUP1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `SPI3_CLK_EN` reader - reg_spi3_clk_en"]
66pub type SPI3_CLK_EN_R = crate::BitReader;
67#[doc = "Field `SPI3_CLK_EN` writer - reg_spi3_clk_en"]
68pub type SPI3_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `PWM0_CLK_EN` reader - reg_pwm0_clk_en"]
70pub type PWM0_CLK_EN_R = crate::BitReader;
71#[doc = "Field `PWM0_CLK_EN` writer - reg_pwm0_clk_en"]
72pub type PWM0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `EXT1_CLK_EN` reader - reg_ext1_clk_en"]
74pub type EXT1_CLK_EN_R = crate::BitReader;
75#[doc = "Field `EXT1_CLK_EN` writer - reg_ext1_clk_en"]
76pub type EXT1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `TWAI_CLK_EN` reader - reg_can_clk_en"]
78pub type TWAI_CLK_EN_R = crate::BitReader;
79#[doc = "Field `TWAI_CLK_EN` writer - reg_can_clk_en"]
80pub type TWAI_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `PWM1_CLK_EN` reader - reg_pwm1_clk_en"]
82pub type PWM1_CLK_EN_R = crate::BitReader;
83#[doc = "Field `PWM1_CLK_EN` writer - reg_pwm1_clk_en"]
84pub type PWM1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `I2S0_CLK_EN` reader - reg_i2s1_clk_en"]
86pub type I2S0_CLK_EN_R = crate::BitReader;
87#[doc = "Field `I2S0_CLK_EN` writer - reg_i2s1_clk_en"]
88pub type I2S0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `SPI2_DMA_CLK_EN` reader - reg_spi2_dma_clk_en"]
90pub type SPI2_DMA_CLK_EN_R = crate::BitReader;
91#[doc = "Field `SPI2_DMA_CLK_EN` writer - reg_spi2_dma_clk_en"]
92pub type SPI2_DMA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `USB_DEVICE_CLK_EN` reader - reg_usb_device_clk_en"]
94pub type USB_DEVICE_CLK_EN_R = crate::BitReader;
95#[doc = "Field `USB_DEVICE_CLK_EN` writer - reg_usb_device_clk_en"]
96pub type USB_DEVICE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `UART_MEM_CLK_EN` reader - reg_uart_mem_clk_en"]
98pub type UART_MEM_CLK_EN_R = crate::BitReader;
99#[doc = "Field `UART_MEM_CLK_EN` writer - reg_uart_mem_clk_en"]
100pub type UART_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `PWM2_CLK_EN` reader - reg_pwm2_clk_en"]
102pub type PWM2_CLK_EN_R = crate::BitReader;
103#[doc = "Field `PWM2_CLK_EN` writer - reg_pwm2_clk_en"]
104pub type PWM2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `PWM3_CLK_EN` reader - reg_pwm3_clk_en"]
106pub type PWM3_CLK_EN_R = crate::BitReader;
107#[doc = "Field `PWM3_CLK_EN` writer - reg_pwm3_clk_en"]
108pub type PWM3_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `SPI3_DMA_CLK_EN` reader - reg_spi3_dma_clk_en"]
110pub type SPI3_DMA_CLK_EN_R = crate::BitReader;
111#[doc = "Field `SPI3_DMA_CLK_EN` writer - reg_spi3_dma_clk_en"]
112pub type SPI3_DMA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
113#[doc = "Field `APB_SARADC_CLK_EN` reader - reg_apb_saradc_clk_en"]
114pub type APB_SARADC_CLK_EN_R = crate::BitReader;
115#[doc = "Field `APB_SARADC_CLK_EN` writer - reg_apb_saradc_clk_en"]
116pub type APB_SARADC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
117#[doc = "Field `SYSTIMER_CLK_EN` reader - reg_systimer_clk_en"]
118pub type SYSTIMER_CLK_EN_R = crate::BitReader;
119#[doc = "Field `SYSTIMER_CLK_EN` writer - reg_systimer_clk_en"]
120pub type SYSTIMER_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
121#[doc = "Field `ADC2_ARB_CLK_EN` reader - reg_adc2_arb_clk_en"]
122pub type ADC2_ARB_CLK_EN_R = crate::BitReader;
123#[doc = "Field `ADC2_ARB_CLK_EN` writer - reg_adc2_arb_clk_en"]
124pub type ADC2_ARB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
125#[doc = "Field `SPI4_CLK_EN` reader - reg_spi4_clk_en"]
126pub type SPI4_CLK_EN_R = crate::BitReader;
127#[doc = "Field `SPI4_CLK_EN` writer - reg_spi4_clk_en"]
128pub type SPI4_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
129impl R {
130    #[doc = "Bit 0 - reg_timers_clk_en"]
131    #[inline(always)]
132    pub fn timers_clk_en(&self) -> TIMERS_CLK_EN_R {
133        TIMERS_CLK_EN_R::new((self.bits & 1) != 0)
134    }
135    #[doc = "Bit 1 - reg_spi01_clk_en"]
136    #[inline(always)]
137    pub fn spi01_clk_en(&self) -> SPI01_CLK_EN_R {
138        SPI01_CLK_EN_R::new(((self.bits >> 1) & 1) != 0)
139    }
140    #[doc = "Bit 2 - reg_uart_clk_en"]
141    #[inline(always)]
142    pub fn uart_clk_en(&self) -> UART_CLK_EN_R {
143        UART_CLK_EN_R::new(((self.bits >> 2) & 1) != 0)
144    }
145    #[doc = "Bit 3 - reg_wdg_clk_en"]
146    #[inline(always)]
147    pub fn wdg_clk_en(&self) -> WDG_CLK_EN_R {
148        WDG_CLK_EN_R::new(((self.bits >> 3) & 1) != 0)
149    }
150    #[doc = "Bit 5 - reg_uart1_clk_en"]
151    #[inline(always)]
152    pub fn uart1_clk_en(&self) -> UART1_CLK_EN_R {
153        UART1_CLK_EN_R::new(((self.bits >> 5) & 1) != 0)
154    }
155    #[doc = "Bit 6 - reg_spi2_clk_en"]
156    #[inline(always)]
157    pub fn spi2_clk_en(&self) -> SPI2_CLK_EN_R {
158        SPI2_CLK_EN_R::new(((self.bits >> 6) & 1) != 0)
159    }
160    #[doc = "Bit 7 - reg_ext0_clk_en"]
161    #[inline(always)]
162    pub fn i2c_ext0_clk_en(&self) -> I2C_EXT0_CLK_EN_R {
163        I2C_EXT0_CLK_EN_R::new(((self.bits >> 7) & 1) != 0)
164    }
165    #[doc = "Bit 8 - reg_uhci0_clk_en"]
166    #[inline(always)]
167    pub fn uhci0_clk_en(&self) -> UHCI0_CLK_EN_R {
168        UHCI0_CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
169    }
170    #[doc = "Bit 9 - reg_rmt_clk_en"]
171    #[inline(always)]
172    pub fn rmt_clk_en(&self) -> RMT_CLK_EN_R {
173        RMT_CLK_EN_R::new(((self.bits >> 9) & 1) != 0)
174    }
175    #[doc = "Bit 10 - reg_pcnt_clk_en"]
176    #[inline(always)]
177    pub fn pcnt_clk_en(&self) -> PCNT_CLK_EN_R {
178        PCNT_CLK_EN_R::new(((self.bits >> 10) & 1) != 0)
179    }
180    #[doc = "Bit 11 - reg_ledc_clk_en"]
181    #[inline(always)]
182    pub fn ledc_clk_en(&self) -> LEDC_CLK_EN_R {
183        LEDC_CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
184    }
185    #[doc = "Bit 12 - reg_uhci1_clk_en"]
186    #[inline(always)]
187    pub fn uhci1_clk_en(&self) -> UHCI1_CLK_EN_R {
188        UHCI1_CLK_EN_R::new(((self.bits >> 12) & 1) != 0)
189    }
190    #[doc = "Bit 13 - reg_timergroup_clk_en"]
191    #[inline(always)]
192    pub fn timergroup_clk_en(&self) -> TIMERGROUP_CLK_EN_R {
193        TIMERGROUP_CLK_EN_R::new(((self.bits >> 13) & 1) != 0)
194    }
195    #[doc = "Bit 14 - reg_efuse_clk_en"]
196    #[inline(always)]
197    pub fn efuse_clk_en(&self) -> EFUSE_CLK_EN_R {
198        EFUSE_CLK_EN_R::new(((self.bits >> 14) & 1) != 0)
199    }
200    #[doc = "Bit 15 - reg_timergroup1_clk_en"]
201    #[inline(always)]
202    pub fn timergroup1_clk_en(&self) -> TIMERGROUP1_CLK_EN_R {
203        TIMERGROUP1_CLK_EN_R::new(((self.bits >> 15) & 1) != 0)
204    }
205    #[doc = "Bit 16 - reg_spi3_clk_en"]
206    #[inline(always)]
207    pub fn spi3_clk_en(&self) -> SPI3_CLK_EN_R {
208        SPI3_CLK_EN_R::new(((self.bits >> 16) & 1) != 0)
209    }
210    #[doc = "Bit 17 - reg_pwm0_clk_en"]
211    #[inline(always)]
212    pub fn pwm0_clk_en(&self) -> PWM0_CLK_EN_R {
213        PWM0_CLK_EN_R::new(((self.bits >> 17) & 1) != 0)
214    }
215    #[doc = "Bit 18 - reg_ext1_clk_en"]
216    #[inline(always)]
217    pub fn ext1_clk_en(&self) -> EXT1_CLK_EN_R {
218        EXT1_CLK_EN_R::new(((self.bits >> 18) & 1) != 0)
219    }
220    #[doc = "Bit 19 - reg_can_clk_en"]
221    #[inline(always)]
222    pub fn twai_clk_en(&self) -> TWAI_CLK_EN_R {
223        TWAI_CLK_EN_R::new(((self.bits >> 19) & 1) != 0)
224    }
225    #[doc = "Bit 20 - reg_pwm1_clk_en"]
226    #[inline(always)]
227    pub fn pwm1_clk_en(&self) -> PWM1_CLK_EN_R {
228        PWM1_CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
229    }
230    #[doc = "Bit 21 - reg_i2s1_clk_en"]
231    #[inline(always)]
232    pub fn i2s0_clk_en(&self) -> I2S0_CLK_EN_R {
233        I2S0_CLK_EN_R::new(((self.bits >> 21) & 1) != 0)
234    }
235    #[doc = "Bit 22 - reg_spi2_dma_clk_en"]
236    #[inline(always)]
237    pub fn spi2_dma_clk_en(&self) -> SPI2_DMA_CLK_EN_R {
238        SPI2_DMA_CLK_EN_R::new(((self.bits >> 22) & 1) != 0)
239    }
240    #[doc = "Bit 23 - reg_usb_device_clk_en"]
241    #[inline(always)]
242    pub fn usb_device_clk_en(&self) -> USB_DEVICE_CLK_EN_R {
243        USB_DEVICE_CLK_EN_R::new(((self.bits >> 23) & 1) != 0)
244    }
245    #[doc = "Bit 24 - reg_uart_mem_clk_en"]
246    #[inline(always)]
247    pub fn uart_mem_clk_en(&self) -> UART_MEM_CLK_EN_R {
248        UART_MEM_CLK_EN_R::new(((self.bits >> 24) & 1) != 0)
249    }
250    #[doc = "Bit 25 - reg_pwm2_clk_en"]
251    #[inline(always)]
252    pub fn pwm2_clk_en(&self) -> PWM2_CLK_EN_R {
253        PWM2_CLK_EN_R::new(((self.bits >> 25) & 1) != 0)
254    }
255    #[doc = "Bit 26 - reg_pwm3_clk_en"]
256    #[inline(always)]
257    pub fn pwm3_clk_en(&self) -> PWM3_CLK_EN_R {
258        PWM3_CLK_EN_R::new(((self.bits >> 26) & 1) != 0)
259    }
260    #[doc = "Bit 27 - reg_spi3_dma_clk_en"]
261    #[inline(always)]
262    pub fn spi3_dma_clk_en(&self) -> SPI3_DMA_CLK_EN_R {
263        SPI3_DMA_CLK_EN_R::new(((self.bits >> 27) & 1) != 0)
264    }
265    #[doc = "Bit 28 - reg_apb_saradc_clk_en"]
266    #[inline(always)]
267    pub fn apb_saradc_clk_en(&self) -> APB_SARADC_CLK_EN_R {
268        APB_SARADC_CLK_EN_R::new(((self.bits >> 28) & 1) != 0)
269    }
270    #[doc = "Bit 29 - reg_systimer_clk_en"]
271    #[inline(always)]
272    pub fn systimer_clk_en(&self) -> SYSTIMER_CLK_EN_R {
273        SYSTIMER_CLK_EN_R::new(((self.bits >> 29) & 1) != 0)
274    }
275    #[doc = "Bit 30 - reg_adc2_arb_clk_en"]
276    #[inline(always)]
277    pub fn adc2_arb_clk_en(&self) -> ADC2_ARB_CLK_EN_R {
278        ADC2_ARB_CLK_EN_R::new(((self.bits >> 30) & 1) != 0)
279    }
280    #[doc = "Bit 31 - reg_spi4_clk_en"]
281    #[inline(always)]
282    pub fn spi4_clk_en(&self) -> SPI4_CLK_EN_R {
283        SPI4_CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
284    }
285}
286#[cfg(feature = "impl-register-debug")]
287impl core::fmt::Debug for R {
288    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
289        f.debug_struct("PERIP_CLK_EN0")
290            .field("timers_clk_en", &self.timers_clk_en())
291            .field("spi01_clk_en", &self.spi01_clk_en())
292            .field("uart_clk_en", &self.uart_clk_en())
293            .field("wdg_clk_en", &self.wdg_clk_en())
294            .field("uart1_clk_en", &self.uart1_clk_en())
295            .field("spi2_clk_en", &self.spi2_clk_en())
296            .field("i2c_ext0_clk_en", &self.i2c_ext0_clk_en())
297            .field("uhci0_clk_en", &self.uhci0_clk_en())
298            .field("rmt_clk_en", &self.rmt_clk_en())
299            .field("pcnt_clk_en", &self.pcnt_clk_en())
300            .field("ledc_clk_en", &self.ledc_clk_en())
301            .field("uhci1_clk_en", &self.uhci1_clk_en())
302            .field("timergroup_clk_en", &self.timergroup_clk_en())
303            .field("efuse_clk_en", &self.efuse_clk_en())
304            .field("timergroup1_clk_en", &self.timergroup1_clk_en())
305            .field("spi3_clk_en", &self.spi3_clk_en())
306            .field("pwm0_clk_en", &self.pwm0_clk_en())
307            .field("ext1_clk_en", &self.ext1_clk_en())
308            .field("twai_clk_en", &self.twai_clk_en())
309            .field("pwm1_clk_en", &self.pwm1_clk_en())
310            .field("i2s0_clk_en", &self.i2s0_clk_en())
311            .field("spi2_dma_clk_en", &self.spi2_dma_clk_en())
312            .field("usb_device_clk_en", &self.usb_device_clk_en())
313            .field("uart_mem_clk_en", &self.uart_mem_clk_en())
314            .field("pwm2_clk_en", &self.pwm2_clk_en())
315            .field("pwm3_clk_en", &self.pwm3_clk_en())
316            .field("spi3_dma_clk_en", &self.spi3_dma_clk_en())
317            .field("apb_saradc_clk_en", &self.apb_saradc_clk_en())
318            .field("systimer_clk_en", &self.systimer_clk_en())
319            .field("adc2_arb_clk_en", &self.adc2_arb_clk_en())
320            .field("spi4_clk_en", &self.spi4_clk_en())
321            .finish()
322    }
323}
324impl W {
325    #[doc = "Bit 0 - reg_timers_clk_en"]
326    #[inline(always)]
327    pub fn timers_clk_en(&mut self) -> TIMERS_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
328        TIMERS_CLK_EN_W::new(self, 0)
329    }
330    #[doc = "Bit 1 - reg_spi01_clk_en"]
331    #[inline(always)]
332    pub fn spi01_clk_en(&mut self) -> SPI01_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
333        SPI01_CLK_EN_W::new(self, 1)
334    }
335    #[doc = "Bit 2 - reg_uart_clk_en"]
336    #[inline(always)]
337    pub fn uart_clk_en(&mut self) -> UART_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
338        UART_CLK_EN_W::new(self, 2)
339    }
340    #[doc = "Bit 3 - reg_wdg_clk_en"]
341    #[inline(always)]
342    pub fn wdg_clk_en(&mut self) -> WDG_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
343        WDG_CLK_EN_W::new(self, 3)
344    }
345    #[doc = "Bit 5 - reg_uart1_clk_en"]
346    #[inline(always)]
347    pub fn uart1_clk_en(&mut self) -> UART1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
348        UART1_CLK_EN_W::new(self, 5)
349    }
350    #[doc = "Bit 6 - reg_spi2_clk_en"]
351    #[inline(always)]
352    pub fn spi2_clk_en(&mut self) -> SPI2_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
353        SPI2_CLK_EN_W::new(self, 6)
354    }
355    #[doc = "Bit 7 - reg_ext0_clk_en"]
356    #[inline(always)]
357    pub fn i2c_ext0_clk_en(&mut self) -> I2C_EXT0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
358        I2C_EXT0_CLK_EN_W::new(self, 7)
359    }
360    #[doc = "Bit 8 - reg_uhci0_clk_en"]
361    #[inline(always)]
362    pub fn uhci0_clk_en(&mut self) -> UHCI0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
363        UHCI0_CLK_EN_W::new(self, 8)
364    }
365    #[doc = "Bit 9 - reg_rmt_clk_en"]
366    #[inline(always)]
367    pub fn rmt_clk_en(&mut self) -> RMT_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
368        RMT_CLK_EN_W::new(self, 9)
369    }
370    #[doc = "Bit 10 - reg_pcnt_clk_en"]
371    #[inline(always)]
372    pub fn pcnt_clk_en(&mut self) -> PCNT_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
373        PCNT_CLK_EN_W::new(self, 10)
374    }
375    #[doc = "Bit 11 - reg_ledc_clk_en"]
376    #[inline(always)]
377    pub fn ledc_clk_en(&mut self) -> LEDC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
378        LEDC_CLK_EN_W::new(self, 11)
379    }
380    #[doc = "Bit 12 - reg_uhci1_clk_en"]
381    #[inline(always)]
382    pub fn uhci1_clk_en(&mut self) -> UHCI1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
383        UHCI1_CLK_EN_W::new(self, 12)
384    }
385    #[doc = "Bit 13 - reg_timergroup_clk_en"]
386    #[inline(always)]
387    pub fn timergroup_clk_en(&mut self) -> TIMERGROUP_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
388        TIMERGROUP_CLK_EN_W::new(self, 13)
389    }
390    #[doc = "Bit 14 - reg_efuse_clk_en"]
391    #[inline(always)]
392    pub fn efuse_clk_en(&mut self) -> EFUSE_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
393        EFUSE_CLK_EN_W::new(self, 14)
394    }
395    #[doc = "Bit 15 - reg_timergroup1_clk_en"]
396    #[inline(always)]
397    pub fn timergroup1_clk_en(&mut self) -> TIMERGROUP1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
398        TIMERGROUP1_CLK_EN_W::new(self, 15)
399    }
400    #[doc = "Bit 16 - reg_spi3_clk_en"]
401    #[inline(always)]
402    pub fn spi3_clk_en(&mut self) -> SPI3_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
403        SPI3_CLK_EN_W::new(self, 16)
404    }
405    #[doc = "Bit 17 - reg_pwm0_clk_en"]
406    #[inline(always)]
407    pub fn pwm0_clk_en(&mut self) -> PWM0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
408        PWM0_CLK_EN_W::new(self, 17)
409    }
410    #[doc = "Bit 18 - reg_ext1_clk_en"]
411    #[inline(always)]
412    pub fn ext1_clk_en(&mut self) -> EXT1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
413        EXT1_CLK_EN_W::new(self, 18)
414    }
415    #[doc = "Bit 19 - reg_can_clk_en"]
416    #[inline(always)]
417    pub fn twai_clk_en(&mut self) -> TWAI_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
418        TWAI_CLK_EN_W::new(self, 19)
419    }
420    #[doc = "Bit 20 - reg_pwm1_clk_en"]
421    #[inline(always)]
422    pub fn pwm1_clk_en(&mut self) -> PWM1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
423        PWM1_CLK_EN_W::new(self, 20)
424    }
425    #[doc = "Bit 21 - reg_i2s1_clk_en"]
426    #[inline(always)]
427    pub fn i2s0_clk_en(&mut self) -> I2S0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
428        I2S0_CLK_EN_W::new(self, 21)
429    }
430    #[doc = "Bit 22 - reg_spi2_dma_clk_en"]
431    #[inline(always)]
432    pub fn spi2_dma_clk_en(&mut self) -> SPI2_DMA_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
433        SPI2_DMA_CLK_EN_W::new(self, 22)
434    }
435    #[doc = "Bit 23 - reg_usb_device_clk_en"]
436    #[inline(always)]
437    pub fn usb_device_clk_en(&mut self) -> USB_DEVICE_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
438        USB_DEVICE_CLK_EN_W::new(self, 23)
439    }
440    #[doc = "Bit 24 - reg_uart_mem_clk_en"]
441    #[inline(always)]
442    pub fn uart_mem_clk_en(&mut self) -> UART_MEM_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
443        UART_MEM_CLK_EN_W::new(self, 24)
444    }
445    #[doc = "Bit 25 - reg_pwm2_clk_en"]
446    #[inline(always)]
447    pub fn pwm2_clk_en(&mut self) -> PWM2_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
448        PWM2_CLK_EN_W::new(self, 25)
449    }
450    #[doc = "Bit 26 - reg_pwm3_clk_en"]
451    #[inline(always)]
452    pub fn pwm3_clk_en(&mut self) -> PWM3_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
453        PWM3_CLK_EN_W::new(self, 26)
454    }
455    #[doc = "Bit 27 - reg_spi3_dma_clk_en"]
456    #[inline(always)]
457    pub fn spi3_dma_clk_en(&mut self) -> SPI3_DMA_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
458        SPI3_DMA_CLK_EN_W::new(self, 27)
459    }
460    #[doc = "Bit 28 - reg_apb_saradc_clk_en"]
461    #[inline(always)]
462    pub fn apb_saradc_clk_en(&mut self) -> APB_SARADC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
463        APB_SARADC_CLK_EN_W::new(self, 28)
464    }
465    #[doc = "Bit 29 - reg_systimer_clk_en"]
466    #[inline(always)]
467    pub fn systimer_clk_en(&mut self) -> SYSTIMER_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
468        SYSTIMER_CLK_EN_W::new(self, 29)
469    }
470    #[doc = "Bit 30 - reg_adc2_arb_clk_en"]
471    #[inline(always)]
472    pub fn adc2_arb_clk_en(&mut self) -> ADC2_ARB_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
473        ADC2_ARB_CLK_EN_W::new(self, 30)
474    }
475    #[doc = "Bit 31 - reg_spi4_clk_en"]
476    #[inline(always)]
477    pub fn spi4_clk_en(&mut self) -> SPI4_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
478        SPI4_CLK_EN_W::new(self, 31)
479    }
480}
481#[doc = "peripheral clock gating register\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_clk_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_clk_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
482pub struct PERIP_CLK_EN0_SPEC;
483impl crate::RegisterSpec for PERIP_CLK_EN0_SPEC {
484    type Ux = u32;
485}
486#[doc = "`read()` method returns [`perip_clk_en0::R`](R) reader structure"]
487impl crate::Readable for PERIP_CLK_EN0_SPEC {}
488#[doc = "`write(|w| ..)` method takes [`perip_clk_en0::W`](W) writer structure"]
489impl crate::Writable for PERIP_CLK_EN0_SPEC {
490    type Safety = crate::Unsafe;
491}
492#[doc = "`reset()` method sets PERIP_CLK_EN0 to value 0xf9c1_e06f"]
493impl crate::Resettable for PERIP_CLK_EN0_SPEC {
494    const RESET_VALUE: u32 = 0xf9c1_e06f;
495}
esp32c3/system/perip_clk_en0.rs

esp32c3/system/
perip_clk_en0.rs
