esp32c3/system/
perip_clk_en0.rs

1#[doc = "Register `PERIP_CLK_EN0` reader"]
2pub type R = crate::R<PERIP_CLK_EN0_SPEC>;
3#[doc = "Register `PERIP_CLK_EN0` writer"]
4pub type W = crate::W<PERIP_CLK_EN0_SPEC>;
5#[doc = "Field `TIMERS_CLK_EN` reader - reg_timers_clk_en"]
6pub type TIMERS_CLK_EN_R = crate::BitReader;
7#[doc = "Field `TIMERS_CLK_EN` writer - reg_timers_clk_en"]
8pub type TIMERS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SPI01_CLK_EN` reader - reg_spi01_clk_en"]
10pub type SPI01_CLK_EN_R = crate::BitReader;
11#[doc = "Field `SPI01_CLK_EN` writer - reg_spi01_clk_en"]
12pub type SPI01_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `UART_CLK_EN` reader - reg_uart_clk_en"]
14pub type UART_CLK_EN_R = crate::BitReader;
15#[doc = "Field `UART_CLK_EN` writer - reg_uart_clk_en"]
16pub type UART_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `WDG_CLK_EN` reader - reg_wdg_clk_en"]
18pub type WDG_CLK_EN_R = crate::BitReader;
19#[doc = "Field `WDG_CLK_EN` writer - reg_wdg_clk_en"]
20pub type WDG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `I2S0_CLK_EN` reader - reg_i2s0_clk_en"]
22pub type I2S0_CLK_EN_R = crate::BitReader;
23#[doc = "Field `I2S0_CLK_EN` writer - reg_i2s0_clk_en"]
24pub type I2S0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `UART1_CLK_EN` reader - reg_uart1_clk_en"]
26pub type UART1_CLK_EN_R = crate::BitReader;
27#[doc = "Field `UART1_CLK_EN` writer - reg_uart1_clk_en"]
28pub type UART1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SPI2_CLK_EN` reader - reg_spi2_clk_en"]
30pub type SPI2_CLK_EN_R = crate::BitReader;
31#[doc = "Field `SPI2_CLK_EN` writer - reg_spi2_clk_en"]
32pub type SPI2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `I2C_EXT0_CLK_EN` reader - reg_ext0_clk_en"]
34pub type I2C_EXT0_CLK_EN_R = crate::BitReader;
35#[doc = "Field `I2C_EXT0_CLK_EN` writer - reg_ext0_clk_en"]
36pub type I2C_EXT0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `UHCI0_CLK_EN` reader - reg_uhci0_clk_en"]
38pub type UHCI0_CLK_EN_R = crate::BitReader;
39#[doc = "Field `UHCI0_CLK_EN` writer - reg_uhci0_clk_en"]
40pub type UHCI0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `RMT_CLK_EN` reader - reg_rmt_clk_en"]
42pub type RMT_CLK_EN_R = crate::BitReader;
43#[doc = "Field `RMT_CLK_EN` writer - reg_rmt_clk_en"]
44pub type RMT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `PCNT_CLK_EN` reader - reg_pcnt_clk_en"]
46pub type PCNT_CLK_EN_R = crate::BitReader;
47#[doc = "Field `PCNT_CLK_EN` writer - reg_pcnt_clk_en"]
48pub type PCNT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `LEDC_CLK_EN` reader - reg_ledc_clk_en"]
50pub type LEDC_CLK_EN_R = crate::BitReader;
51#[doc = "Field `LEDC_CLK_EN` writer - reg_ledc_clk_en"]
52pub type LEDC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `UHCI1_CLK_EN` reader - reg_uhci1_clk_en"]
54pub type UHCI1_CLK_EN_R = crate::BitReader;
55#[doc = "Field `UHCI1_CLK_EN` writer - reg_uhci1_clk_en"]
56pub type UHCI1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `TIMERGROUP_CLK_EN` reader - reg_timergroup_clk_en"]
58pub type TIMERGROUP_CLK_EN_R = crate::BitReader;
59#[doc = "Field `TIMERGROUP_CLK_EN` writer - reg_timergroup_clk_en"]
60pub type TIMERGROUP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `EFUSE_CLK_EN` reader - reg_efuse_clk_en"]
62pub type EFUSE_CLK_EN_R = crate::BitReader;
63#[doc = "Field `EFUSE_CLK_EN` writer - reg_efuse_clk_en"]
64pub type EFUSE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `TIMERGROUP1_CLK_EN` reader - reg_timergroup1_clk_en"]
66pub type TIMERGROUP1_CLK_EN_R = crate::BitReader;
67#[doc = "Field `TIMERGROUP1_CLK_EN` writer - reg_timergroup1_clk_en"]
68pub type TIMERGROUP1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `SPI3_CLK_EN` reader - reg_spi3_clk_en"]
70pub type SPI3_CLK_EN_R = crate::BitReader;
71#[doc = "Field `SPI3_CLK_EN` writer - reg_spi3_clk_en"]
72pub type SPI3_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `PWM0_CLK_EN` reader - reg_pwm0_clk_en"]
74pub type PWM0_CLK_EN_R = crate::BitReader;
75#[doc = "Field `PWM0_CLK_EN` writer - reg_pwm0_clk_en"]
76pub type PWM0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `EXT1_CLK_EN` reader - reg_ext1_clk_en"]
78pub type EXT1_CLK_EN_R = crate::BitReader;
79#[doc = "Field `EXT1_CLK_EN` writer - reg_ext1_clk_en"]
80pub type EXT1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `TWAI_CLK_EN` reader - reg_can_clk_en"]
82pub type TWAI_CLK_EN_R = crate::BitReader;
83#[doc = "Field `TWAI_CLK_EN` writer - reg_can_clk_en"]
84pub type TWAI_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `PWM1_CLK_EN` reader - reg_pwm1_clk_en"]
86pub type PWM1_CLK_EN_R = crate::BitReader;
87#[doc = "Field `PWM1_CLK_EN` writer - reg_pwm1_clk_en"]
88pub type PWM1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `I2S1_CLK_EN` reader - reg_i2s1_clk_en"]
90pub type I2S1_CLK_EN_R = crate::BitReader;
91#[doc = "Field `I2S1_CLK_EN` writer - reg_i2s1_clk_en"]
92pub type I2S1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `SPI2_DMA_CLK_EN` reader - reg_spi2_dma_clk_en"]
94pub type SPI2_DMA_CLK_EN_R = crate::BitReader;
95#[doc = "Field `SPI2_DMA_CLK_EN` writer - reg_spi2_dma_clk_en"]
96pub type SPI2_DMA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `USB_DEVICE_CLK_EN` reader - reg_usb_device_clk_en"]
98pub type USB_DEVICE_CLK_EN_R = crate::BitReader;
99#[doc = "Field `USB_DEVICE_CLK_EN` writer - reg_usb_device_clk_en"]
100pub type USB_DEVICE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `UART_MEM_CLK_EN` reader - reg_uart_mem_clk_en"]
102pub type UART_MEM_CLK_EN_R = crate::BitReader;
103#[doc = "Field `UART_MEM_CLK_EN` writer - reg_uart_mem_clk_en"]
104pub type UART_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `PWM2_CLK_EN` reader - reg_pwm2_clk_en"]
106pub type PWM2_CLK_EN_R = crate::BitReader;
107#[doc = "Field `PWM2_CLK_EN` writer - reg_pwm2_clk_en"]
108pub type PWM2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `PWM3_CLK_EN` reader - reg_pwm3_clk_en"]
110pub type PWM3_CLK_EN_R = crate::BitReader;
111#[doc = "Field `PWM3_CLK_EN` writer - reg_pwm3_clk_en"]
112pub type PWM3_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
113#[doc = "Field `SPI3_DMA_CLK_EN` reader - reg_spi3_dma_clk_en"]
114pub type SPI3_DMA_CLK_EN_R = crate::BitReader;
115#[doc = "Field `SPI3_DMA_CLK_EN` writer - reg_spi3_dma_clk_en"]
116pub type SPI3_DMA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
117#[doc = "Field `APB_SARADC_CLK_EN` reader - reg_apb_saradc_clk_en"]
118pub type APB_SARADC_CLK_EN_R = crate::BitReader;
119#[doc = "Field `APB_SARADC_CLK_EN` writer - reg_apb_saradc_clk_en"]
120pub type APB_SARADC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
121#[doc = "Field `SYSTIMER_CLK_EN` reader - reg_systimer_clk_en"]
122pub type SYSTIMER_CLK_EN_R = crate::BitReader;
123#[doc = "Field `SYSTIMER_CLK_EN` writer - reg_systimer_clk_en"]
124pub type SYSTIMER_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
125#[doc = "Field `ADC2_ARB_CLK_EN` reader - reg_adc2_arb_clk_en"]
126pub type ADC2_ARB_CLK_EN_R = crate::BitReader;
127#[doc = "Field `ADC2_ARB_CLK_EN` writer - reg_adc2_arb_clk_en"]
128pub type ADC2_ARB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
129#[doc = "Field `SPI4_CLK_EN` reader - reg_spi4_clk_en"]
130pub type SPI4_CLK_EN_R = crate::BitReader;
131#[doc = "Field `SPI4_CLK_EN` writer - reg_spi4_clk_en"]
132pub type SPI4_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
133impl R {
134    #[doc = "Bit 0 - reg_timers_clk_en"]
135    #[inline(always)]
136    pub fn timers_clk_en(&self) -> TIMERS_CLK_EN_R {
137        TIMERS_CLK_EN_R::new((self.bits & 1) != 0)
138    }
139    #[doc = "Bit 1 - reg_spi01_clk_en"]
140    #[inline(always)]
141    pub fn spi01_clk_en(&self) -> SPI01_CLK_EN_R {
142        SPI01_CLK_EN_R::new(((self.bits >> 1) & 1) != 0)
143    }
144    #[doc = "Bit 2 - reg_uart_clk_en"]
145    #[inline(always)]
146    pub fn uart_clk_en(&self) -> UART_CLK_EN_R {
147        UART_CLK_EN_R::new(((self.bits >> 2) & 1) != 0)
148    }
149    #[doc = "Bit 3 - reg_wdg_clk_en"]
150    #[inline(always)]
151    pub fn wdg_clk_en(&self) -> WDG_CLK_EN_R {
152        WDG_CLK_EN_R::new(((self.bits >> 3) & 1) != 0)
153    }
154    #[doc = "Bit 4 - reg_i2s0_clk_en"]
155    #[inline(always)]
156    pub fn i2s0_clk_en(&self) -> I2S0_CLK_EN_R {
157        I2S0_CLK_EN_R::new(((self.bits >> 4) & 1) != 0)
158    }
159    #[doc = "Bit 5 - reg_uart1_clk_en"]
160    #[inline(always)]
161    pub fn uart1_clk_en(&self) -> UART1_CLK_EN_R {
162        UART1_CLK_EN_R::new(((self.bits >> 5) & 1) != 0)
163    }
164    #[doc = "Bit 6 - reg_spi2_clk_en"]
165    #[inline(always)]
166    pub fn spi2_clk_en(&self) -> SPI2_CLK_EN_R {
167        SPI2_CLK_EN_R::new(((self.bits >> 6) & 1) != 0)
168    }
169    #[doc = "Bit 7 - reg_ext0_clk_en"]
170    #[inline(always)]
171    pub fn i2c_ext0_clk_en(&self) -> I2C_EXT0_CLK_EN_R {
172        I2C_EXT0_CLK_EN_R::new(((self.bits >> 7) & 1) != 0)
173    }
174    #[doc = "Bit 8 - reg_uhci0_clk_en"]
175    #[inline(always)]
176    pub fn uhci0_clk_en(&self) -> UHCI0_CLK_EN_R {
177        UHCI0_CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
178    }
179    #[doc = "Bit 9 - reg_rmt_clk_en"]
180    #[inline(always)]
181    pub fn rmt_clk_en(&self) -> RMT_CLK_EN_R {
182        RMT_CLK_EN_R::new(((self.bits >> 9) & 1) != 0)
183    }
184    #[doc = "Bit 10 - reg_pcnt_clk_en"]
185    #[inline(always)]
186    pub fn pcnt_clk_en(&self) -> PCNT_CLK_EN_R {
187        PCNT_CLK_EN_R::new(((self.bits >> 10) & 1) != 0)
188    }
189    #[doc = "Bit 11 - reg_ledc_clk_en"]
190    #[inline(always)]
191    pub fn ledc_clk_en(&self) -> LEDC_CLK_EN_R {
192        LEDC_CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
193    }
194    #[doc = "Bit 12 - reg_uhci1_clk_en"]
195    #[inline(always)]
196    pub fn uhci1_clk_en(&self) -> UHCI1_CLK_EN_R {
197        UHCI1_CLK_EN_R::new(((self.bits >> 12) & 1) != 0)
198    }
199    #[doc = "Bit 13 - reg_timergroup_clk_en"]
200    #[inline(always)]
201    pub fn timergroup_clk_en(&self) -> TIMERGROUP_CLK_EN_R {
202        TIMERGROUP_CLK_EN_R::new(((self.bits >> 13) & 1) != 0)
203    }
204    #[doc = "Bit 14 - reg_efuse_clk_en"]
205    #[inline(always)]
206    pub fn efuse_clk_en(&self) -> EFUSE_CLK_EN_R {
207        EFUSE_CLK_EN_R::new(((self.bits >> 14) & 1) != 0)
208    }
209    #[doc = "Bit 15 - reg_timergroup1_clk_en"]
210    #[inline(always)]
211    pub fn timergroup1_clk_en(&self) -> TIMERGROUP1_CLK_EN_R {
212        TIMERGROUP1_CLK_EN_R::new(((self.bits >> 15) & 1) != 0)
213    }
214    #[doc = "Bit 16 - reg_spi3_clk_en"]
215    #[inline(always)]
216    pub fn spi3_clk_en(&self) -> SPI3_CLK_EN_R {
217        SPI3_CLK_EN_R::new(((self.bits >> 16) & 1) != 0)
218    }
219    #[doc = "Bit 17 - reg_pwm0_clk_en"]
220    #[inline(always)]
221    pub fn pwm0_clk_en(&self) -> PWM0_CLK_EN_R {
222        PWM0_CLK_EN_R::new(((self.bits >> 17) & 1) != 0)
223    }
224    #[doc = "Bit 18 - reg_ext1_clk_en"]
225    #[inline(always)]
226    pub fn ext1_clk_en(&self) -> EXT1_CLK_EN_R {
227        EXT1_CLK_EN_R::new(((self.bits >> 18) & 1) != 0)
228    }
229    #[doc = "Bit 19 - reg_can_clk_en"]
230    #[inline(always)]
231    pub fn twai_clk_en(&self) -> TWAI_CLK_EN_R {
232        TWAI_CLK_EN_R::new(((self.bits >> 19) & 1) != 0)
233    }
234    #[doc = "Bit 20 - reg_pwm1_clk_en"]
235    #[inline(always)]
236    pub fn pwm1_clk_en(&self) -> PWM1_CLK_EN_R {
237        PWM1_CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
238    }
239    #[doc = "Bit 21 - reg_i2s1_clk_en"]
240    #[inline(always)]
241    pub fn i2s1_clk_en(&self) -> I2S1_CLK_EN_R {
242        I2S1_CLK_EN_R::new(((self.bits >> 21) & 1) != 0)
243    }
244    #[doc = "Bit 22 - reg_spi2_dma_clk_en"]
245    #[inline(always)]
246    pub fn spi2_dma_clk_en(&self) -> SPI2_DMA_CLK_EN_R {
247        SPI2_DMA_CLK_EN_R::new(((self.bits >> 22) & 1) != 0)
248    }
249    #[doc = "Bit 23 - reg_usb_device_clk_en"]
250    #[inline(always)]
251    pub fn usb_device_clk_en(&self) -> USB_DEVICE_CLK_EN_R {
252        USB_DEVICE_CLK_EN_R::new(((self.bits >> 23) & 1) != 0)
253    }
254    #[doc = "Bit 24 - reg_uart_mem_clk_en"]
255    #[inline(always)]
256    pub fn uart_mem_clk_en(&self) -> UART_MEM_CLK_EN_R {
257        UART_MEM_CLK_EN_R::new(((self.bits >> 24) & 1) != 0)
258    }
259    #[doc = "Bit 25 - reg_pwm2_clk_en"]
260    #[inline(always)]
261    pub fn pwm2_clk_en(&self) -> PWM2_CLK_EN_R {
262        PWM2_CLK_EN_R::new(((self.bits >> 25) & 1) != 0)
263    }
264    #[doc = "Bit 26 - reg_pwm3_clk_en"]
265    #[inline(always)]
266    pub fn pwm3_clk_en(&self) -> PWM3_CLK_EN_R {
267        PWM3_CLK_EN_R::new(((self.bits >> 26) & 1) != 0)
268    }
269    #[doc = "Bit 27 - reg_spi3_dma_clk_en"]
270    #[inline(always)]
271    pub fn spi3_dma_clk_en(&self) -> SPI3_DMA_CLK_EN_R {
272        SPI3_DMA_CLK_EN_R::new(((self.bits >> 27) & 1) != 0)
273    }
274    #[doc = "Bit 28 - reg_apb_saradc_clk_en"]
275    #[inline(always)]
276    pub fn apb_saradc_clk_en(&self) -> APB_SARADC_CLK_EN_R {
277        APB_SARADC_CLK_EN_R::new(((self.bits >> 28) & 1) != 0)
278    }
279    #[doc = "Bit 29 - reg_systimer_clk_en"]
280    #[inline(always)]
281    pub fn systimer_clk_en(&self) -> SYSTIMER_CLK_EN_R {
282        SYSTIMER_CLK_EN_R::new(((self.bits >> 29) & 1) != 0)
283    }
284    #[doc = "Bit 30 - reg_adc2_arb_clk_en"]
285    #[inline(always)]
286    pub fn adc2_arb_clk_en(&self) -> ADC2_ARB_CLK_EN_R {
287        ADC2_ARB_CLK_EN_R::new(((self.bits >> 30) & 1) != 0)
288    }
289    #[doc = "Bit 31 - reg_spi4_clk_en"]
290    #[inline(always)]
291    pub fn spi4_clk_en(&self) -> SPI4_CLK_EN_R {
292        SPI4_CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
293    }
294}
295#[cfg(feature = "impl-register-debug")]
296impl core::fmt::Debug for R {
297    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
298        f.debug_struct("PERIP_CLK_EN0")
299            .field("timers_clk_en", &self.timers_clk_en())
300            .field("spi01_clk_en", &self.spi01_clk_en())
301            .field("uart_clk_en", &self.uart_clk_en())
302            .field("wdg_clk_en", &self.wdg_clk_en())
303            .field("i2s0_clk_en", &self.i2s0_clk_en())
304            .field("uart1_clk_en", &self.uart1_clk_en())
305            .field("spi2_clk_en", &self.spi2_clk_en())
306            .field("i2c_ext0_clk_en", &self.i2c_ext0_clk_en())
307            .field("uhci0_clk_en", &self.uhci0_clk_en())
308            .field("rmt_clk_en", &self.rmt_clk_en())
309            .field("pcnt_clk_en", &self.pcnt_clk_en())
310            .field("ledc_clk_en", &self.ledc_clk_en())
311            .field("uhci1_clk_en", &self.uhci1_clk_en())
312            .field("timergroup_clk_en", &self.timergroup_clk_en())
313            .field("efuse_clk_en", &self.efuse_clk_en())
314            .field("timergroup1_clk_en", &self.timergroup1_clk_en())
315            .field("spi3_clk_en", &self.spi3_clk_en())
316            .field("pwm0_clk_en", &self.pwm0_clk_en())
317            .field("ext1_clk_en", &self.ext1_clk_en())
318            .field("twai_clk_en", &self.twai_clk_en())
319            .field("pwm1_clk_en", &self.pwm1_clk_en())
320            .field("i2s1_clk_en", &self.i2s1_clk_en())
321            .field("spi2_dma_clk_en", &self.spi2_dma_clk_en())
322            .field("usb_device_clk_en", &self.usb_device_clk_en())
323            .field("uart_mem_clk_en", &self.uart_mem_clk_en())
324            .field("pwm2_clk_en", &self.pwm2_clk_en())
325            .field("pwm3_clk_en", &self.pwm3_clk_en())
326            .field("spi3_dma_clk_en", &self.spi3_dma_clk_en())
327            .field("apb_saradc_clk_en", &self.apb_saradc_clk_en())
328            .field("systimer_clk_en", &self.systimer_clk_en())
329            .field("adc2_arb_clk_en", &self.adc2_arb_clk_en())
330            .field("spi4_clk_en", &self.spi4_clk_en())
331            .finish()
332    }
333}
334impl W {
335    #[doc = "Bit 0 - reg_timers_clk_en"]
336    #[inline(always)]
337    pub fn timers_clk_en(&mut self) -> TIMERS_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
338        TIMERS_CLK_EN_W::new(self, 0)
339    }
340    #[doc = "Bit 1 - reg_spi01_clk_en"]
341    #[inline(always)]
342    pub fn spi01_clk_en(&mut self) -> SPI01_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
343        SPI01_CLK_EN_W::new(self, 1)
344    }
345    #[doc = "Bit 2 - reg_uart_clk_en"]
346    #[inline(always)]
347    pub fn uart_clk_en(&mut self) -> UART_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
348        UART_CLK_EN_W::new(self, 2)
349    }
350    #[doc = "Bit 3 - reg_wdg_clk_en"]
351    #[inline(always)]
352    pub fn wdg_clk_en(&mut self) -> WDG_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
353        WDG_CLK_EN_W::new(self, 3)
354    }
355    #[doc = "Bit 4 - reg_i2s0_clk_en"]
356    #[inline(always)]
357    pub fn i2s0_clk_en(&mut self) -> I2S0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
358        I2S0_CLK_EN_W::new(self, 4)
359    }
360    #[doc = "Bit 5 - reg_uart1_clk_en"]
361    #[inline(always)]
362    pub fn uart1_clk_en(&mut self) -> UART1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
363        UART1_CLK_EN_W::new(self, 5)
364    }
365    #[doc = "Bit 6 - reg_spi2_clk_en"]
366    #[inline(always)]
367    pub fn spi2_clk_en(&mut self) -> SPI2_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
368        SPI2_CLK_EN_W::new(self, 6)
369    }
370    #[doc = "Bit 7 - reg_ext0_clk_en"]
371    #[inline(always)]
372    pub fn i2c_ext0_clk_en(&mut self) -> I2C_EXT0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
373        I2C_EXT0_CLK_EN_W::new(self, 7)
374    }
375    #[doc = "Bit 8 - reg_uhci0_clk_en"]
376    #[inline(always)]
377    pub fn uhci0_clk_en(&mut self) -> UHCI0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
378        UHCI0_CLK_EN_W::new(self, 8)
379    }
380    #[doc = "Bit 9 - reg_rmt_clk_en"]
381    #[inline(always)]
382    pub fn rmt_clk_en(&mut self) -> RMT_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
383        RMT_CLK_EN_W::new(self, 9)
384    }
385    #[doc = "Bit 10 - reg_pcnt_clk_en"]
386    #[inline(always)]
387    pub fn pcnt_clk_en(&mut self) -> PCNT_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
388        PCNT_CLK_EN_W::new(self, 10)
389    }
390    #[doc = "Bit 11 - reg_ledc_clk_en"]
391    #[inline(always)]
392    pub fn ledc_clk_en(&mut self) -> LEDC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
393        LEDC_CLK_EN_W::new(self, 11)
394    }
395    #[doc = "Bit 12 - reg_uhci1_clk_en"]
396    #[inline(always)]
397    pub fn uhci1_clk_en(&mut self) -> UHCI1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
398        UHCI1_CLK_EN_W::new(self, 12)
399    }
400    #[doc = "Bit 13 - reg_timergroup_clk_en"]
401    #[inline(always)]
402    pub fn timergroup_clk_en(&mut self) -> TIMERGROUP_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
403        TIMERGROUP_CLK_EN_W::new(self, 13)
404    }
405    #[doc = "Bit 14 - reg_efuse_clk_en"]
406    #[inline(always)]
407    pub fn efuse_clk_en(&mut self) -> EFUSE_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
408        EFUSE_CLK_EN_W::new(self, 14)
409    }
410    #[doc = "Bit 15 - reg_timergroup1_clk_en"]
411    #[inline(always)]
412    pub fn timergroup1_clk_en(&mut self) -> TIMERGROUP1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
413        TIMERGROUP1_CLK_EN_W::new(self, 15)
414    }
415    #[doc = "Bit 16 - reg_spi3_clk_en"]
416    #[inline(always)]
417    pub fn spi3_clk_en(&mut self) -> SPI3_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
418        SPI3_CLK_EN_W::new(self, 16)
419    }
420    #[doc = "Bit 17 - reg_pwm0_clk_en"]
421    #[inline(always)]
422    pub fn pwm0_clk_en(&mut self) -> PWM0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
423        PWM0_CLK_EN_W::new(self, 17)
424    }
425    #[doc = "Bit 18 - reg_ext1_clk_en"]
426    #[inline(always)]
427    pub fn ext1_clk_en(&mut self) -> EXT1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
428        EXT1_CLK_EN_W::new(self, 18)
429    }
430    #[doc = "Bit 19 - reg_can_clk_en"]
431    #[inline(always)]
432    pub fn twai_clk_en(&mut self) -> TWAI_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
433        TWAI_CLK_EN_W::new(self, 19)
434    }
435    #[doc = "Bit 20 - reg_pwm1_clk_en"]
436    #[inline(always)]
437    pub fn pwm1_clk_en(&mut self) -> PWM1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
438        PWM1_CLK_EN_W::new(self, 20)
439    }
440    #[doc = "Bit 21 - reg_i2s1_clk_en"]
441    #[inline(always)]
442    pub fn i2s1_clk_en(&mut self) -> I2S1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
443        I2S1_CLK_EN_W::new(self, 21)
444    }
445    #[doc = "Bit 22 - reg_spi2_dma_clk_en"]
446    #[inline(always)]
447    pub fn spi2_dma_clk_en(&mut self) -> SPI2_DMA_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
448        SPI2_DMA_CLK_EN_W::new(self, 22)
449    }
450    #[doc = "Bit 23 - reg_usb_device_clk_en"]
451    #[inline(always)]
452    pub fn usb_device_clk_en(&mut self) -> USB_DEVICE_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
453        USB_DEVICE_CLK_EN_W::new(self, 23)
454    }
455    #[doc = "Bit 24 - reg_uart_mem_clk_en"]
456    #[inline(always)]
457    pub fn uart_mem_clk_en(&mut self) -> UART_MEM_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
458        UART_MEM_CLK_EN_W::new(self, 24)
459    }
460    #[doc = "Bit 25 - reg_pwm2_clk_en"]
461    #[inline(always)]
462    pub fn pwm2_clk_en(&mut self) -> PWM2_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
463        PWM2_CLK_EN_W::new(self, 25)
464    }
465    #[doc = "Bit 26 - reg_pwm3_clk_en"]
466    #[inline(always)]
467    pub fn pwm3_clk_en(&mut self) -> PWM3_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
468        PWM3_CLK_EN_W::new(self, 26)
469    }
470    #[doc = "Bit 27 - reg_spi3_dma_clk_en"]
471    #[inline(always)]
472    pub fn spi3_dma_clk_en(&mut self) -> SPI3_DMA_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
473        SPI3_DMA_CLK_EN_W::new(self, 27)
474    }
475    #[doc = "Bit 28 - reg_apb_saradc_clk_en"]
476    #[inline(always)]
477    pub fn apb_saradc_clk_en(&mut self) -> APB_SARADC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
478        APB_SARADC_CLK_EN_W::new(self, 28)
479    }
480    #[doc = "Bit 29 - reg_systimer_clk_en"]
481    #[inline(always)]
482    pub fn systimer_clk_en(&mut self) -> SYSTIMER_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
483        SYSTIMER_CLK_EN_W::new(self, 29)
484    }
485    #[doc = "Bit 30 - reg_adc2_arb_clk_en"]
486    #[inline(always)]
487    pub fn adc2_arb_clk_en(&mut self) -> ADC2_ARB_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
488        ADC2_ARB_CLK_EN_W::new(self, 30)
489    }
490    #[doc = "Bit 31 - reg_spi4_clk_en"]
491    #[inline(always)]
492    pub fn spi4_clk_en(&mut self) -> SPI4_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
493        SPI4_CLK_EN_W::new(self, 31)
494    }
495}
496#[doc = "peripheral clock gating register\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_clk_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_clk_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
497pub struct PERIP_CLK_EN0_SPEC;
498impl crate::RegisterSpec for PERIP_CLK_EN0_SPEC {
499    type Ux = u32;
500}
501#[doc = "`read()` method returns [`perip_clk_en0::R`](R) reader structure"]
502impl crate::Readable for PERIP_CLK_EN0_SPEC {}
503#[doc = "`write(|w| ..)` method takes [`perip_clk_en0::W`](W) writer structure"]
504impl crate::Writable for PERIP_CLK_EN0_SPEC {
505    type Safety = crate::Unsafe;
506    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
507    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
508}
509#[doc = "`reset()` method sets PERIP_CLK_EN0 to value 0xf9c1_e06f"]
510impl crate::Resettable for PERIP_CLK_EN0_SPEC {
511    const RESET_VALUE: u32 = 0xf9c1_e06f;
512}
esp32c3/system/perip_clk_en0.rs

esp32c3/system/
perip_clk_en0.rs
