esp32s3/sens/
sar_reader2_ctrl.rs
1#[doc = "Register `SAR_READER2_CTRL` reader"]
2pub type R = crate::R<SAR_READER2_CTRL_SPEC>;
3#[doc = "Register `SAR_READER2_CTRL` writer"]
4pub type W = crate::W<SAR_READER2_CTRL_SPEC>;
5#[doc = "Field `SAR_SAR2_CLK_DIV` reader - clock divider"]
6pub type SAR_SAR2_CLK_DIV_R = crate::FieldReader;
7#[doc = "Field `SAR_SAR2_CLK_DIV` writer - clock divider"]
8pub type SAR_SAR2_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `SAR_SAR2_WAIT_ARB_CYCLE` reader - wait arbit stable after sar_done"]
10pub type SAR_SAR2_WAIT_ARB_CYCLE_R = crate::FieldReader;
11#[doc = "Field `SAR_SAR2_WAIT_ARB_CYCLE` writer - wait arbit stable after sar_done"]
12pub type SAR_SAR2_WAIT_ARB_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `SAR_SAR2_CLK_GATED` reader - ******* Description ***********"]
14pub type SAR_SAR2_CLK_GATED_R = crate::BitReader;
15#[doc = "Field `SAR_SAR2_CLK_GATED` writer - ******* Description ***********"]
16pub type SAR_SAR2_CLK_GATED_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SAR_SAR2_SAMPLE_NUM` reader - ******* Description ***********"]
18pub type SAR_SAR2_SAMPLE_NUM_R = crate::FieldReader;
19#[doc = "Field `SAR_SAR2_SAMPLE_NUM` writer - ******* Description ***********"]
20pub type SAR_SAR2_SAMPLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
21#[doc = "Field `SAR_SAR2_DATA_INV` reader - Invert SAR ADC2 data"]
22pub type SAR_SAR2_DATA_INV_R = crate::BitReader;
23#[doc = "Field `SAR_SAR2_DATA_INV` writer - Invert SAR ADC2 data"]
24pub type SAR_SAR2_DATA_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SAR_SAR2_INT_EN` reader - enable saradc2 to send out interrupt"]
26pub type SAR_SAR2_INT_EN_R = crate::BitReader;
27#[doc = "Field `SAR_SAR2_INT_EN` writer - enable saradc2 to send out interrupt"]
28pub type SAR_SAR2_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30 #[doc = "Bits 0:7 - clock divider"]
31 #[inline(always)]
32 pub fn sar_sar2_clk_div(&self) -> SAR_SAR2_CLK_DIV_R {
33 SAR_SAR2_CLK_DIV_R::new((self.bits & 0xff) as u8)
34 }
35 #[doc = "Bits 16:17 - wait arbit stable after sar_done"]
36 #[inline(always)]
37 pub fn sar_sar2_wait_arb_cycle(&self) -> SAR_SAR2_WAIT_ARB_CYCLE_R {
38 SAR_SAR2_WAIT_ARB_CYCLE_R::new(((self.bits >> 16) & 3) as u8)
39 }
40 #[doc = "Bit 18 - ******* Description ***********"]
41 #[inline(always)]
42 pub fn sar_sar2_clk_gated(&self) -> SAR_SAR2_CLK_GATED_R {
43 SAR_SAR2_CLK_GATED_R::new(((self.bits >> 18) & 1) != 0)
44 }
45 #[doc = "Bits 19:26 - ******* Description ***********"]
46 #[inline(always)]
47 pub fn sar_sar2_sample_num(&self) -> SAR_SAR2_SAMPLE_NUM_R {
48 SAR_SAR2_SAMPLE_NUM_R::new(((self.bits >> 19) & 0xff) as u8)
49 }
50 #[doc = "Bit 29 - Invert SAR ADC2 data"]
51 #[inline(always)]
52 pub fn sar_sar2_data_inv(&self) -> SAR_SAR2_DATA_INV_R {
53 SAR_SAR2_DATA_INV_R::new(((self.bits >> 29) & 1) != 0)
54 }
55 #[doc = "Bit 30 - enable saradc2 to send out interrupt"]
56 #[inline(always)]
57 pub fn sar_sar2_int_en(&self) -> SAR_SAR2_INT_EN_R {
58 SAR_SAR2_INT_EN_R::new(((self.bits >> 30) & 1) != 0)
59 }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64 f.debug_struct("SAR_READER2_CTRL")
65 .field("sar_sar2_clk_div", &self.sar_sar2_clk_div())
66 .field("sar_sar2_wait_arb_cycle", &self.sar_sar2_wait_arb_cycle())
67 .field("sar_sar2_clk_gated", &self.sar_sar2_clk_gated())
68 .field("sar_sar2_sample_num", &self.sar_sar2_sample_num())
69 .field("sar_sar2_data_inv", &self.sar_sar2_data_inv())
70 .field("sar_sar2_int_en", &self.sar_sar2_int_en())
71 .finish()
72 }
73}
74impl W {
75 #[doc = "Bits 0:7 - clock divider"]
76 #[inline(always)]
77 pub fn sar_sar2_clk_div(&mut self) -> SAR_SAR2_CLK_DIV_W<SAR_READER2_CTRL_SPEC> {
78 SAR_SAR2_CLK_DIV_W::new(self, 0)
79 }
80 #[doc = "Bits 16:17 - wait arbit stable after sar_done"]
81 #[inline(always)]
82 pub fn sar_sar2_wait_arb_cycle(&mut self) -> SAR_SAR2_WAIT_ARB_CYCLE_W<SAR_READER2_CTRL_SPEC> {
83 SAR_SAR2_WAIT_ARB_CYCLE_W::new(self, 16)
84 }
85 #[doc = "Bit 18 - ******* Description ***********"]
86 #[inline(always)]
87 pub fn sar_sar2_clk_gated(&mut self) -> SAR_SAR2_CLK_GATED_W<SAR_READER2_CTRL_SPEC> {
88 SAR_SAR2_CLK_GATED_W::new(self, 18)
89 }
90 #[doc = "Bits 19:26 - ******* Description ***********"]
91 #[inline(always)]
92 pub fn sar_sar2_sample_num(&mut self) -> SAR_SAR2_SAMPLE_NUM_W<SAR_READER2_CTRL_SPEC> {
93 SAR_SAR2_SAMPLE_NUM_W::new(self, 19)
94 }
95 #[doc = "Bit 29 - Invert SAR ADC2 data"]
96 #[inline(always)]
97 pub fn sar_sar2_data_inv(&mut self) -> SAR_SAR2_DATA_INV_W<SAR_READER2_CTRL_SPEC> {
98 SAR_SAR2_DATA_INV_W::new(self, 29)
99 }
100 #[doc = "Bit 30 - enable saradc2 to send out interrupt"]
101 #[inline(always)]
102 pub fn sar_sar2_int_en(&mut self) -> SAR_SAR2_INT_EN_W<SAR_READER2_CTRL_SPEC> {
103 SAR_SAR2_INT_EN_W::new(self, 30)
104 }
105}
106#[doc = "configure saradc2 reader\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_reader2_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_reader2_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct SAR_READER2_CTRL_SPEC;
108impl crate::RegisterSpec for SAR_READER2_CTRL_SPEC {
109 type Ux = u32;
110}
111#[doc = "`read()` method returns [`sar_reader2_ctrl::R`](R) reader structure"]
112impl crate::Readable for SAR_READER2_CTRL_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`sar_reader2_ctrl::W`](W) writer structure"]
114impl crate::Writable for SAR_READER2_CTRL_SPEC {
115 type Safety = crate::Unsafe;
116 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets SAR_READER2_CTRL to value 0x4005_0002"]
120impl crate::Resettable for SAR_READER2_CTRL_SPEC {
121 const RESET_VALUE: u32 = 0x4005_0002;
122}