1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `FDUMMY_OUT` reader - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller."]
6pub type FDUMMY_OUT_R = crate::BitReader;
7#[doc = "Field `FDUMMY_OUT` writer - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller."]
8pub type FDUMMY_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FDOUT_OCT` reader - Set this bit to enable 8-bit-mode(8-bm) in DOUT phase."]
10pub type FDOUT_OCT_R = crate::BitReader;
11#[doc = "Field `FDOUT_OCT` writer - Set this bit to enable 8-bit-mode(8-bm) in DOUT phase."]
12pub type FDOUT_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FDIN_OCT` reader - Set this bit to enable 8-bit-mode(8-bm) in DIN phase."]
14pub type FDIN_OCT_R = crate::BitReader;
15#[doc = "Field `FDIN_OCT` writer - Set this bit to enable 8-bit-mode(8-bm) in DIN phase."]
16pub type FDIN_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FADDR_OCT` reader - Set this bit to enable 8-bit-mode(8-bm) in ADDR phase."]
18pub type FADDR_OCT_R = crate::BitReader;
19#[doc = "Field `FADDR_OCT` writer - Set this bit to enable 8-bit-mode(8-bm) in ADDR phase."]
20pub type FADDR_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FCMD_DUAL` reader - Set this bit to enable 2-bit-mode(2-bm) in CMD phase."]
22pub type FCMD_DUAL_R = crate::BitReader;
23#[doc = "Field `FCMD_DUAL` writer - Set this bit to enable 2-bit-mode(2-bm) in CMD phase."]
24pub type FCMD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FCMD_QUAD` reader - Set this bit to enable 4-bit-mode(4-bm) in CMD phase."]
26pub type FCMD_QUAD_R = crate::BitReader;
27#[doc = "Field `FCMD_QUAD` writer - Set this bit to enable 4-bit-mode(4-bm) in CMD phase."]
28pub type FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FCMD_OCT` reader - Set this bit to enable 8-bit-mode(8-bm) in CMD phase."]
30pub type FCMD_OCT_R = crate::BitReader;
31#[doc = "Field `FCMD_OCT` writer - Set this bit to enable 8-bit-mode(8-bm) in CMD phase."]
32pub type FCMD_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FCS_CRC_EN` reader - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
34pub type FCS_CRC_EN_R = crate::BitReader;
35#[doc = "Field `FCS_CRC_EN` writer - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
36pub type FCS_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TX_CRC_EN` reader - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
38pub type TX_CRC_EN_R = crate::BitReader;
39#[doc = "Field `TX_CRC_EN` writer - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
40pub type TX_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FASTRD_MODE` reader - This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set."]
42pub type FASTRD_MODE_R = crate::BitReader;
43#[doc = "Field `FASTRD_MODE` writer - This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set."]
44pub type FASTRD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FREAD_DUAL` reader - In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable."]
46pub type FREAD_DUAL_R = crate::BitReader;
47#[doc = "Field `FREAD_DUAL` writer - In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable."]
48pub type FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RESANDRES` reader - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
50pub type RESANDRES_R = crate::BitReader;
51#[doc = "Field `RESANDRES` writer - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
52pub type RESANDRES_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low"]
54pub type Q_POL_R = crate::BitReader;
55#[doc = "Field `Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low"]
56pub type Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low"]
58pub type D_POL_R = crate::BitReader;
59#[doc = "Field `D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low"]
60pub type D_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `FREAD_QUAD` reader - In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
62pub type FREAD_QUAD_R = crate::BitReader;
63#[doc = "Field `FREAD_QUAD` writer - In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
64pub type FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `WP` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
66pub type WP_R = crate::BitReader;
67#[doc = "Field `WP` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
68pub type WP_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `WRSR_2B` reader - Two bytes data will be written to status register when it is set. 1: enable 0: disable."]
70pub type WRSR_2B_R = crate::BitReader;
71#[doc = "Field `WRSR_2B` writer - Two bytes data will be written to status register when it is set. 1: enable 0: disable."]
72pub type WRSR_2B_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `FREAD_DIO` reader - In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable."]
74pub type FREAD_DIO_R = crate::BitReader;
75#[doc = "Field `FREAD_DIO` writer - In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable."]
76pub type FREAD_DIO_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `FREAD_QIO` reader - In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
78pub type FREAD_QIO_R = crate::BitReader;
79#[doc = "Field `FREAD_QIO` writer - In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
80pub type FREAD_QIO_W<'a, REG> = crate::BitWriter<'a, REG>;
81impl R {
82 #[doc = "Bit 3 - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller."]
83 #[inline(always)]
84 pub fn fdummy_out(&self) -> FDUMMY_OUT_R {
85 FDUMMY_OUT_R::new(((self.bits >> 3) & 1) != 0)
86 }
87 #[doc = "Bit 4 - Set this bit to enable 8-bit-mode(8-bm) in DOUT phase."]
88 #[inline(always)]
89 pub fn fdout_oct(&self) -> FDOUT_OCT_R {
90 FDOUT_OCT_R::new(((self.bits >> 4) & 1) != 0)
91 }
92 #[doc = "Bit 5 - Set this bit to enable 8-bit-mode(8-bm) in DIN phase."]
93 #[inline(always)]
94 pub fn fdin_oct(&self) -> FDIN_OCT_R {
95 FDIN_OCT_R::new(((self.bits >> 5) & 1) != 0)
96 }
97 #[doc = "Bit 6 - Set this bit to enable 8-bit-mode(8-bm) in ADDR phase."]
98 #[inline(always)]
99 pub fn faddr_oct(&self) -> FADDR_OCT_R {
100 FADDR_OCT_R::new(((self.bits >> 6) & 1) != 0)
101 }
102 #[doc = "Bit 7 - Set this bit to enable 2-bit-mode(2-bm) in CMD phase."]
103 #[inline(always)]
104 pub fn fcmd_dual(&self) -> FCMD_DUAL_R {
105 FCMD_DUAL_R::new(((self.bits >> 7) & 1) != 0)
106 }
107 #[doc = "Bit 8 - Set this bit to enable 4-bit-mode(4-bm) in CMD phase."]
108 #[inline(always)]
109 pub fn fcmd_quad(&self) -> FCMD_QUAD_R {
110 FCMD_QUAD_R::new(((self.bits >> 8) & 1) != 0)
111 }
112 #[doc = "Bit 9 - Set this bit to enable 8-bit-mode(8-bm) in CMD phase."]
113 #[inline(always)]
114 pub fn fcmd_oct(&self) -> FCMD_OCT_R {
115 FCMD_OCT_R::new(((self.bits >> 9) & 1) != 0)
116 }
117 #[doc = "Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
118 #[inline(always)]
119 pub fn fcs_crc_en(&self) -> FCS_CRC_EN_R {
120 FCS_CRC_EN_R::new(((self.bits >> 10) & 1) != 0)
121 }
122 #[doc = "Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
123 #[inline(always)]
124 pub fn tx_crc_en(&self) -> TX_CRC_EN_R {
125 TX_CRC_EN_R::new(((self.bits >> 11) & 1) != 0)
126 }
127 #[doc = "Bit 13 - This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set."]
128 #[inline(always)]
129 pub fn fastrd_mode(&self) -> FASTRD_MODE_R {
130 FASTRD_MODE_R::new(((self.bits >> 13) & 1) != 0)
131 }
132 #[doc = "Bit 14 - In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable."]
133 #[inline(always)]
134 pub fn fread_dual(&self) -> FREAD_DUAL_R {
135 FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0)
136 }
137 #[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
138 #[inline(always)]
139 pub fn resandres(&self) -> RESANDRES_R {
140 RESANDRES_R::new(((self.bits >> 15) & 1) != 0)
141 }
142 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
143 #[inline(always)]
144 pub fn q_pol(&self) -> Q_POL_R {
145 Q_POL_R::new(((self.bits >> 18) & 1) != 0)
146 }
147 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
148 #[inline(always)]
149 pub fn d_pol(&self) -> D_POL_R {
150 D_POL_R::new(((self.bits >> 19) & 1) != 0)
151 }
152 #[doc = "Bit 20 - In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
153 #[inline(always)]
154 pub fn fread_quad(&self) -> FREAD_QUAD_R {
155 FREAD_QUAD_R::new(((self.bits >> 20) & 1) != 0)
156 }
157 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
158 #[inline(always)]
159 pub fn wp(&self) -> WP_R {
160 WP_R::new(((self.bits >> 21) & 1) != 0)
161 }
162 #[doc = "Bit 22 - Two bytes data will be written to status register when it is set. 1: enable 0: disable."]
163 #[inline(always)]
164 pub fn wrsr_2b(&self) -> WRSR_2B_R {
165 WRSR_2B_R::new(((self.bits >> 22) & 1) != 0)
166 }
167 #[doc = "Bit 23 - In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable."]
168 #[inline(always)]
169 pub fn fread_dio(&self) -> FREAD_DIO_R {
170 FREAD_DIO_R::new(((self.bits >> 23) & 1) != 0)
171 }
172 #[doc = "Bit 24 - In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
173 #[inline(always)]
174 pub fn fread_qio(&self) -> FREAD_QIO_R {
175 FREAD_QIO_R::new(((self.bits >> 24) & 1) != 0)
176 }
177}
178#[cfg(feature = "impl-register-debug")]
179impl core::fmt::Debug for R {
180 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
181 f.debug_struct("CTRL")
182 .field("fdummy_out", &self.fdummy_out())
183 .field("fdout_oct", &self.fdout_oct())
184 .field("fdin_oct", &self.fdin_oct())
185 .field("faddr_oct", &self.faddr_oct())
186 .field("fcmd_dual", &self.fcmd_dual())
187 .field("fcmd_quad", &self.fcmd_quad())
188 .field("fcmd_oct", &self.fcmd_oct())
189 .field("fcs_crc_en", &self.fcs_crc_en())
190 .field("tx_crc_en", &self.tx_crc_en())
191 .field("fastrd_mode", &self.fastrd_mode())
192 .field("fread_dual", &self.fread_dual())
193 .field("resandres", &self.resandres())
194 .field("q_pol", &self.q_pol())
195 .field("d_pol", &self.d_pol())
196 .field("fread_quad", &self.fread_quad())
197 .field("wp", &self.wp())
198 .field("wrsr_2b", &self.wrsr_2b())
199 .field("fread_dio", &self.fread_dio())
200 .field("fread_qio", &self.fread_qio())
201 .finish()
202 }
203}
204impl W {
205 #[doc = "Bit 3 - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller."]
206 #[inline(always)]
207 pub fn fdummy_out(&mut self) -> FDUMMY_OUT_W<CTRL_SPEC> {
208 FDUMMY_OUT_W::new(self, 3)
209 }
210 #[doc = "Bit 4 - Set this bit to enable 8-bit-mode(8-bm) in DOUT phase."]
211 #[inline(always)]
212 pub fn fdout_oct(&mut self) -> FDOUT_OCT_W<CTRL_SPEC> {
213 FDOUT_OCT_W::new(self, 4)
214 }
215 #[doc = "Bit 5 - Set this bit to enable 8-bit-mode(8-bm) in DIN phase."]
216 #[inline(always)]
217 pub fn fdin_oct(&mut self) -> FDIN_OCT_W<CTRL_SPEC> {
218 FDIN_OCT_W::new(self, 5)
219 }
220 #[doc = "Bit 6 - Set this bit to enable 8-bit-mode(8-bm) in ADDR phase."]
221 #[inline(always)]
222 pub fn faddr_oct(&mut self) -> FADDR_OCT_W<CTRL_SPEC> {
223 FADDR_OCT_W::new(self, 6)
224 }
225 #[doc = "Bit 7 - Set this bit to enable 2-bit-mode(2-bm) in CMD phase."]
226 #[inline(always)]
227 pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<CTRL_SPEC> {
228 FCMD_DUAL_W::new(self, 7)
229 }
230 #[doc = "Bit 8 - Set this bit to enable 4-bit-mode(4-bm) in CMD phase."]
231 #[inline(always)]
232 pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
233 FCMD_QUAD_W::new(self, 8)
234 }
235 #[doc = "Bit 9 - Set this bit to enable 8-bit-mode(8-bm) in CMD phase."]
236 #[inline(always)]
237 pub fn fcmd_oct(&mut self) -> FCMD_OCT_W<CTRL_SPEC> {
238 FCMD_OCT_W::new(self, 9)
239 }
240 #[doc = "Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
241 #[inline(always)]
242 pub fn fcs_crc_en(&mut self) -> FCS_CRC_EN_W<CTRL_SPEC> {
243 FCS_CRC_EN_W::new(self, 10)
244 }
245 #[doc = "Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
246 #[inline(always)]
247 pub fn tx_crc_en(&mut self) -> TX_CRC_EN_W<CTRL_SPEC> {
248 TX_CRC_EN_W::new(self, 11)
249 }
250 #[doc = "Bit 13 - This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set."]
251 #[inline(always)]
252 pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<CTRL_SPEC> {
253 FASTRD_MODE_W::new(self, 13)
254 }
255 #[doc = "Bit 14 - In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable."]
256 #[inline(always)]
257 pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
258 FREAD_DUAL_W::new(self, 14)
259 }
260 #[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
261 #[inline(always)]
262 pub fn resandres(&mut self) -> RESANDRES_W<CTRL_SPEC> {
263 RESANDRES_W::new(self, 15)
264 }
265 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
266 #[inline(always)]
267 pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
268 Q_POL_W::new(self, 18)
269 }
270 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
271 #[inline(always)]
272 pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
273 D_POL_W::new(self, 19)
274 }
275 #[doc = "Bit 20 - In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
276 #[inline(always)]
277 pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
278 FREAD_QUAD_W::new(self, 20)
279 }
280 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
281 #[inline(always)]
282 pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
283 WP_W::new(self, 21)
284 }
285 #[doc = "Bit 22 - Two bytes data will be written to status register when it is set. 1: enable 0: disable."]
286 #[inline(always)]
287 pub fn wrsr_2b(&mut self) -> WRSR_2B_W<CTRL_SPEC> {
288 WRSR_2B_W::new(self, 22)
289 }
290 #[doc = "Bit 23 - In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable."]
291 #[inline(always)]
292 pub fn fread_dio(&mut self) -> FREAD_DIO_W<CTRL_SPEC> {
293 FREAD_DIO_W::new(self, 23)
294 }
295 #[doc = "Bit 24 - In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
296 #[inline(always)]
297 pub fn fread_qio(&mut self) -> FREAD_QIO_W<CTRL_SPEC> {
298 FREAD_QIO_W::new(self, 24)
299 }
300}
301#[doc = "SPI1 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
302pub struct CTRL_SPEC;
303impl crate::RegisterSpec for CTRL_SPEC {
304 type Ux = u32;
305}
306#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
307impl crate::Readable for CTRL_SPEC {}
308#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
309impl crate::Writable for CTRL_SPEC {
310 type Safety = crate::Unsafe;
311 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
312 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
313}
314#[doc = "`reset()` method sets CTRL to value 0x002c_a000"]
315impl crate::Resettable for CTRL_SPEC {
316 const RESET_VALUE: u32 = 0x002c_a000;
317}