esp32s3/apb_saradc/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `THRES1_LOW` writer - interrupt of thres1 low"]
4pub type THRES1_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `THRES0_LOW` writer - interrupt of thres0 low"]
6pub type THRES0_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `THRES1_HIGH` writer - interrupt of thres1 high"]
8pub type THRES1_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `THRES0_HIGH` writer - interrupt of thres0 high"]
10pub type THRES0_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `ADC2_DONE` writer - interrupt of sar2 done"]
12pub type ADC2_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `ADC1_DONE` writer - interrupt of sar1 done"]
14pub type ADC1_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[cfg(feature = "impl-register-debug")]
16impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
17    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
18        write!(f, "(not readable)")
19    }
20}
21impl W {
22    #[doc = "Bit 26 - interrupt of thres1 low"]
23    #[inline(always)]
24    pub fn thres1_low(&mut self) -> THRES1_LOW_W<INT_CLR_SPEC> {
25        THRES1_LOW_W::new(self, 26)
26    }
27    #[doc = "Bit 27 - interrupt of thres0 low"]
28    #[inline(always)]
29    pub fn thres0_low(&mut self) -> THRES0_LOW_W<INT_CLR_SPEC> {
30        THRES0_LOW_W::new(self, 27)
31    }
32    #[doc = "Bit 28 - interrupt of thres1 high"]
33    #[inline(always)]
34    pub fn thres1_high(&mut self) -> THRES1_HIGH_W<INT_CLR_SPEC> {
35        THRES1_HIGH_W::new(self, 28)
36    }
37    #[doc = "Bit 29 - interrupt of thres0 high"]
38    #[inline(always)]
39    pub fn thres0_high(&mut self) -> THRES0_HIGH_W<INT_CLR_SPEC> {
40        THRES0_HIGH_W::new(self, 29)
41    }
42    #[doc = "Bit 30 - interrupt of sar2 done"]
43    #[inline(always)]
44    pub fn adc2_done(&mut self) -> ADC2_DONE_W<INT_CLR_SPEC> {
45        ADC2_DONE_W::new(self, 30)
46    }
47    #[doc = "Bit 31 - interrupt of sar1 done"]
48    #[inline(always)]
49    pub fn adc1_done(&mut self) -> ADC1_DONE_W<INT_CLR_SPEC> {
50        ADC1_DONE_W::new(self, 31)
51    }
52}
53#[doc = "clear interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
54pub struct INT_CLR_SPEC;
55impl crate::RegisterSpec for INT_CLR_SPEC {
56    type Ux = u32;
57}
58#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
59impl crate::Writable for INT_CLR_SPEC {
60    type Safety = crate::Unsafe;
61    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xfc00_0000;
63}
64#[doc = "`reset()` method sets INT_CLR to value 0"]
65impl crate::Resettable for INT_CLR_SPEC {
66    const RESET_VALUE: u32 = 0;
67}
esp32s3/apb_saradc/int_clr.rs

esp32s3/apb_saradc/
int_clr.rs
