1#[doc = "Register `USER` reader"]
2pub type R = crate::R<USER_SPEC>;
3#[doc = "Register `USER` writer"]
4pub type W = crate::W<USER_SPEC>;
5#[doc = "Field `CK_OUT_EDGE` reader - This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK."]
6pub type CK_OUT_EDGE_R = crate::BitReader;
7#[doc = "Field `CK_OUT_EDGE` writer - This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK."]
8pub type CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FWRITE_DUAL` reader - Set this bit to enable 2-bm in DOUT phase in SPI1 write operation."]
10pub type FWRITE_DUAL_R = crate::BitReader;
11#[doc = "Field `FWRITE_DUAL` writer - Set this bit to enable 2-bm in DOUT phase in SPI1 write operation."]
12pub type FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FWRITE_QUAD` reader - Set this bit to enable 4-bm in DOUT phase in SPI1 write operation."]
14pub type FWRITE_QUAD_R = crate::BitReader;
15#[doc = "Field `FWRITE_QUAD` writer - Set this bit to enable 4-bm in DOUT phase in SPI1 write operation."]
16pub type FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FWRITE_DIO` reader - Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation."]
18pub type FWRITE_DIO_R = crate::BitReader;
19#[doc = "Field `FWRITE_DIO` writer - Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation."]
20pub type FWRITE_DIO_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FWRITE_QIO` reader - Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation."]
22pub type FWRITE_QIO_R = crate::BitReader;
23#[doc = "Field `FWRITE_QIO` writer - Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation."]
24pub type FWRITE_QIO_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `USR_MISO_HIGHPART` reader - DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable."]
26pub type USR_MISO_HIGHPART_R = crate::BitReader;
27#[doc = "Field `USR_MISO_HIGHPART` writer - DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable."]
28pub type USR_MISO_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `USR_MOSI_HIGHPART` reader - DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable."]
30pub type USR_MOSI_HIGHPART_R = crate::BitReader;
31#[doc = "Field `USR_MOSI_HIGHPART` writer - DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable."]
32pub type USR_MOSI_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `USR_DUMMY_IDLE` reader - SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable."]
34pub type USR_DUMMY_IDLE_R = crate::BitReader;
35#[doc = "Field `USR_DUMMY_IDLE` writer - SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable."]
36pub type USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `USR_MOSI` reader - Set this bit to enable the DOUT phase of an write-data operation."]
38pub type USR_MOSI_R = crate::BitReader;
39#[doc = "Field `USR_MOSI` writer - Set this bit to enable the DOUT phase of an write-data operation."]
40pub type USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `USR_MISO` reader - Set this bit to enable enable the DIN phase of a read-data operation."]
42pub type USR_MISO_R = crate::BitReader;
43#[doc = "Field `USR_MISO` writer - Set this bit to enable enable the DIN phase of a read-data operation."]
44pub type USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `USR_DUMMY` reader - Set this bit to enable enable the DUMMY phase of an operation."]
46pub type USR_DUMMY_R = crate::BitReader;
47#[doc = "Field `USR_DUMMY` writer - Set this bit to enable enable the DUMMY phase of an operation."]
48pub type USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `USR_ADDR` reader - Set this bit to enable enable the ADDR phase of an operation."]
50pub type USR_ADDR_R = crate::BitReader;
51#[doc = "Field `USR_ADDR` writer - Set this bit to enable enable the ADDR phase of an operation."]
52pub type USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `USR_COMMAND` reader - Set this bit to enable enable the CMD phase of an operation."]
54pub type USR_COMMAND_R = crate::BitReader;
55#[doc = "Field `USR_COMMAND` writer - Set this bit to enable enable the CMD phase of an operation."]
56pub type USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58 #[doc = "Bit 9 - This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK."]
59 #[inline(always)]
60 pub fn ck_out_edge(&self) -> CK_OUT_EDGE_R {
61 CK_OUT_EDGE_R::new(((self.bits >> 9) & 1) != 0)
62 }
63 #[doc = "Bit 12 - Set this bit to enable 2-bm in DOUT phase in SPI1 write operation."]
64 #[inline(always)]
65 pub fn fwrite_dual(&self) -> FWRITE_DUAL_R {
66 FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0)
67 }
68 #[doc = "Bit 13 - Set this bit to enable 4-bm in DOUT phase in SPI1 write operation."]
69 #[inline(always)]
70 pub fn fwrite_quad(&self) -> FWRITE_QUAD_R {
71 FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0)
72 }
73 #[doc = "Bit 14 - Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation."]
74 #[inline(always)]
75 pub fn fwrite_dio(&self) -> FWRITE_DIO_R {
76 FWRITE_DIO_R::new(((self.bits >> 14) & 1) != 0)
77 }
78 #[doc = "Bit 15 - Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation."]
79 #[inline(always)]
80 pub fn fwrite_qio(&self) -> FWRITE_QIO_R {
81 FWRITE_QIO_R::new(((self.bits >> 15) & 1) != 0)
82 }
83 #[doc = "Bit 24 - DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable."]
84 #[inline(always)]
85 pub fn usr_miso_highpart(&self) -> USR_MISO_HIGHPART_R {
86 USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0)
87 }
88 #[doc = "Bit 25 - DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable."]
89 #[inline(always)]
90 pub fn usr_mosi_highpart(&self) -> USR_MOSI_HIGHPART_R {
91 USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0)
92 }
93 #[doc = "Bit 26 - SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable."]
94 #[inline(always)]
95 pub fn usr_dummy_idle(&self) -> USR_DUMMY_IDLE_R {
96 USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0)
97 }
98 #[doc = "Bit 27 - Set this bit to enable the DOUT phase of an write-data operation."]
99 #[inline(always)]
100 pub fn usr_mosi(&self) -> USR_MOSI_R {
101 USR_MOSI_R::new(((self.bits >> 27) & 1) != 0)
102 }
103 #[doc = "Bit 28 - Set this bit to enable enable the DIN phase of a read-data operation."]
104 #[inline(always)]
105 pub fn usr_miso(&self) -> USR_MISO_R {
106 USR_MISO_R::new(((self.bits >> 28) & 1) != 0)
107 }
108 #[doc = "Bit 29 - Set this bit to enable enable the DUMMY phase of an operation."]
109 #[inline(always)]
110 pub fn usr_dummy(&self) -> USR_DUMMY_R {
111 USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0)
112 }
113 #[doc = "Bit 30 - Set this bit to enable enable the ADDR phase of an operation."]
114 #[inline(always)]
115 pub fn usr_addr(&self) -> USR_ADDR_R {
116 USR_ADDR_R::new(((self.bits >> 30) & 1) != 0)
117 }
118 #[doc = "Bit 31 - Set this bit to enable enable the CMD phase of an operation."]
119 #[inline(always)]
120 pub fn usr_command(&self) -> USR_COMMAND_R {
121 USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0)
122 }
123}
124#[cfg(feature = "impl-register-debug")]
125impl core::fmt::Debug for R {
126 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
127 f.debug_struct("USER")
128 .field("ck_out_edge", &self.ck_out_edge())
129 .field("fwrite_dual", &self.fwrite_dual())
130 .field("fwrite_quad", &self.fwrite_quad())
131 .field("fwrite_dio", &self.fwrite_dio())
132 .field("fwrite_qio", &self.fwrite_qio())
133 .field("usr_miso_highpart", &self.usr_miso_highpart())
134 .field("usr_mosi_highpart", &self.usr_mosi_highpart())
135 .field("usr_dummy_idle", &self.usr_dummy_idle())
136 .field("usr_mosi", &self.usr_mosi())
137 .field("usr_miso", &self.usr_miso())
138 .field("usr_dummy", &self.usr_dummy())
139 .field("usr_addr", &self.usr_addr())
140 .field("usr_command", &self.usr_command())
141 .finish()
142 }
143}
144impl W {
145 #[doc = "Bit 9 - This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK."]
146 #[inline(always)]
147 pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
148 CK_OUT_EDGE_W::new(self, 9)
149 }
150 #[doc = "Bit 12 - Set this bit to enable 2-bm in DOUT phase in SPI1 write operation."]
151 #[inline(always)]
152 pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<USER_SPEC> {
153 FWRITE_DUAL_W::new(self, 12)
154 }
155 #[doc = "Bit 13 - Set this bit to enable 4-bm in DOUT phase in SPI1 write operation."]
156 #[inline(always)]
157 pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<USER_SPEC> {
158 FWRITE_QUAD_W::new(self, 13)
159 }
160 #[doc = "Bit 14 - Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation."]
161 #[inline(always)]
162 pub fn fwrite_dio(&mut self) -> FWRITE_DIO_W<USER_SPEC> {
163 FWRITE_DIO_W::new(self, 14)
164 }
165 #[doc = "Bit 15 - Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation."]
166 #[inline(always)]
167 pub fn fwrite_qio(&mut self) -> FWRITE_QIO_W<USER_SPEC> {
168 FWRITE_QIO_W::new(self, 15)
169 }
170 #[doc = "Bit 24 - DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable."]
171 #[inline(always)]
172 pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<USER_SPEC> {
173 USR_MISO_HIGHPART_W::new(self, 24)
174 }
175 #[doc = "Bit 25 - DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable."]
176 #[inline(always)]
177 pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<USER_SPEC> {
178 USR_MOSI_HIGHPART_W::new(self, 25)
179 }
180 #[doc = "Bit 26 - SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable."]
181 #[inline(always)]
182 pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
183 USR_DUMMY_IDLE_W::new(self, 26)
184 }
185 #[doc = "Bit 27 - Set this bit to enable the DOUT phase of an write-data operation."]
186 #[inline(always)]
187 pub fn usr_mosi(&mut self) -> USR_MOSI_W<USER_SPEC> {
188 USR_MOSI_W::new(self, 27)
189 }
190 #[doc = "Bit 28 - Set this bit to enable enable the DIN phase of a read-data operation."]
191 #[inline(always)]
192 pub fn usr_miso(&mut self) -> USR_MISO_W<USER_SPEC> {
193 USR_MISO_W::new(self, 28)
194 }
195 #[doc = "Bit 29 - Set this bit to enable enable the DUMMY phase of an operation."]
196 #[inline(always)]
197 pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
198 USR_DUMMY_W::new(self, 29)
199 }
200 #[doc = "Bit 30 - Set this bit to enable enable the ADDR phase of an operation."]
201 #[inline(always)]
202 pub fn usr_addr(&mut self) -> USR_ADDR_W<USER_SPEC> {
203 USR_ADDR_W::new(self, 30)
204 }
205 #[doc = "Bit 31 - Set this bit to enable enable the CMD phase of an operation."]
206 #[inline(always)]
207 pub fn usr_command(&mut self) -> USR_COMMAND_W<USER_SPEC> {
208 USR_COMMAND_W::new(self, 31)
209 }
210}
211#[doc = "SPI1 user register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct USER_SPEC;
213impl crate::RegisterSpec for USER_SPEC {
214 type Ux = u32;
215}
216#[doc = "`read()` method returns [`user::R`](R) reader structure"]
217impl crate::Readable for USER_SPEC {}
218#[doc = "`write(|w| ..)` method takes [`user::W`](W) writer structure"]
219impl crate::Writable for USER_SPEC {
220 type Safety = crate::Unsafe;
221 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
222 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
223}
224#[doc = "`reset()` method sets USER to value 0x8000_0000"]
225impl crate::Resettable for USER_SPEC {
226 const RESET_VALUE: u32 = 0x8000_0000;
227}