esp32s3/system/
core_1_control_0.rs

1#[doc = "Register `CORE_1_CONTROL_0` reader"]
2pub type R = crate::R<CORE_1_CONTROL_0_SPEC>;
3#[doc = "Register `CORE_1_CONTROL_0` writer"]
4pub type W = crate::W<CORE_1_CONTROL_0_SPEC>;
5#[doc = "Field `CONTROL_CORE_1_RUNSTALL` reader - Set 1 to stall core1"]
6pub type CONTROL_CORE_1_RUNSTALL_R = crate::BitReader;
7#[doc = "Field `CONTROL_CORE_1_RUNSTALL` writer - Set 1 to stall core1"]
8pub type CONTROL_CORE_1_RUNSTALL_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CONTROL_CORE_1_CLKGATE_EN` reader - Set 1 to open core1 clock"]
10pub type CONTROL_CORE_1_CLKGATE_EN_R = crate::BitReader;
11#[doc = "Field `CONTROL_CORE_1_CLKGATE_EN` writer - Set 1 to open core1 clock"]
12pub type CONTROL_CORE_1_CLKGATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CONTROL_CORE_1_RESETING` reader - Set 1 to let core1 reset"]
14pub type CONTROL_CORE_1_RESETING_R = crate::BitReader;
15#[doc = "Field `CONTROL_CORE_1_RESETING` writer - Set 1 to let core1 reset"]
16pub type CONTROL_CORE_1_RESETING_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - Set 1 to stall core1"]
19    #[inline(always)]
20    pub fn control_core_1_runstall(&self) -> CONTROL_CORE_1_RUNSTALL_R {
21        CONTROL_CORE_1_RUNSTALL_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - Set 1 to open core1 clock"]
24    #[inline(always)]
25    pub fn control_core_1_clkgate_en(&self) -> CONTROL_CORE_1_CLKGATE_EN_R {
26        CONTROL_CORE_1_CLKGATE_EN_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 2 - Set 1 to let core1 reset"]
29    #[inline(always)]
30    pub fn control_core_1_reseting(&self) -> CONTROL_CORE_1_RESETING_R {
31        CONTROL_CORE_1_RESETING_R::new(((self.bits >> 2) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("CORE_1_CONTROL_0")
38            .field("control_core_1_runstall", &self.control_core_1_runstall())
39            .field(
40                "control_core_1_clkgate_en",
41                &self.control_core_1_clkgate_en(),
42            )
43            .field("control_core_1_reseting", &self.control_core_1_reseting())
44            .finish()
45    }
46}
47impl W {
48    #[doc = "Bit 0 - Set 1 to stall core1"]
49    #[inline(always)]
50    pub fn control_core_1_runstall(&mut self) -> CONTROL_CORE_1_RUNSTALL_W<CORE_1_CONTROL_0_SPEC> {
51        CONTROL_CORE_1_RUNSTALL_W::new(self, 0)
52    }
53    #[doc = "Bit 1 - Set 1 to open core1 clock"]
54    #[inline(always)]
55    pub fn control_core_1_clkgate_en(
56        &mut self,
57    ) -> CONTROL_CORE_1_CLKGATE_EN_W<CORE_1_CONTROL_0_SPEC> {
58        CONTROL_CORE_1_CLKGATE_EN_W::new(self, 1)
59    }
60    #[doc = "Bit 2 - Set 1 to let core1 reset"]
61    #[inline(always)]
62    pub fn control_core_1_reseting(&mut self) -> CONTROL_CORE_1_RESETING_W<CORE_1_CONTROL_0_SPEC> {
63        CONTROL_CORE_1_RESETING_W::new(self, 2)
64    }
65}
66#[doc = "Core0 control regiter 0\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_control_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_control_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
67pub struct CORE_1_CONTROL_0_SPEC;
68impl crate::RegisterSpec for CORE_1_CONTROL_0_SPEC {
69    type Ux = u32;
70}
71#[doc = "`read()` method returns [`core_1_control_0::R`](R) reader structure"]
72impl crate::Readable for CORE_1_CONTROL_0_SPEC {}
73#[doc = "`write(|w| ..)` method takes [`core_1_control_0::W`](W) writer structure"]
74impl crate::Writable for CORE_1_CONTROL_0_SPEC {
75    type Safety = crate::Unsafe;
76    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
77    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
78}
79#[doc = "`reset()` method sets CORE_1_CONTROL_0 to value 0x04"]
80impl crate::Resettable for CORE_1_CONTROL_0_SPEC {
81    const RESET_VALUE: u32 = 0x04;
82}
esp32s3/system/core_1_control_0.rs

esp32s3/system/
core_1_control_0.rs
