1#[doc = "Register `CTR` reader"]
2pub type R = crate::R<CTR_SPEC>;
3#[doc = "Register `CTR` writer"]
4pub type W = crate::W<CTR_SPEC>;
5#[doc = "Field `SDA_FORCE_OUT` reader - 0: direct output; 1: open drain output."]
6pub type SDA_FORCE_OUT_R = crate::BitReader;
7#[doc = "Field `SDA_FORCE_OUT` writer - 0: direct output; 1: open drain output."]
8pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SCL_FORCE_OUT` reader - 0: direct output; 1: open drain output."]
10pub type SCL_FORCE_OUT_R = crate::BitReader;
11#[doc = "Field `SCL_FORCE_OUT` writer - 0: direct output; 1: open drain output."]
12pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SAMPLE_SCL_LEVEL` reader - This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level."]
14pub type SAMPLE_SCL_LEVEL_R = crate::BitReader;
15#[doc = "Field `SAMPLE_SCL_LEVEL` writer - This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level."]
16pub type SAMPLE_SCL_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RX_FULL_ACK_LEVEL` reader - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
18pub type RX_FULL_ACK_LEVEL_R = crate::BitReader;
19#[doc = "Field `RX_FULL_ACK_LEVEL` writer - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
20pub type RX_FULL_ACK_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MS_MODE` reader - Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave."]
22pub type MS_MODE_R = crate::BitReader;
23#[doc = "Field `MS_MODE` writer - Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave."]
24pub type MS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TRANS_START` writer - Set this bit to start sending the data in txfifo."]
26pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `TX_LSB_FIRST` reader - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit; 0: send data from the most significant bit."]
28pub type TX_LSB_FIRST_R = crate::BitReader;
29#[doc = "Field `TX_LSB_FIRST` writer - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit; 0: send data from the most significant bit."]
30pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `RX_LSB_FIRST` reader - This bit is used to control the storage mode for received data. 1: receive data from the least significant bit; 0: receive data from the most significant bit."]
32pub type RX_LSB_FIRST_R = crate::BitReader;
33#[doc = "Field `RX_LSB_FIRST` writer - This bit is used to control the storage mode for received data. 1: receive data from the least significant bit; 0: receive data from the most significant bit."]
34pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `CLK_EN` reader - Reserved"]
36pub type CLK_EN_R = crate::BitReader;
37#[doc = "Field `CLK_EN` writer - Reserved"]
38pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `ARBITRATION_EN` reader - This is the enable bit for arbitration_lost."]
40pub type ARBITRATION_EN_R = crate::BitReader;
41#[doc = "Field `ARBITRATION_EN` writer - This is the enable bit for arbitration_lost."]
42pub type ARBITRATION_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `FSM_RST` writer - This register is used to reset the scl FMS."]
44pub type FSM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CONF_UPGATE` writer - synchronization bit"]
46pub type CONF_UPGATE_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `SLV_TX_AUTO_START_EN` reader - This is the enable bit for slave to send data automatically"]
48pub type SLV_TX_AUTO_START_EN_R = crate::BitReader;
49#[doc = "Field `SLV_TX_AUTO_START_EN` writer - This is the enable bit for slave to send data automatically"]
50pub type SLV_TX_AUTO_START_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
51#[doc = "Field `ADDR_10BIT_RW_CHECK_EN` reader - This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol"]
52pub type ADDR_10BIT_RW_CHECK_EN_R = crate::BitReader;
53#[doc = "Field `ADDR_10BIT_RW_CHECK_EN` writer - This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol"]
54pub type ADDR_10BIT_RW_CHECK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
55#[doc = "Field `ADDR_BROADCASTING_EN` reader - This is the enable bit to support the 7bit general call function."]
56pub type ADDR_BROADCASTING_EN_R = crate::BitReader;
57#[doc = "Field `ADDR_BROADCASTING_EN` writer - This is the enable bit to support the 7bit general call function."]
58pub type ADDR_BROADCASTING_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
59impl R {
60 #[doc = "Bit 0 - 0: direct output; 1: open drain output."]
61 #[inline(always)]
62 pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R {
63 SDA_FORCE_OUT_R::new((self.bits & 1) != 0)
64 }
65 #[doc = "Bit 1 - 0: direct output; 1: open drain output."]
66 #[inline(always)]
67 pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R {
68 SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0)
69 }
70 #[doc = "Bit 2 - This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level."]
71 #[inline(always)]
72 pub fn sample_scl_level(&self) -> SAMPLE_SCL_LEVEL_R {
73 SAMPLE_SCL_LEVEL_R::new(((self.bits >> 2) & 1) != 0)
74 }
75 #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
76 #[inline(always)]
77 pub fn rx_full_ack_level(&self) -> RX_FULL_ACK_LEVEL_R {
78 RX_FULL_ACK_LEVEL_R::new(((self.bits >> 3) & 1) != 0)
79 }
80 #[doc = "Bit 4 - Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave."]
81 #[inline(always)]
82 pub fn ms_mode(&self) -> MS_MODE_R {
83 MS_MODE_R::new(((self.bits >> 4) & 1) != 0)
84 }
85 #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit; 0: send data from the most significant bit."]
86 #[inline(always)]
87 pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R {
88 TX_LSB_FIRST_R::new(((self.bits >> 6) & 1) != 0)
89 }
90 #[doc = "Bit 7 - This bit is used to control the storage mode for received data. 1: receive data from the least significant bit; 0: receive data from the most significant bit."]
91 #[inline(always)]
92 pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R {
93 RX_LSB_FIRST_R::new(((self.bits >> 7) & 1) != 0)
94 }
95 #[doc = "Bit 8 - Reserved"]
96 #[inline(always)]
97 pub fn clk_en(&self) -> CLK_EN_R {
98 CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
99 }
100 #[doc = "Bit 9 - This is the enable bit for arbitration_lost."]
101 #[inline(always)]
102 pub fn arbitration_en(&self) -> ARBITRATION_EN_R {
103 ARBITRATION_EN_R::new(((self.bits >> 9) & 1) != 0)
104 }
105 #[doc = "Bit 12 - This is the enable bit for slave to send data automatically"]
106 #[inline(always)]
107 pub fn slv_tx_auto_start_en(&self) -> SLV_TX_AUTO_START_EN_R {
108 SLV_TX_AUTO_START_EN_R::new(((self.bits >> 12) & 1) != 0)
109 }
110 #[doc = "Bit 13 - This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol"]
111 #[inline(always)]
112 pub fn addr_10bit_rw_check_en(&self) -> ADDR_10BIT_RW_CHECK_EN_R {
113 ADDR_10BIT_RW_CHECK_EN_R::new(((self.bits >> 13) & 1) != 0)
114 }
115 #[doc = "Bit 14 - This is the enable bit to support the 7bit general call function."]
116 #[inline(always)]
117 pub fn addr_broadcasting_en(&self) -> ADDR_BROADCASTING_EN_R {
118 ADDR_BROADCASTING_EN_R::new(((self.bits >> 14) & 1) != 0)
119 }
120}
121#[cfg(feature = "impl-register-debug")]
122impl core::fmt::Debug for R {
123 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
124 f.debug_struct("CTR")
125 .field("sda_force_out", &self.sda_force_out())
126 .field("scl_force_out", &self.scl_force_out())
127 .field("sample_scl_level", &self.sample_scl_level())
128 .field("rx_full_ack_level", &self.rx_full_ack_level())
129 .field("ms_mode", &self.ms_mode())
130 .field("tx_lsb_first", &self.tx_lsb_first())
131 .field("rx_lsb_first", &self.rx_lsb_first())
132 .field("clk_en", &self.clk_en())
133 .field("arbitration_en", &self.arbitration_en())
134 .field("slv_tx_auto_start_en", &self.slv_tx_auto_start_en())
135 .field("addr_10bit_rw_check_en", &self.addr_10bit_rw_check_en())
136 .field("addr_broadcasting_en", &self.addr_broadcasting_en())
137 .finish()
138 }
139}
140impl W {
141 #[doc = "Bit 0 - 0: direct output; 1: open drain output."]
142 #[inline(always)]
143 pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTR_SPEC> {
144 SDA_FORCE_OUT_W::new(self, 0)
145 }
146 #[doc = "Bit 1 - 0: direct output; 1: open drain output."]
147 #[inline(always)]
148 pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTR_SPEC> {
149 SCL_FORCE_OUT_W::new(self, 1)
150 }
151 #[doc = "Bit 2 - This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level."]
152 #[inline(always)]
153 pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W<CTR_SPEC> {
154 SAMPLE_SCL_LEVEL_W::new(self, 2)
155 }
156 #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
157 #[inline(always)]
158 pub fn rx_full_ack_level(&mut self) -> RX_FULL_ACK_LEVEL_W<CTR_SPEC> {
159 RX_FULL_ACK_LEVEL_W::new(self, 3)
160 }
161 #[doc = "Bit 4 - Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave."]
162 #[inline(always)]
163 pub fn ms_mode(&mut self) -> MS_MODE_W<CTR_SPEC> {
164 MS_MODE_W::new(self, 4)
165 }
166 #[doc = "Bit 5 - Set this bit to start sending the data in txfifo."]
167 #[inline(always)]
168 pub fn trans_start(&mut self) -> TRANS_START_W<CTR_SPEC> {
169 TRANS_START_W::new(self, 5)
170 }
171 #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit; 0: send data from the most significant bit."]
172 #[inline(always)]
173 pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTR_SPEC> {
174 TX_LSB_FIRST_W::new(self, 6)
175 }
176 #[doc = "Bit 7 - This bit is used to control the storage mode for received data. 1: receive data from the least significant bit; 0: receive data from the most significant bit."]
177 #[inline(always)]
178 pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTR_SPEC> {
179 RX_LSB_FIRST_W::new(self, 7)
180 }
181 #[doc = "Bit 8 - Reserved"]
182 #[inline(always)]
183 pub fn clk_en(&mut self) -> CLK_EN_W<CTR_SPEC> {
184 CLK_EN_W::new(self, 8)
185 }
186 #[doc = "Bit 9 - This is the enable bit for arbitration_lost."]
187 #[inline(always)]
188 pub fn arbitration_en(&mut self) -> ARBITRATION_EN_W<CTR_SPEC> {
189 ARBITRATION_EN_W::new(self, 9)
190 }
191 #[doc = "Bit 10 - This register is used to reset the scl FMS."]
192 #[inline(always)]
193 pub fn fsm_rst(&mut self) -> FSM_RST_W<CTR_SPEC> {
194 FSM_RST_W::new(self, 10)
195 }
196 #[doc = "Bit 11 - synchronization bit"]
197 #[inline(always)]
198 pub fn conf_upgate(&mut self) -> CONF_UPGATE_W<CTR_SPEC> {
199 CONF_UPGATE_W::new(self, 11)
200 }
201 #[doc = "Bit 12 - This is the enable bit for slave to send data automatically"]
202 #[inline(always)]
203 pub fn slv_tx_auto_start_en(&mut self) -> SLV_TX_AUTO_START_EN_W<CTR_SPEC> {
204 SLV_TX_AUTO_START_EN_W::new(self, 12)
205 }
206 #[doc = "Bit 13 - This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol"]
207 #[inline(always)]
208 pub fn addr_10bit_rw_check_en(&mut self) -> ADDR_10BIT_RW_CHECK_EN_W<CTR_SPEC> {
209 ADDR_10BIT_RW_CHECK_EN_W::new(self, 13)
210 }
211 #[doc = "Bit 14 - This is the enable bit to support the 7bit general call function."]
212 #[inline(always)]
213 pub fn addr_broadcasting_en(&mut self) -> ADDR_BROADCASTING_EN_W<CTR_SPEC> {
214 ADDR_BROADCASTING_EN_W::new(self, 14)
215 }
216}
217#[doc = "Transmission setting\n\nYou can [`read`](crate::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
218pub struct CTR_SPEC;
219impl crate::RegisterSpec for CTR_SPEC {
220 type Ux = u32;
221}
222#[doc = "`read()` method returns [`ctr::R`](R) reader structure"]
223impl crate::Readable for CTR_SPEC {}
224#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"]
225impl crate::Writable for CTR_SPEC {
226 type Safety = crate::Unsafe;
227 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
228 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
229}
230#[doc = "`reset()` method sets CTR to value 0x020b"]
231impl crate::Resettable for CTR_SPEC {
232 const RESET_VALUE: u32 = 0x020b;
233}