esp32s3/ledc/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `TIMER_OVF(0-3)` writer - Set this bit to clear the TIMER%s_OVF interrupt."]
4pub type TIMER_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `DUTY_CHNG_END_CH(0-7)` writer - Set this bit to clear the DUTY_CHNG_END_CH%s interrupt."]
6pub type DUTY_CHNG_END_CH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `OVF_CNT_CH(0-7)` writer - Set this bit to clear the OVF_CNT_CH%s interrupt."]
8pub type OVF_CNT_CH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[cfg(feature = "impl-register-debug")]
10impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
11    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
12        write!(f, "(not readable)")
13    }
14}
15impl W {
16    #[doc = "Set this bit to clear the TIMER(0-3)_OVF interrupt."]
17    #[doc = ""]
18    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
19    #[inline(always)]
20    pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_CLR_SPEC> {
21        #[allow(clippy::no_effect)]
22        [(); 4][n as usize];
23        TIMER_OVF_W::new(self, n)
24    }
25    #[doc = "Bit 0 - Set this bit to clear the TIMER0_OVF interrupt."]
26    #[inline(always)]
27    pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
28        TIMER_OVF_W::new(self, 0)
29    }
30    #[doc = "Bit 1 - Set this bit to clear the TIMER1_OVF interrupt."]
31    #[inline(always)]
32    pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
33        TIMER_OVF_W::new(self, 1)
34    }
35    #[doc = "Bit 2 - Set this bit to clear the TIMER2_OVF interrupt."]
36    #[inline(always)]
37    pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
38        TIMER_OVF_W::new(self, 2)
39    }
40    #[doc = "Bit 3 - Set this bit to clear the TIMER3_OVF interrupt."]
41    #[inline(always)]
42    pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
43        TIMER_OVF_W::new(self, 3)
44    }
45    #[doc = "Set this bit to clear the DUTY_CHNG_END_CH(0-7) interrupt."]
46    #[doc = ""]
47    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
48    #[inline(always)]
49    pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
50        #[allow(clippy::no_effect)]
51        [(); 8][n as usize];
52        DUTY_CHNG_END_CH_W::new(self, n + 4)
53    }
54    #[doc = "Bit 4 - Set this bit to clear the DUTY_CHNG_END_CH0 interrupt."]
55    #[inline(always)]
56    pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
57        DUTY_CHNG_END_CH_W::new(self, 4)
58    }
59    #[doc = "Bit 5 - Set this bit to clear the DUTY_CHNG_END_CH1 interrupt."]
60    #[inline(always)]
61    pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
62        DUTY_CHNG_END_CH_W::new(self, 5)
63    }
64    #[doc = "Bit 6 - Set this bit to clear the DUTY_CHNG_END_CH2 interrupt."]
65    #[inline(always)]
66    pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
67        DUTY_CHNG_END_CH_W::new(self, 6)
68    }
69    #[doc = "Bit 7 - Set this bit to clear the DUTY_CHNG_END_CH3 interrupt."]
70    #[inline(always)]
71    pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
72        DUTY_CHNG_END_CH_W::new(self, 7)
73    }
74    #[doc = "Bit 8 - Set this bit to clear the DUTY_CHNG_END_CH4 interrupt."]
75    #[inline(always)]
76    pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
77        DUTY_CHNG_END_CH_W::new(self, 8)
78    }
79    #[doc = "Bit 9 - Set this bit to clear the DUTY_CHNG_END_CH5 interrupt."]
80    #[inline(always)]
81    pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
82        DUTY_CHNG_END_CH_W::new(self, 9)
83    }
84    #[doc = "Bit 10 - Set this bit to clear the DUTY_CHNG_END_CH6 interrupt."]
85    #[inline(always)]
86    pub fn duty_chng_end_ch6(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
87        DUTY_CHNG_END_CH_W::new(self, 10)
88    }
89    #[doc = "Bit 11 - Set this bit to clear the DUTY_CHNG_END_CH7 interrupt."]
90    #[inline(always)]
91    pub fn duty_chng_end_ch7(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
92        DUTY_CHNG_END_CH_W::new(self, 11)
93    }
94    #[doc = "Set this bit to clear the OVF_CNT_CH(0-7) interrupt."]
95    #[doc = ""]
96    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
97    #[inline(always)]
98    pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
99        #[allow(clippy::no_effect)]
100        [(); 8][n as usize];
101        OVF_CNT_CH_W::new(self, n + 12)
102    }
103    #[doc = "Bit 12 - Set this bit to clear the OVF_CNT_CH0 interrupt."]
104    #[inline(always)]
105    pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
106        OVF_CNT_CH_W::new(self, 12)
107    }
108    #[doc = "Bit 13 - Set this bit to clear the OVF_CNT_CH1 interrupt."]
109    #[inline(always)]
110    pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
111        OVF_CNT_CH_W::new(self, 13)
112    }
113    #[doc = "Bit 14 - Set this bit to clear the OVF_CNT_CH2 interrupt."]
114    #[inline(always)]
115    pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
116        OVF_CNT_CH_W::new(self, 14)
117    }
118    #[doc = "Bit 15 - Set this bit to clear the OVF_CNT_CH3 interrupt."]
119    #[inline(always)]
120    pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
121        OVF_CNT_CH_W::new(self, 15)
122    }
123    #[doc = "Bit 16 - Set this bit to clear the OVF_CNT_CH4 interrupt."]
124    #[inline(always)]
125    pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
126        OVF_CNT_CH_W::new(self, 16)
127    }
128    #[doc = "Bit 17 - Set this bit to clear the OVF_CNT_CH5 interrupt."]
129    #[inline(always)]
130    pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
131        OVF_CNT_CH_W::new(self, 17)
132    }
133    #[doc = "Bit 18 - Set this bit to clear the OVF_CNT_CH6 interrupt."]
134    #[inline(always)]
135    pub fn ovf_cnt_ch6(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
136        OVF_CNT_CH_W::new(self, 18)
137    }
138    #[doc = "Bit 19 - Set this bit to clear the OVF_CNT_CH7 interrupt."]
139    #[inline(always)]
140    pub fn ovf_cnt_ch7(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
141        OVF_CNT_CH_W::new(self, 19)
142    }
143}
144#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
145pub struct INT_CLR_SPEC;
146impl crate::RegisterSpec for INT_CLR_SPEC {
147    type Ux = u32;
148}
149#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
150impl crate::Writable for INT_CLR_SPEC {
151    type Safety = crate::Unsafe;
152    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
153    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x000f_ffff;
154}
155#[doc = "`reset()` method sets INT_CLR to value 0"]
156impl crate::Resettable for INT_CLR_SPEC {
157    const RESET_VALUE: u32 = 0;
158}
esp32s3/ledc/int_clr.rs

esp32s3/ledc/
int_clr.rs
