esp32s3/rtc_cntl/
ulp_cp_timer.rs

1#[doc = "Register `ULP_CP_TIMER` reader"]
2pub type R = crate::R<ULP_CP_TIMER_SPEC>;
3#[doc = "Register `ULP_CP_TIMER` writer"]
4pub type W = crate::W<ULP_CP_TIMER_SPEC>;
5#[doc = "Field `ULP_CP_PC_INIT` reader - ULP-coprocessor PC initial address"]
6pub type ULP_CP_PC_INIT_R = crate::FieldReader<u16>;
7#[doc = "Field `ULP_CP_PC_INIT` writer - ULP-coprocessor PC initial address"]
8pub type ULP_CP_PC_INIT_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
9#[doc = "Field `ULP_CP_GPIO_WAKEUP_ENA` reader - ULP-coprocessor wakeup by GPIO enable"]
10pub type ULP_CP_GPIO_WAKEUP_ENA_R = crate::BitReader;
11#[doc = "Field `ULP_CP_GPIO_WAKEUP_ENA` writer - ULP-coprocessor wakeup by GPIO enable"]
12pub type ULP_CP_GPIO_WAKEUP_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ULP_CP_GPIO_WAKEUP_CLR` writer - ULP-coprocessor wakeup by GPIO state clear"]
14pub type ULP_CP_GPIO_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `ULP_CP_SLP_TIMER_EN` reader - ULP-coprocessor timer enable bit"]
16pub type ULP_CP_SLP_TIMER_EN_R = crate::BitReader;
17#[doc = "Field `ULP_CP_SLP_TIMER_EN` writer - ULP-coprocessor timer enable bit"]
18pub type ULP_CP_SLP_TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
19impl R {
20    #[doc = "Bits 0:10 - ULP-coprocessor PC initial address"]
21    #[inline(always)]
22    pub fn ulp_cp_pc_init(&self) -> ULP_CP_PC_INIT_R {
23        ULP_CP_PC_INIT_R::new((self.bits & 0x07ff) as u16)
24    }
25    #[doc = "Bit 29 - ULP-coprocessor wakeup by GPIO enable"]
26    #[inline(always)]
27    pub fn ulp_cp_gpio_wakeup_ena(&self) -> ULP_CP_GPIO_WAKEUP_ENA_R {
28        ULP_CP_GPIO_WAKEUP_ENA_R::new(((self.bits >> 29) & 1) != 0)
29    }
30    #[doc = "Bit 31 - ULP-coprocessor timer enable bit"]
31    #[inline(always)]
32    pub fn ulp_cp_slp_timer_en(&self) -> ULP_CP_SLP_TIMER_EN_R {
33        ULP_CP_SLP_TIMER_EN_R::new(((self.bits >> 31) & 1) != 0)
34    }
35}
36#[cfg(feature = "impl-register-debug")]
37impl core::fmt::Debug for R {
38    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
39        f.debug_struct("ULP_CP_TIMER")
40            .field("ulp_cp_pc_init", &self.ulp_cp_pc_init())
41            .field("ulp_cp_gpio_wakeup_ena", &self.ulp_cp_gpio_wakeup_ena())
42            .field("ulp_cp_slp_timer_en", &self.ulp_cp_slp_timer_en())
43            .finish()
44    }
45}
46impl W {
47    #[doc = "Bits 0:10 - ULP-coprocessor PC initial address"]
48    #[inline(always)]
49    pub fn ulp_cp_pc_init(&mut self) -> ULP_CP_PC_INIT_W<ULP_CP_TIMER_SPEC> {
50        ULP_CP_PC_INIT_W::new(self, 0)
51    }
52    #[doc = "Bit 29 - ULP-coprocessor wakeup by GPIO enable"]
53    #[inline(always)]
54    pub fn ulp_cp_gpio_wakeup_ena(&mut self) -> ULP_CP_GPIO_WAKEUP_ENA_W<ULP_CP_TIMER_SPEC> {
55        ULP_CP_GPIO_WAKEUP_ENA_W::new(self, 29)
56    }
57    #[doc = "Bit 30 - ULP-coprocessor wakeup by GPIO state clear"]
58    #[inline(always)]
59    pub fn ulp_cp_gpio_wakeup_clr(&mut self) -> ULP_CP_GPIO_WAKEUP_CLR_W<ULP_CP_TIMER_SPEC> {
60        ULP_CP_GPIO_WAKEUP_CLR_W::new(self, 30)
61    }
62    #[doc = "Bit 31 - ULP-coprocessor timer enable bit"]
63    #[inline(always)]
64    pub fn ulp_cp_slp_timer_en(&mut self) -> ULP_CP_SLP_TIMER_EN_W<ULP_CP_TIMER_SPEC> {
65        ULP_CP_SLP_TIMER_EN_W::new(self, 31)
66    }
67}
68#[doc = "configure ulp\n\nYou can [`read`](crate::Reg::read) this register and get [`ulp_cp_timer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ulp_cp_timer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
69pub struct ULP_CP_TIMER_SPEC;
70impl crate::RegisterSpec for ULP_CP_TIMER_SPEC {
71    type Ux = u32;
72}
73#[doc = "`read()` method returns [`ulp_cp_timer::R`](R) reader structure"]
74impl crate::Readable for ULP_CP_TIMER_SPEC {}
75#[doc = "`write(|w| ..)` method takes [`ulp_cp_timer::W`](W) writer structure"]
76impl crate::Writable for ULP_CP_TIMER_SPEC {
77    type Safety = crate::Unsafe;
78    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
79    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
80}
81#[doc = "`reset()` method sets ULP_CP_TIMER to value 0"]
82impl crate::Resettable for ULP_CP_TIMER_SPEC {
83    const RESET_VALUE: u32 = 0;
84}
esp32s3/rtc_cntl/ulp_cp_timer.rs

esp32s3/rtc_cntl/
ulp_cp_timer.rs
