1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 ctrl: CTRL,
6 _reserved1: [u8; 0x04],
7 clkdiv: CLKDIV,
8 clksrc: CLKSRC,
9 clkena: CLKENA,
10 tmout: TMOUT,
11 ctype: CTYPE,
12 blksiz: BLKSIZ,
13 bytcnt: BYTCNT,
14 intmask: INTMASK,
15 cmdarg: CMDARG,
16 cmd: CMD,
17 resp0: RESP0,
18 resp1: RESP1,
19 resp2: RESP2,
20 resp3: RESP3,
21 mintsts: MINTSTS,
22 rintsts: RINTSTS,
23 status: STATUS,
24 fifoth: FIFOTH,
25 cdetect: CDETECT,
26 wrtprt: WRTPRT,
27 _reserved21: [u8; 0x04],
28 tcbcnt: TCBCNT,
29 tbbcnt: TBBCNT,
30 debnce: DEBNCE,
31 usrid: USRID,
32 verid: VERID,
33 hcon: HCON,
34 uhs: UHS,
35 rst_n: RST_N,
36 _reserved29: [u8; 0x04],
37 bmod: BMOD,
38 pldmnd: PLDMND,
39 dbaddr: DBADDR,
40 idsts: IDSTS,
41 idinten: IDINTEN,
42 dscaddr: DSCADDR,
43 bufaddr: BUFADDR,
44 _reserved36: [u8; 0x64],
45 cardthrctl: CARDTHRCTL,
46 _reserved37: [u8; 0x08],
47 emmcddr: EMMCDDR,
48 enshift: ENSHIFT,
49 _reserved39: [u8; 0xec],
50 buffifo: BUFFIFO,
51 _reserved40: [u8; 0x05fc],
52 clk_edge_sel: CLK_EDGE_SEL,
53}
54impl RegisterBlock {
55 #[doc = "0x00 - Control register"]
56 #[inline(always)]
57 pub const fn ctrl(&self) -> &CTRL {
58 &self.ctrl
59 }
60 #[doc = "0x08 - Clock divider configuration register"]
61 #[inline(always)]
62 pub const fn clkdiv(&self) -> &CLKDIV {
63 &self.clkdiv
64 }
65 #[doc = "0x0c - Clock source selection register"]
66 #[inline(always)]
67 pub const fn clksrc(&self) -> &CLKSRC {
68 &self.clksrc
69 }
70 #[doc = "0x10 - Clock enable register"]
71 #[inline(always)]
72 pub const fn clkena(&self) -> &CLKENA {
73 &self.clkena
74 }
75 #[doc = "0x14 - Data and response timeout configuration register"]
76 #[inline(always)]
77 pub const fn tmout(&self) -> &TMOUT {
78 &self.tmout
79 }
80 #[doc = "0x18 - Card bus width configuration register"]
81 #[inline(always)]
82 pub const fn ctype(&self) -> &CTYPE {
83 &self.ctype
84 }
85 #[doc = "0x1c - Card data block size configuration register"]
86 #[inline(always)]
87 pub const fn blksiz(&self) -> &BLKSIZ {
88 &self.blksiz
89 }
90 #[doc = "0x20 - Data transfer length configuration register"]
91 #[inline(always)]
92 pub const fn bytcnt(&self) -> &BYTCNT {
93 &self.bytcnt
94 }
95 #[doc = "0x24 - SDIO interrupt mask register"]
96 #[inline(always)]
97 pub const fn intmask(&self) -> &INTMASK {
98 &self.intmask
99 }
100 #[doc = "0x28 - Command argument data register"]
101 #[inline(always)]
102 pub const fn cmdarg(&self) -> &CMDARG {
103 &self.cmdarg
104 }
105 #[doc = "0x2c - Command and boot configuration register"]
106 #[inline(always)]
107 pub const fn cmd(&self) -> &CMD {
108 &self.cmd
109 }
110 #[doc = "0x30 - Response data register"]
111 #[inline(always)]
112 pub const fn resp0(&self) -> &RESP0 {
113 &self.resp0
114 }
115 #[doc = "0x34 - Long response data register"]
116 #[inline(always)]
117 pub const fn resp1(&self) -> &RESP1 {
118 &self.resp1
119 }
120 #[doc = "0x38 - Long response data register"]
121 #[inline(always)]
122 pub const fn resp2(&self) -> &RESP2 {
123 &self.resp2
124 }
125 #[doc = "0x3c - Long response data register"]
126 #[inline(always)]
127 pub const fn resp3(&self) -> &RESP3 {
128 &self.resp3
129 }
130 #[doc = "0x40 - Masked interrupt status register"]
131 #[inline(always)]
132 pub const fn mintsts(&self) -> &MINTSTS {
133 &self.mintsts
134 }
135 #[doc = "0x44 - Raw interrupt status register"]
136 #[inline(always)]
137 pub const fn rintsts(&self) -> &RINTSTS {
138 &self.rintsts
139 }
140 #[doc = "0x48 - SD/MMC status register"]
141 #[inline(always)]
142 pub const fn status(&self) -> &STATUS {
143 &self.status
144 }
145 #[doc = "0x4c - FIFO configuration register"]
146 #[inline(always)]
147 pub const fn fifoth(&self) -> &FIFOTH {
148 &self.fifoth
149 }
150 #[doc = "0x50 - Card detect register"]
151 #[inline(always)]
152 pub const fn cdetect(&self) -> &CDETECT {
153 &self.cdetect
154 }
155 #[doc = "0x54 - Card write protection (WP) status register"]
156 #[inline(always)]
157 pub const fn wrtprt(&self) -> &WRTPRT {
158 &self.wrtprt
159 }
160 #[doc = "0x5c - Transferred byte count register"]
161 #[inline(always)]
162 pub const fn tcbcnt(&self) -> &TCBCNT {
163 &self.tcbcnt
164 }
165 #[doc = "0x60 - Transferred byte count register"]
166 #[inline(always)]
167 pub const fn tbbcnt(&self) -> &TBBCNT {
168 &self.tbbcnt
169 }
170 #[doc = "0x64 - Debounce filter time configuration register"]
171 #[inline(always)]
172 pub const fn debnce(&self) -> &DEBNCE {
173 &self.debnce
174 }
175 #[doc = "0x68 - User ID (scratchpad) register"]
176 #[inline(always)]
177 pub const fn usrid(&self) -> &USRID {
178 &self.usrid
179 }
180 #[doc = "0x6c - Version ID (scratchpad) register"]
181 #[inline(always)]
182 pub const fn verid(&self) -> &VERID {
183 &self.verid
184 }
185 #[doc = "0x70 - Hardware feature register"]
186 #[inline(always)]
187 pub const fn hcon(&self) -> &HCON {
188 &self.hcon
189 }
190 #[doc = "0x74 - UHS-1 register"]
191 #[inline(always)]
192 pub const fn uhs(&self) -> &UHS {
193 &self.uhs
194 }
195 #[doc = "0x78 - Card reset register"]
196 #[inline(always)]
197 pub const fn rst_n(&self) -> &RST_N {
198 &self.rst_n
199 }
200 #[doc = "0x80 - Burst mode transfer configuration register"]
201 #[inline(always)]
202 pub const fn bmod(&self) -> &BMOD {
203 &self.bmod
204 }
205 #[doc = "0x84 - Poll demand configuration register"]
206 #[inline(always)]
207 pub const fn pldmnd(&self) -> &PLDMND {
208 &self.pldmnd
209 }
210 #[doc = "0x88 - Descriptor base address register"]
211 #[inline(always)]
212 pub const fn dbaddr(&self) -> &DBADDR {
213 &self.dbaddr
214 }
215 #[doc = "0x8c - IDMAC status register"]
216 #[inline(always)]
217 pub const fn idsts(&self) -> &IDSTS {
218 &self.idsts
219 }
220 #[doc = "0x90 - IDMAC interrupt enable register"]
221 #[inline(always)]
222 pub const fn idinten(&self) -> &IDINTEN {
223 &self.idinten
224 }
225 #[doc = "0x94 - Host descriptor address pointer"]
226 #[inline(always)]
227 pub const fn dscaddr(&self) -> &DSCADDR {
228 &self.dscaddr
229 }
230 #[doc = "0x98 - Host buffer address pointer register"]
231 #[inline(always)]
232 pub const fn bufaddr(&self) -> &BUFADDR {
233 &self.bufaddr
234 }
235 #[doc = "0x100 - Card Threshold Control register"]
236 #[inline(always)]
237 pub const fn cardthrctl(&self) -> &CARDTHRCTL {
238 &self.cardthrctl
239 }
240 #[doc = "0x10c - eMMC DDR register"]
241 #[inline(always)]
242 pub const fn emmcddr(&self) -> &EMMCDDR {
243 &self.emmcddr
244 }
245 #[doc = "0x110 - Enable Phase Shift register"]
246 #[inline(always)]
247 pub const fn enshift(&self) -> &ENSHIFT {
248 &self.enshift
249 }
250 #[doc = "0x200 - CPU write and read transmit data by FIFO"]
251 #[inline(always)]
252 pub const fn buffifo(&self) -> &BUFFIFO {
253 &self.buffifo
254 }
255 #[doc = "0x800 - SDIO control register."]
256 #[inline(always)]
257 pub const fn clk_edge_sel(&self) -> &CLK_EDGE_SEL {
258 &self.clk_edge_sel
259 }
260}
261#[doc = "CTRL (rw) register accessor: Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
262pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
263#[doc = "Control register"]
264pub mod ctrl;
265#[doc = "CLKDIV (rw) register accessor: Clock divider configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`] module"]
266pub type CLKDIV = crate::Reg<clkdiv::CLKDIV_SPEC>;
267#[doc = "Clock divider configuration register"]
268pub mod clkdiv;
269#[doc = "CLKSRC (rw) register accessor: Clock source selection register\n\nYou can [`read`](crate::Reg::read) this register and get [`clksrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clksrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksrc`] module"]
270pub type CLKSRC = crate::Reg<clksrc::CLKSRC_SPEC>;
271#[doc = "Clock source selection register"]
272pub mod clksrc;
273#[doc = "CLKENA (rw) register accessor: Clock enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkena`] module"]
274pub type CLKENA = crate::Reg<clkena::CLKENA_SPEC>;
275#[doc = "Clock enable register"]
276pub mod clkena;
277#[doc = "TMOUT (rw) register accessor: Data and response timeout configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmout`] module"]
278pub type TMOUT = crate::Reg<tmout::TMOUT_SPEC>;
279#[doc = "Data and response timeout configuration register"]
280pub mod tmout;
281#[doc = "CTYPE (rw) register accessor: Card bus width configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctype::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctype::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctype`] module"]
282pub type CTYPE = crate::Reg<ctype::CTYPE_SPEC>;
283#[doc = "Card bus width configuration register"]
284pub mod ctype;
285#[doc = "BLKSIZ (rw) register accessor: Card data block size configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`blksiz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blksiz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blksiz`] module"]
286pub type BLKSIZ = crate::Reg<blksiz::BLKSIZ_SPEC>;
287#[doc = "Card data block size configuration register"]
288pub mod blksiz;
289#[doc = "BYTCNT (rw) register accessor: Data transfer length configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`bytcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bytcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bytcnt`] module"]
290pub type BYTCNT = crate::Reg<bytcnt::BYTCNT_SPEC>;
291#[doc = "Data transfer length configuration register"]
292pub mod bytcnt;
293#[doc = "INTMASK (rw) register accessor: SDIO interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`intmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intmask`] module"]
294pub type INTMASK = crate::Reg<intmask::INTMASK_SPEC>;
295#[doc = "SDIO interrupt mask register"]
296pub mod intmask;
297#[doc = "CMDARG (rw) register accessor: Command argument data register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdarg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdarg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdarg`] module"]
298pub type CMDARG = crate::Reg<cmdarg::CMDARG_SPEC>;
299#[doc = "Command argument data register"]
300pub mod cmdarg;
301#[doc = "CMD (rw) register accessor: Command and boot configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"]
302pub type CMD = crate::Reg<cmd::CMD_SPEC>;
303#[doc = "Command and boot configuration register"]
304pub mod cmd;
305#[doc = "RESP0 (r) register accessor: Response data register\n\nYou can [`read`](crate::Reg::read) this register and get [`resp0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp0`] module"]
306pub type RESP0 = crate::Reg<resp0::RESP0_SPEC>;
307#[doc = "Response data register"]
308pub mod resp0;
309#[doc = "RESP1 (r) register accessor: Long response data register\n\nYou can [`read`](crate::Reg::read) this register and get [`resp1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp1`] module"]
310pub type RESP1 = crate::Reg<resp1::RESP1_SPEC>;
311#[doc = "Long response data register"]
312pub mod resp1;
313#[doc = "RESP2 (r) register accessor: Long response data register\n\nYou can [`read`](crate::Reg::read) this register and get [`resp2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp2`] module"]
314pub type RESP2 = crate::Reg<resp2::RESP2_SPEC>;
315#[doc = "Long response data register"]
316pub mod resp2;
317#[doc = "RESP3 (r) register accessor: Long response data register\n\nYou can [`read`](crate::Reg::read) this register and get [`resp3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp3`] module"]
318pub type RESP3 = crate::Reg<resp3::RESP3_SPEC>;
319#[doc = "Long response data register"]
320pub mod resp3;
321#[doc = "MINTSTS (r) register accessor: Masked interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mintsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mintsts`] module"]
322pub type MINTSTS = crate::Reg<mintsts::MINTSTS_SPEC>;
323#[doc = "Masked interrupt status register"]
324pub mod mintsts;
325#[doc = "RINTSTS (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`rintsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rintsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rintsts`] module"]
326pub type RINTSTS = crate::Reg<rintsts::RINTSTS_SPEC>;
327#[doc = "Raw interrupt status register"]
328pub mod rintsts;
329#[doc = "STATUS (r) register accessor: SD/MMC status register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"]
330pub type STATUS = crate::Reg<status::STATUS_SPEC>;
331#[doc = "SD/MMC status register"]
332pub mod status;
333#[doc = "FIFOTH (rw) register accessor: FIFO configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifoth::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifoth::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifoth`] module"]
334pub type FIFOTH = crate::Reg<fifoth::FIFOTH_SPEC>;
335#[doc = "FIFO configuration register"]
336pub mod fifoth;
337#[doc = "CDETECT (r) register accessor: Card detect register\n\nYou can [`read`](crate::Reg::read) this register and get [`cdetect::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cdetect`] module"]
338pub type CDETECT = crate::Reg<cdetect::CDETECT_SPEC>;
339#[doc = "Card detect register"]
340pub mod cdetect;
341#[doc = "WRTPRT (r) register accessor: Card write protection (WP) status register\n\nYou can [`read`](crate::Reg::read) this register and get [`wrtprt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wrtprt`] module"]
342pub type WRTPRT = crate::Reg<wrtprt::WRTPRT_SPEC>;
343#[doc = "Card write protection (WP) status register"]
344pub mod wrtprt;
345#[doc = "TCBCNT (r) register accessor: Transferred byte count register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcbcnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcbcnt`] module"]
346pub type TCBCNT = crate::Reg<tcbcnt::TCBCNT_SPEC>;
347#[doc = "Transferred byte count register"]
348pub mod tcbcnt;
349#[doc = "TBBCNT (r) register accessor: Transferred byte count register\n\nYou can [`read`](crate::Reg::read) this register and get [`tbbcnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tbbcnt`] module"]
350pub type TBBCNT = crate::Reg<tbbcnt::TBBCNT_SPEC>;
351#[doc = "Transferred byte count register"]
352pub mod tbbcnt;
353#[doc = "DEBNCE (rw) register accessor: Debounce filter time configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`debnce::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debnce::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debnce`] module"]
354pub type DEBNCE = crate::Reg<debnce::DEBNCE_SPEC>;
355#[doc = "Debounce filter time configuration register"]
356pub mod debnce;
357#[doc = "USRID (rw) register accessor: User ID (scratchpad) register\n\nYou can [`read`](crate::Reg::read) this register and get [`usrid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usrid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usrid`] module"]
358pub type USRID = crate::Reg<usrid::USRID_SPEC>;
359#[doc = "User ID (scratchpad) register"]
360pub mod usrid;
361#[doc = "VERID (r) register accessor: Version ID (scratchpad) register\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"]
362pub type VERID = crate::Reg<verid::VERID_SPEC>;
363#[doc = "Version ID (scratchpad) register"]
364pub mod verid;
365#[doc = "HCON (r) register accessor: Hardware feature register\n\nYou can [`read`](crate::Reg::read) this register and get [`hcon::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcon`] module"]
366pub type HCON = crate::Reg<hcon::HCON_SPEC>;
367#[doc = "Hardware feature register"]
368pub mod hcon;
369#[doc = "UHS (rw) register accessor: UHS-1 register\n\nYou can [`read`](crate::Reg::read) this register and get [`uhs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uhs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uhs`] module"]
370pub type UHS = crate::Reg<uhs::UHS_SPEC>;
371#[doc = "UHS-1 register"]
372pub mod uhs;
373#[doc = "RST_N (rw) register accessor: Card reset register\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_n::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_n::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_n`] module"]
374pub type RST_N = crate::Reg<rst_n::RST_N_SPEC>;
375#[doc = "Card reset register"]
376pub mod rst_n;
377#[doc = "BMOD (rw) register accessor: Burst mode transfer configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`bmod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bmod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bmod`] module"]
378pub type BMOD = crate::Reg<bmod::BMOD_SPEC>;
379#[doc = "Burst mode transfer configuration register"]
380pub mod bmod;
381#[doc = "PLDMND (w) register accessor: Poll demand configuration register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pldmnd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pldmnd`] module"]
382pub type PLDMND = crate::Reg<pldmnd::PLDMND_SPEC>;
383#[doc = "Poll demand configuration register"]
384pub mod pldmnd;
385#[doc = "DBADDR (rw) register accessor: Descriptor base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`dbaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbaddr`] module"]
386pub type DBADDR = crate::Reg<dbaddr::DBADDR_SPEC>;
387#[doc = "Descriptor base address register"]
388pub mod dbaddr;
389#[doc = "IDSTS (rw) register accessor: IDMAC status register\n\nYou can [`read`](crate::Reg::read) this register and get [`idsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`idsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idsts`] module"]
390pub type IDSTS = crate::Reg<idsts::IDSTS_SPEC>;
391#[doc = "IDMAC status register"]
392pub mod idsts;
393#[doc = "IDINTEN (rw) register accessor: IDMAC interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`idinten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`idinten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idinten`] module"]
394pub type IDINTEN = crate::Reg<idinten::IDINTEN_SPEC>;
395#[doc = "IDMAC interrupt enable register"]
396pub mod idinten;
397#[doc = "DSCADDR (r) register accessor: Host descriptor address pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`dscaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dscaddr`] module"]
398pub type DSCADDR = crate::Reg<dscaddr::DSCADDR_SPEC>;
399#[doc = "Host descriptor address pointer"]
400pub mod dscaddr;
401#[doc = "BUFADDR (r) register accessor: Host buffer address pointer register\n\nYou can [`read`](crate::Reg::read) this register and get [`bufaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bufaddr`] module"]
402pub type BUFADDR = crate::Reg<bufaddr::BUFADDR_SPEC>;
403#[doc = "Host buffer address pointer register"]
404pub mod bufaddr;
405#[doc = "CARDTHRCTL (rw) register accessor: Card Threshold Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cardthrctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cardthrctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cardthrctl`] module"]
406pub type CARDTHRCTL = crate::Reg<cardthrctl::CARDTHRCTL_SPEC>;
407#[doc = "Card Threshold Control register"]
408pub mod cardthrctl;
409#[doc = "EMMCDDR (rw) register accessor: eMMC DDR register\n\nYou can [`read`](crate::Reg::read) this register and get [`emmcddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emmcddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emmcddr`] module"]
410pub type EMMCDDR = crate::Reg<emmcddr::EMMCDDR_SPEC>;
411#[doc = "eMMC DDR register"]
412pub mod emmcddr;
413#[doc = "ENSHIFT (rw) register accessor: Enable Phase Shift register\n\nYou can [`read`](crate::Reg::read) this register and get [`enshift::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enshift::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enshift`] module"]
414pub type ENSHIFT = crate::Reg<enshift::ENSHIFT_SPEC>;
415#[doc = "Enable Phase Shift register"]
416pub mod enshift;
417#[doc = "BUFFIFO (rw) register accessor: CPU write and read transmit data by FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`buffifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`buffifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@buffifo`] module"]
418pub type BUFFIFO = crate::Reg<buffifo::BUFFIFO_SPEC>;
419#[doc = "CPU write and read transmit data by FIFO"]
420pub mod buffifo;
421#[doc = "CLK_EDGE_SEL (rw) register accessor: SDIO control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_edge_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_edge_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_edge_sel`] module"]
422pub type CLK_EDGE_SEL = crate::Reg<clk_edge_sel::CLK_EDGE_SEL_SPEC>;
423#[doc = "SDIO control register."]
424pub mod clk_edge_sel;