esp32s3/spi0/
cache_sctrl.rs1#[doc = "Register `CACHE_SCTRL` reader"]
2pub type R = crate::R<CACHE_SCTRL_SPEC>;
3#[doc = "Register `CACHE_SCTRL` writer"]
4pub type W = crate::W<CACHE_SCTRL_SPEC>;
5#[doc = "Field `CACHE_USR_SCMD_4BYTE` reader - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31."]
6pub type CACHE_USR_SCMD_4BYTE_R = crate::BitReader;
7#[doc = "Field `CACHE_USR_SCMD_4BYTE` writer - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31."]
8pub type CACHE_USR_SCMD_4BYTE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `USR_SRAM_DIO` reader - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer."]
10pub type USR_SRAM_DIO_R = crate::BitReader;
11#[doc = "Field `USR_SRAM_DIO` writer - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer."]
12pub type USR_SRAM_DIO_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `USR_SRAM_QIO` reader - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer."]
14pub type USR_SRAM_QIO_R = crate::BitReader;
15#[doc = "Field `USR_SRAM_QIO` writer - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer."]
16pub type USR_SRAM_QIO_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `USR_WR_SRAM_DUMMY` reader - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations."]
18pub type USR_WR_SRAM_DUMMY_R = crate::BitReader;
19#[doc = "Field `USR_WR_SRAM_DUMMY` writer - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations."]
20pub type USR_WR_SRAM_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `USR_RD_SRAM_DUMMY` reader - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations."]
22pub type USR_RD_SRAM_DUMMY_R = crate::BitReader;
23#[doc = "Field `USR_RD_SRAM_DUMMY` writer - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations."]
24pub type USR_RD_SRAM_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CACHE_SRAM_USR_RCMD` reader - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2."]
26pub type CACHE_SRAM_USR_RCMD_R = crate::BitReader;
27#[doc = "Field `CACHE_SRAM_USR_RCMD` writer - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2."]
28pub type CACHE_SRAM_USR_RCMD_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SRAM_RDUMMY_CYCLELEN` reader - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer."]
30pub type SRAM_RDUMMY_CYCLELEN_R = crate::FieldReader;
31#[doc = "Field `SRAM_RDUMMY_CYCLELEN` writer - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer."]
32pub type SRAM_RDUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
33#[doc = "Field `SRAM_ADDR_BITLEN` reader - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1)."]
34pub type SRAM_ADDR_BITLEN_R = crate::FieldReader;
35#[doc = "Field `SRAM_ADDR_BITLEN` writer - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1)."]
36pub type SRAM_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
37#[doc = "Field `CACHE_SRAM_USR_WCMD` reader - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3."]
38pub type CACHE_SRAM_USR_WCMD_R = crate::BitReader;
39#[doc = "Field `CACHE_SRAM_USR_WCMD` writer - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3."]
40pub type CACHE_SRAM_USR_WCMD_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SRAM_OCT` reader - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer."]
42pub type SRAM_OCT_R = crate::BitReader;
43#[doc = "Field `SRAM_OCT` writer - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer."]
44pub type SRAM_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SRAM_WDUMMY_CYCLELEN` reader - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer."]
46pub type SRAM_WDUMMY_CYCLELEN_R = crate::FieldReader;
47#[doc = "Field `SRAM_WDUMMY_CYCLELEN` writer - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer."]
48pub type SRAM_WDUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
49impl R {
50 #[doc = "Bit 0 - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31."]
51 #[inline(always)]
52 pub fn cache_usr_scmd_4byte(&self) -> CACHE_USR_SCMD_4BYTE_R {
53 CACHE_USR_SCMD_4BYTE_R::new((self.bits & 1) != 0)
54 }
55 #[doc = "Bit 1 - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer."]
56 #[inline(always)]
57 pub fn usr_sram_dio(&self) -> USR_SRAM_DIO_R {
58 USR_SRAM_DIO_R::new(((self.bits >> 1) & 1) != 0)
59 }
60 #[doc = "Bit 2 - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer."]
61 #[inline(always)]
62 pub fn usr_sram_qio(&self) -> USR_SRAM_QIO_R {
63 USR_SRAM_QIO_R::new(((self.bits >> 2) & 1) != 0)
64 }
65 #[doc = "Bit 3 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations."]
66 #[inline(always)]
67 pub fn usr_wr_sram_dummy(&self) -> USR_WR_SRAM_DUMMY_R {
68 USR_WR_SRAM_DUMMY_R::new(((self.bits >> 3) & 1) != 0)
69 }
70 #[doc = "Bit 4 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations."]
71 #[inline(always)]
72 pub fn usr_rd_sram_dummy(&self) -> USR_RD_SRAM_DUMMY_R {
73 USR_RD_SRAM_DUMMY_R::new(((self.bits >> 4) & 1) != 0)
74 }
75 #[doc = "Bit 5 - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2."]
76 #[inline(always)]
77 pub fn cache_sram_usr_rcmd(&self) -> CACHE_SRAM_USR_RCMD_R {
78 CACHE_SRAM_USR_RCMD_R::new(((self.bits >> 5) & 1) != 0)
79 }
80 #[doc = "Bits 6:11 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer."]
81 #[inline(always)]
82 pub fn sram_rdummy_cyclelen(&self) -> SRAM_RDUMMY_CYCLELEN_R {
83 SRAM_RDUMMY_CYCLELEN_R::new(((self.bits >> 6) & 0x3f) as u8)
84 }
85 #[doc = "Bits 14:19 - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1)."]
86 #[inline(always)]
87 pub fn sram_addr_bitlen(&self) -> SRAM_ADDR_BITLEN_R {
88 SRAM_ADDR_BITLEN_R::new(((self.bits >> 14) & 0x3f) as u8)
89 }
90 #[doc = "Bit 20 - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3."]
91 #[inline(always)]
92 pub fn cache_sram_usr_wcmd(&self) -> CACHE_SRAM_USR_WCMD_R {
93 CACHE_SRAM_USR_WCMD_R::new(((self.bits >> 20) & 1) != 0)
94 }
95 #[doc = "Bit 21 - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer."]
96 #[inline(always)]
97 pub fn sram_oct(&self) -> SRAM_OCT_R {
98 SRAM_OCT_R::new(((self.bits >> 21) & 1) != 0)
99 }
100 #[doc = "Bits 22:27 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer."]
101 #[inline(always)]
102 pub fn sram_wdummy_cyclelen(&self) -> SRAM_WDUMMY_CYCLELEN_R {
103 SRAM_WDUMMY_CYCLELEN_R::new(((self.bits >> 22) & 0x3f) as u8)
104 }
105}
106#[cfg(feature = "impl-register-debug")]
107impl core::fmt::Debug for R {
108 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109 f.debug_struct("CACHE_SCTRL")
110 .field("cache_usr_scmd_4byte", &self.cache_usr_scmd_4byte())
111 .field("usr_sram_dio", &self.usr_sram_dio())
112 .field("usr_sram_qio", &self.usr_sram_qio())
113 .field("usr_wr_sram_dummy", &self.usr_wr_sram_dummy())
114 .field("usr_rd_sram_dummy", &self.usr_rd_sram_dummy())
115 .field("cache_sram_usr_rcmd", &self.cache_sram_usr_rcmd())
116 .field("sram_rdummy_cyclelen", &self.sram_rdummy_cyclelen())
117 .field("sram_addr_bitlen", &self.sram_addr_bitlen())
118 .field("cache_sram_usr_wcmd", &self.cache_sram_usr_wcmd())
119 .field("sram_oct", &self.sram_oct())
120 .field("sram_wdummy_cyclelen", &self.sram_wdummy_cyclelen())
121 .finish()
122 }
123}
124impl W {
125 #[doc = "Bit 0 - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31."]
126 #[inline(always)]
127 pub fn cache_usr_scmd_4byte(&mut self) -> CACHE_USR_SCMD_4BYTE_W<CACHE_SCTRL_SPEC> {
128 CACHE_USR_SCMD_4BYTE_W::new(self, 0)
129 }
130 #[doc = "Bit 1 - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer."]
131 #[inline(always)]
132 pub fn usr_sram_dio(&mut self) -> USR_SRAM_DIO_W<CACHE_SCTRL_SPEC> {
133 USR_SRAM_DIO_W::new(self, 1)
134 }
135 #[doc = "Bit 2 - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer."]
136 #[inline(always)]
137 pub fn usr_sram_qio(&mut self) -> USR_SRAM_QIO_W<CACHE_SCTRL_SPEC> {
138 USR_SRAM_QIO_W::new(self, 2)
139 }
140 #[doc = "Bit 3 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations."]
141 #[inline(always)]
142 pub fn usr_wr_sram_dummy(&mut self) -> USR_WR_SRAM_DUMMY_W<CACHE_SCTRL_SPEC> {
143 USR_WR_SRAM_DUMMY_W::new(self, 3)
144 }
145 #[doc = "Bit 4 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations."]
146 #[inline(always)]
147 pub fn usr_rd_sram_dummy(&mut self) -> USR_RD_SRAM_DUMMY_W<CACHE_SCTRL_SPEC> {
148 USR_RD_SRAM_DUMMY_W::new(self, 4)
149 }
150 #[doc = "Bit 5 - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2."]
151 #[inline(always)]
152 pub fn cache_sram_usr_rcmd(&mut self) -> CACHE_SRAM_USR_RCMD_W<CACHE_SCTRL_SPEC> {
153 CACHE_SRAM_USR_RCMD_W::new(self, 5)
154 }
155 #[doc = "Bits 6:11 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer."]
156 #[inline(always)]
157 pub fn sram_rdummy_cyclelen(&mut self) -> SRAM_RDUMMY_CYCLELEN_W<CACHE_SCTRL_SPEC> {
158 SRAM_RDUMMY_CYCLELEN_W::new(self, 6)
159 }
160 #[doc = "Bits 14:19 - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1)."]
161 #[inline(always)]
162 pub fn sram_addr_bitlen(&mut self) -> SRAM_ADDR_BITLEN_W<CACHE_SCTRL_SPEC> {
163 SRAM_ADDR_BITLEN_W::new(self, 14)
164 }
165 #[doc = "Bit 20 - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3."]
166 #[inline(always)]
167 pub fn cache_sram_usr_wcmd(&mut self) -> CACHE_SRAM_USR_WCMD_W<CACHE_SCTRL_SPEC> {
168 CACHE_SRAM_USR_WCMD_W::new(self, 20)
169 }
170 #[doc = "Bit 21 - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer."]
171 #[inline(always)]
172 pub fn sram_oct(&mut self) -> SRAM_OCT_W<CACHE_SCTRL_SPEC> {
173 SRAM_OCT_W::new(self, 21)
174 }
175 #[doc = "Bits 22:27 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer."]
176 #[inline(always)]
177 pub fn sram_wdummy_cyclelen(&mut self) -> SRAM_WDUMMY_CYCLELEN_W<CACHE_SCTRL_SPEC> {
178 SRAM_WDUMMY_CYCLELEN_W::new(self, 22)
179 }
180}
181#[doc = "SPI0 external RAM control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_sctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_sctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
182pub struct CACHE_SCTRL_SPEC;
183impl crate::RegisterSpec for CACHE_SCTRL_SPEC {
184 type Ux = u32;
185}
186#[doc = "`read()` method returns [`cache_sctrl::R`](R) reader structure"]
187impl crate::Readable for CACHE_SCTRL_SPEC {}
188#[doc = "`write(|w| ..)` method takes [`cache_sctrl::W`](W) writer structure"]
189impl crate::Writable for CACHE_SCTRL_SPEC {
190 type Safety = crate::Unsafe;
191 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
192 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
193}
194#[doc = "`reset()` method sets CACHE_SCTRL to value 0x0055_c070"]
195impl crate::Resettable for CACHE_SCTRL_SPEC {
196 const RESET_VALUE: u32 = 0x0055_c070;
197}