esp32s3/extmem/
cache_preload_int_ctrl.rs

1#[doc = "Register `CACHE_PRELOAD_INT_CTRL` reader"]
2pub type R = crate::R<CACHE_PRELOAD_INT_CTRL_SPEC>;
3#[doc = "Register `CACHE_PRELOAD_INT_CTRL` writer"]
4pub type W = crate::W<CACHE_PRELOAD_INT_CTRL_SPEC>;
5#[doc = "Field `ST` reader - The bit is used to indicate the interrupt by icache pre-load done."]
6pub type ST_R = crate::BitReader;
7#[doc = "Field `ENA` reader - The bit is used to enable the interrupt by icache pre-load done."]
8pub type ENA_R = crate::BitReader;
9#[doc = "Field `ENA` writer - The bit is used to enable the interrupt by icache pre-load done."]
10pub type ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `CLR` writer - The bit is used to clear the interrupt by icache pre-load done."]
12pub type CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `DCACHE_PRELOAD_INT_ST` reader - The bit is used to indicate the interrupt by dcache pre-load done."]
14pub type DCACHE_PRELOAD_INT_ST_R = crate::BitReader;
15#[doc = "Field `DCACHE_PRELOAD_INT_ENA` reader - The bit is used to enable the interrupt by dcache pre-load done."]
16pub type DCACHE_PRELOAD_INT_ENA_R = crate::BitReader;
17#[doc = "Field `DCACHE_PRELOAD_INT_ENA` writer - The bit is used to enable the interrupt by dcache pre-load done."]
18pub type DCACHE_PRELOAD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `DCACHE_PRELOAD_INT_CLR` writer - The bit is used to clear the interrupt by dcache pre-load done."]
20pub type DCACHE_PRELOAD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - The bit is used to indicate the interrupt by icache pre-load done."]
23    #[inline(always)]
24    pub fn st(&self) -> ST_R {
25        ST_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - The bit is used to enable the interrupt by icache pre-load done."]
28    #[inline(always)]
29    pub fn ena(&self) -> ENA_R {
30        ENA_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 3 - The bit is used to indicate the interrupt by dcache pre-load done."]
33    #[inline(always)]
34    pub fn dcache_preload_int_st(&self) -> DCACHE_PRELOAD_INT_ST_R {
35        DCACHE_PRELOAD_INT_ST_R::new(((self.bits >> 3) & 1) != 0)
36    }
37    #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache pre-load done."]
38    #[inline(always)]
39    pub fn dcache_preload_int_ena(&self) -> DCACHE_PRELOAD_INT_ENA_R {
40        DCACHE_PRELOAD_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CACHE_PRELOAD_INT_CTRL")
47            .field("st", &self.st())
48            .field("ena", &self.ena())
49            .field("dcache_preload_int_st", &self.dcache_preload_int_st())
50            .field("dcache_preload_int_ena", &self.dcache_preload_int_ena())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bit 1 - The bit is used to enable the interrupt by icache pre-load done."]
56    #[inline(always)]
57    pub fn ena(&mut self) -> ENA_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
58        ENA_W::new(self, 1)
59    }
60    #[doc = "Bit 2 - The bit is used to clear the interrupt by icache pre-load done."]
61    #[inline(always)]
62    pub fn clr(&mut self) -> CLR_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
63        CLR_W::new(self, 2)
64    }
65    #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache pre-load done."]
66    #[inline(always)]
67    pub fn dcache_preload_int_ena(
68        &mut self,
69    ) -> DCACHE_PRELOAD_INT_ENA_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
70        DCACHE_PRELOAD_INT_ENA_W::new(self, 4)
71    }
72    #[doc = "Bit 5 - The bit is used to clear the interrupt by dcache pre-load done."]
73    #[inline(always)]
74    pub fn dcache_preload_int_clr(
75        &mut self,
76    ) -> DCACHE_PRELOAD_INT_CLR_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
77        DCACHE_PRELOAD_INT_CLR_W::new(self, 5)
78    }
79}
80#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_preload_int_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_preload_int_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
81pub struct CACHE_PRELOAD_INT_CTRL_SPEC;
82impl crate::RegisterSpec for CACHE_PRELOAD_INT_CTRL_SPEC {
83    type Ux = u32;
84}
85#[doc = "`read()` method returns [`cache_preload_int_ctrl::R`](R) reader structure"]
86impl crate::Readable for CACHE_PRELOAD_INT_CTRL_SPEC {}
87#[doc = "`write(|w| ..)` method takes [`cache_preload_int_ctrl::W`](W) writer structure"]
88impl crate::Writable for CACHE_PRELOAD_INT_CTRL_SPEC {
89    type Safety = crate::Unsafe;
90    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
91    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x04;
92}
93#[doc = "`reset()` method sets CACHE_PRELOAD_INT_CTRL to value 0"]
94impl crate::Resettable for CACHE_PRELOAD_INT_CTRL_SPEC {
95    const RESET_VALUE: u32 = 0;
96}
esp32s3/extmem/cache_preload_int_ctrl.rs

esp32s3/extmem/
cache_preload_int_ctrl.rs
