1#[doc = "Register `DDR` reader"]
2pub type R = crate::R<DDR_SPEC>;
3#[doc = "Register `DDR` writer"]
4pub type W = crate::W<DDR_SPEC>;
5#[doc = "Field `SPI_FMEM_DDR_EN` reader - 1: in DDR mode, 0: in SDR mode."]
6pub type SPI_FMEM_DDR_EN_R = crate::BitReader;
7#[doc = "Field `SPI_FMEM_DDR_EN` writer - 1: in DDR mode, 0: in SDR mode."]
8pub type SPI_FMEM_DDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SPI_FMEM_VAR_DUMMY` reader - Set the bit to enable variable dummy cycle in DDRmode."]
10pub type SPI_FMEM_VAR_DUMMY_R = crate::BitReader;
11#[doc = "Field `SPI_FMEM_VAR_DUMMY` writer - Set the bit to enable variable dummy cycle in DDRmode."]
12pub type SPI_FMEM_VAR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SPI_FMEM_DDR_RDAT_SWP` reader - Set the bit to reorder RX data of the word in DDR mode."]
14pub type SPI_FMEM_DDR_RDAT_SWP_R = crate::BitReader;
15#[doc = "Field `SPI_FMEM_DDR_RDAT_SWP` writer - Set the bit to reorder RX data of the word in DDR mode."]
16pub type SPI_FMEM_DDR_RDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SPI_FMEM_DDR_WDAT_SWP` reader - Set the bit to reorder TX data of the word in DDR mode."]
18pub type SPI_FMEM_DDR_WDAT_SWP_R = crate::BitReader;
19#[doc = "Field `SPI_FMEM_DDR_WDAT_SWP` writer - Set the bit to reorder TX data of the word in DDR mode."]
20pub type SPI_FMEM_DDR_WDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SPI_FMEM_DDR_CMD_DIS` reader - the bit is used to disable dual edge in command phase when DDR mode."]
22pub type SPI_FMEM_DDR_CMD_DIS_R = crate::BitReader;
23#[doc = "Field `SPI_FMEM_DDR_CMD_DIS` writer - the bit is used to disable dual edge in command phase when DDR mode."]
24pub type SPI_FMEM_DDR_CMD_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SPI_FMEM_OUTMINBYTELEN` reader - It is the minimum output data length in the panda device."]
26pub type SPI_FMEM_OUTMINBYTELEN_R = crate::FieldReader;
27#[doc = "Field `SPI_FMEM_OUTMINBYTELEN` writer - It is the minimum output data length in the panda device."]
28pub type SPI_FMEM_OUTMINBYTELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
29#[doc = "Field `SPI_FMEM_USR_DDR_DQS_THD` reader - The delay number of data strobe which from memory based on SPI_CLK."]
30pub type SPI_FMEM_USR_DDR_DQS_THD_R = crate::FieldReader;
31#[doc = "Field `SPI_FMEM_USR_DDR_DQS_THD` writer - The delay number of data strobe which from memory based on SPI_CLK."]
32pub type SPI_FMEM_USR_DDR_DQS_THD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
33#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP` reader - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
34pub type SPI_FMEM_DDR_DQS_LOOP_R = crate::BitReader;
35#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP` writer - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
36pub type SPI_FMEM_DDR_DQS_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP_MODE` reader - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
38pub type SPI_FMEM_DDR_DQS_LOOP_MODE_R = crate::BitReader;
39#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP_MODE` writer - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
40pub type SPI_FMEM_DDR_DQS_LOOP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SPI_FMEM_CLK_DIFF_EN` reader - Set this bit to enable the differential SPI_CLK#."]
42pub type SPI_FMEM_CLK_DIFF_EN_R = crate::BitReader;
43#[doc = "Field `SPI_FMEM_CLK_DIFF_EN` writer - Set this bit to enable the differential SPI_CLK#."]
44pub type SPI_FMEM_CLK_DIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SPI_FMEM_HYPERBUS_MODE` reader - Set this bit to enable the SPI HyperBus mode."]
46pub type SPI_FMEM_HYPERBUS_MODE_R = crate::BitReader;
47#[doc = "Field `SPI_FMEM_HYPERBUS_MODE` writer - Set this bit to enable the SPI HyperBus mode."]
48pub type SPI_FMEM_HYPERBUS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SPI_FMEM_DQS_CA_IN` reader - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
50pub type SPI_FMEM_DQS_CA_IN_R = crate::BitReader;
51#[doc = "Field `SPI_FMEM_DQS_CA_IN` writer - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
52pub type SPI_FMEM_DQS_CA_IN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `SPI_FMEM_HYPERBUS_DUMMY_2X` reader - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."]
54pub type SPI_FMEM_HYPERBUS_DUMMY_2X_R = crate::BitReader;
55#[doc = "Field `SPI_FMEM_HYPERBUS_DUMMY_2X` writer - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."]
56pub type SPI_FMEM_HYPERBUS_DUMMY_2X_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `SPI_FMEM_CLK_DIFF_INV` reader - Set this bit to invert SPI_DIFF when accesses to flash. ."]
58pub type SPI_FMEM_CLK_DIFF_INV_R = crate::BitReader;
59#[doc = "Field `SPI_FMEM_CLK_DIFF_INV` writer - Set this bit to invert SPI_DIFF when accesses to flash. ."]
60pub type SPI_FMEM_CLK_DIFF_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `SPI_FMEM_OCTA_RAM_ADDR` reader - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
62pub type SPI_FMEM_OCTA_RAM_ADDR_R = crate::BitReader;
63#[doc = "Field `SPI_FMEM_OCTA_RAM_ADDR` writer - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
64pub type SPI_FMEM_OCTA_RAM_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `SPI_FMEM_HYPERBUS_CA` reader - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
66pub type SPI_FMEM_HYPERBUS_CA_R = crate::BitReader;
67#[doc = "Field `SPI_FMEM_HYPERBUS_CA` writer - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
68pub type SPI_FMEM_HYPERBUS_CA_W<'a, REG> = crate::BitWriter<'a, REG>;
69impl R {
70 #[doc = "Bit 0 - 1: in DDR mode, 0: in SDR mode."]
71 #[inline(always)]
72 pub fn spi_fmem_ddr_en(&self) -> SPI_FMEM_DDR_EN_R {
73 SPI_FMEM_DDR_EN_R::new((self.bits & 1) != 0)
74 }
75 #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in DDRmode."]
76 #[inline(always)]
77 pub fn spi_fmem_var_dummy(&self) -> SPI_FMEM_VAR_DUMMY_R {
78 SPI_FMEM_VAR_DUMMY_R::new(((self.bits >> 1) & 1) != 0)
79 }
80 #[doc = "Bit 2 - Set the bit to reorder RX data of the word in DDR mode."]
81 #[inline(always)]
82 pub fn spi_fmem_ddr_rdat_swp(&self) -> SPI_FMEM_DDR_RDAT_SWP_R {
83 SPI_FMEM_DDR_RDAT_SWP_R::new(((self.bits >> 2) & 1) != 0)
84 }
85 #[doc = "Bit 3 - Set the bit to reorder TX data of the word in DDR mode."]
86 #[inline(always)]
87 pub fn spi_fmem_ddr_wdat_swp(&self) -> SPI_FMEM_DDR_WDAT_SWP_R {
88 SPI_FMEM_DDR_WDAT_SWP_R::new(((self.bits >> 3) & 1) != 0)
89 }
90 #[doc = "Bit 4 - the bit is used to disable dual edge in command phase when DDR mode."]
91 #[inline(always)]
92 pub fn spi_fmem_ddr_cmd_dis(&self) -> SPI_FMEM_DDR_CMD_DIS_R {
93 SPI_FMEM_DDR_CMD_DIS_R::new(((self.bits >> 4) & 1) != 0)
94 }
95 #[doc = "Bits 5:11 - It is the minimum output data length in the panda device."]
96 #[inline(always)]
97 pub fn spi_fmem_outminbytelen(&self) -> SPI_FMEM_OUTMINBYTELEN_R {
98 SPI_FMEM_OUTMINBYTELEN_R::new(((self.bits >> 5) & 0x7f) as u8)
99 }
100 #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI_CLK."]
101 #[inline(always)]
102 pub fn spi_fmem_usr_ddr_dqs_thd(&self) -> SPI_FMEM_USR_DDR_DQS_THD_R {
103 SPI_FMEM_USR_DDR_DQS_THD_R::new(((self.bits >> 14) & 0x7f) as u8)
104 }
105 #[doc = "Bit 21 - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
106 #[inline(always)]
107 pub fn spi_fmem_ddr_dqs_loop(&self) -> SPI_FMEM_DDR_DQS_LOOP_R {
108 SPI_FMEM_DDR_DQS_LOOP_R::new(((self.bits >> 21) & 1) != 0)
109 }
110 #[doc = "Bit 22 - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
111 #[inline(always)]
112 pub fn spi_fmem_ddr_dqs_loop_mode(&self) -> SPI_FMEM_DDR_DQS_LOOP_MODE_R {
113 SPI_FMEM_DDR_DQS_LOOP_MODE_R::new(((self.bits >> 22) & 1) != 0)
114 }
115 #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."]
116 #[inline(always)]
117 pub fn spi_fmem_clk_diff_en(&self) -> SPI_FMEM_CLK_DIFF_EN_R {
118 SPI_FMEM_CLK_DIFF_EN_R::new(((self.bits >> 24) & 1) != 0)
119 }
120 #[doc = "Bit 25 - Set this bit to enable the SPI HyperBus mode."]
121 #[inline(always)]
122 pub fn spi_fmem_hyperbus_mode(&self) -> SPI_FMEM_HYPERBUS_MODE_R {
123 SPI_FMEM_HYPERBUS_MODE_R::new(((self.bits >> 25) & 1) != 0)
124 }
125 #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
126 #[inline(always)]
127 pub fn spi_fmem_dqs_ca_in(&self) -> SPI_FMEM_DQS_CA_IN_R {
128 SPI_FMEM_DQS_CA_IN_R::new(((self.bits >> 26) & 1) != 0)
129 }
130 #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."]
131 #[inline(always)]
132 pub fn spi_fmem_hyperbus_dummy_2x(&self) -> SPI_FMEM_HYPERBUS_DUMMY_2X_R {
133 SPI_FMEM_HYPERBUS_DUMMY_2X_R::new(((self.bits >> 27) & 1) != 0)
134 }
135 #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. ."]
136 #[inline(always)]
137 pub fn spi_fmem_clk_diff_inv(&self) -> SPI_FMEM_CLK_DIFF_INV_R {
138 SPI_FMEM_CLK_DIFF_INV_R::new(((self.bits >> 28) & 1) != 0)
139 }
140 #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
141 #[inline(always)]
142 pub fn spi_fmem_octa_ram_addr(&self) -> SPI_FMEM_OCTA_RAM_ADDR_R {
143 SPI_FMEM_OCTA_RAM_ADDR_R::new(((self.bits >> 29) & 1) != 0)
144 }
145 #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
146 #[inline(always)]
147 pub fn spi_fmem_hyperbus_ca(&self) -> SPI_FMEM_HYPERBUS_CA_R {
148 SPI_FMEM_HYPERBUS_CA_R::new(((self.bits >> 30) & 1) != 0)
149 }
150}
151#[cfg(feature = "impl-register-debug")]
152impl core::fmt::Debug for R {
153 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
154 f.debug_struct("DDR")
155 .field("spi_fmem_ddr_en", &self.spi_fmem_ddr_en())
156 .field("spi_fmem_var_dummy", &self.spi_fmem_var_dummy())
157 .field("spi_fmem_ddr_rdat_swp", &self.spi_fmem_ddr_rdat_swp())
158 .field("spi_fmem_ddr_wdat_swp", &self.spi_fmem_ddr_wdat_swp())
159 .field("spi_fmem_ddr_cmd_dis", &self.spi_fmem_ddr_cmd_dis())
160 .field("spi_fmem_outminbytelen", &self.spi_fmem_outminbytelen())
161 .field("spi_fmem_usr_ddr_dqs_thd", &self.spi_fmem_usr_ddr_dqs_thd())
162 .field("spi_fmem_ddr_dqs_loop", &self.spi_fmem_ddr_dqs_loop())
163 .field(
164 "spi_fmem_ddr_dqs_loop_mode",
165 &self.spi_fmem_ddr_dqs_loop_mode(),
166 )
167 .field("spi_fmem_clk_diff_en", &self.spi_fmem_clk_diff_en())
168 .field("spi_fmem_hyperbus_mode", &self.spi_fmem_hyperbus_mode())
169 .field("spi_fmem_dqs_ca_in", &self.spi_fmem_dqs_ca_in())
170 .field(
171 "spi_fmem_hyperbus_dummy_2x",
172 &self.spi_fmem_hyperbus_dummy_2x(),
173 )
174 .field("spi_fmem_clk_diff_inv", &self.spi_fmem_clk_diff_inv())
175 .field("spi_fmem_octa_ram_addr", &self.spi_fmem_octa_ram_addr())
176 .field("spi_fmem_hyperbus_ca", &self.spi_fmem_hyperbus_ca())
177 .finish()
178 }
179}
180impl W {
181 #[doc = "Bit 0 - 1: in DDR mode, 0: in SDR mode."]
182 #[inline(always)]
183 pub fn spi_fmem_ddr_en(&mut self) -> SPI_FMEM_DDR_EN_W<DDR_SPEC> {
184 SPI_FMEM_DDR_EN_W::new(self, 0)
185 }
186 #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in DDRmode."]
187 #[inline(always)]
188 pub fn spi_fmem_var_dummy(&mut self) -> SPI_FMEM_VAR_DUMMY_W<DDR_SPEC> {
189 SPI_FMEM_VAR_DUMMY_W::new(self, 1)
190 }
191 #[doc = "Bit 2 - Set the bit to reorder RX data of the word in DDR mode."]
192 #[inline(always)]
193 pub fn spi_fmem_ddr_rdat_swp(&mut self) -> SPI_FMEM_DDR_RDAT_SWP_W<DDR_SPEC> {
194 SPI_FMEM_DDR_RDAT_SWP_W::new(self, 2)
195 }
196 #[doc = "Bit 3 - Set the bit to reorder TX data of the word in DDR mode."]
197 #[inline(always)]
198 pub fn spi_fmem_ddr_wdat_swp(&mut self) -> SPI_FMEM_DDR_WDAT_SWP_W<DDR_SPEC> {
199 SPI_FMEM_DDR_WDAT_SWP_W::new(self, 3)
200 }
201 #[doc = "Bit 4 - the bit is used to disable dual edge in command phase when DDR mode."]
202 #[inline(always)]
203 pub fn spi_fmem_ddr_cmd_dis(&mut self) -> SPI_FMEM_DDR_CMD_DIS_W<DDR_SPEC> {
204 SPI_FMEM_DDR_CMD_DIS_W::new(self, 4)
205 }
206 #[doc = "Bits 5:11 - It is the minimum output data length in the panda device."]
207 #[inline(always)]
208 pub fn spi_fmem_outminbytelen(&mut self) -> SPI_FMEM_OUTMINBYTELEN_W<DDR_SPEC> {
209 SPI_FMEM_OUTMINBYTELEN_W::new(self, 5)
210 }
211 #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI_CLK."]
212 #[inline(always)]
213 pub fn spi_fmem_usr_ddr_dqs_thd(&mut self) -> SPI_FMEM_USR_DDR_DQS_THD_W<DDR_SPEC> {
214 SPI_FMEM_USR_DDR_DQS_THD_W::new(self, 14)
215 }
216 #[doc = "Bit 21 - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
217 #[inline(always)]
218 pub fn spi_fmem_ddr_dqs_loop(&mut self) -> SPI_FMEM_DDR_DQS_LOOP_W<DDR_SPEC> {
219 SPI_FMEM_DDR_DQS_LOOP_W::new(self, 21)
220 }
221 #[doc = "Bit 22 - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
222 #[inline(always)]
223 pub fn spi_fmem_ddr_dqs_loop_mode(&mut self) -> SPI_FMEM_DDR_DQS_LOOP_MODE_W<DDR_SPEC> {
224 SPI_FMEM_DDR_DQS_LOOP_MODE_W::new(self, 22)
225 }
226 #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."]
227 #[inline(always)]
228 pub fn spi_fmem_clk_diff_en(&mut self) -> SPI_FMEM_CLK_DIFF_EN_W<DDR_SPEC> {
229 SPI_FMEM_CLK_DIFF_EN_W::new(self, 24)
230 }
231 #[doc = "Bit 25 - Set this bit to enable the SPI HyperBus mode."]
232 #[inline(always)]
233 pub fn spi_fmem_hyperbus_mode(&mut self) -> SPI_FMEM_HYPERBUS_MODE_W<DDR_SPEC> {
234 SPI_FMEM_HYPERBUS_MODE_W::new(self, 25)
235 }
236 #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
237 #[inline(always)]
238 pub fn spi_fmem_dqs_ca_in(&mut self) -> SPI_FMEM_DQS_CA_IN_W<DDR_SPEC> {
239 SPI_FMEM_DQS_CA_IN_W::new(self, 26)
240 }
241 #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."]
242 #[inline(always)]
243 pub fn spi_fmem_hyperbus_dummy_2x(&mut self) -> SPI_FMEM_HYPERBUS_DUMMY_2X_W<DDR_SPEC> {
244 SPI_FMEM_HYPERBUS_DUMMY_2X_W::new(self, 27)
245 }
246 #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. ."]
247 #[inline(always)]
248 pub fn spi_fmem_clk_diff_inv(&mut self) -> SPI_FMEM_CLK_DIFF_INV_W<DDR_SPEC> {
249 SPI_FMEM_CLK_DIFF_INV_W::new(self, 28)
250 }
251 #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
252 #[inline(always)]
253 pub fn spi_fmem_octa_ram_addr(&mut self) -> SPI_FMEM_OCTA_RAM_ADDR_W<DDR_SPEC> {
254 SPI_FMEM_OCTA_RAM_ADDR_W::new(self, 29)
255 }
256 #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
257 #[inline(always)]
258 pub fn spi_fmem_hyperbus_ca(&mut self) -> SPI_FMEM_HYPERBUS_CA_W<DDR_SPEC> {
259 SPI_FMEM_HYPERBUS_CA_W::new(self, 30)
260 }
261}
262#[doc = "SPI1 DDR control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
263pub struct DDR_SPEC;
264impl crate::RegisterSpec for DDR_SPEC {
265 type Ux = u32;
266}
267#[doc = "`read()` method returns [`ddr::R`](R) reader structure"]
268impl crate::Readable for DDR_SPEC {}
269#[doc = "`write(|w| ..)` method takes [`ddr::W`](W) writer structure"]
270impl crate::Writable for DDR_SPEC {
271 type Safety = crate::Unsafe;
272 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
273 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
274}
275#[doc = "`reset()` method sets DDR to value 0x20"]
276impl crate::Resettable for DDR_SPEC {
277 const RESET_VALUE: u32 = 0x20;
278}