esp32s3/extmem/
dcache_sync_ctrl.rs

1#[doc = "Register `DCACHE_SYNC_CTRL` reader"]
2pub type R = crate::R<DCACHE_SYNC_CTRL_SPEC>;
3#[doc = "Register `DCACHE_SYNC_CTRL` writer"]
4pub type W = crate::W<DCACHE_SYNC_CTRL_SPEC>;
5#[doc = "Field `DCACHE_INVALIDATE_ENA` reader - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
6pub type DCACHE_INVALIDATE_ENA_R = crate::BitReader;
7#[doc = "Field `DCACHE_INVALIDATE_ENA` writer - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
8pub type DCACHE_INVALIDATE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DCACHE_WRITEBACK_ENA` reader - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done."]
10pub type DCACHE_WRITEBACK_ENA_R = crate::BitReader;
11#[doc = "Field `DCACHE_WRITEBACK_ENA` writer - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done."]
12pub type DCACHE_WRITEBACK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DCACHE_CLEAN_ENA` reader - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done."]
14pub type DCACHE_CLEAN_ENA_R = crate::BitReader;
15#[doc = "Field `DCACHE_CLEAN_ENA` writer - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done."]
16pub type DCACHE_CLEAN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DCACHE_SYNC_DONE` reader - The bit is used to indicate clean/writeback/invalidate operation is finished."]
18pub type DCACHE_SYNC_DONE_R = crate::BitReader;
19impl R {
20    #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
21    #[inline(always)]
22    pub fn dcache_invalidate_ena(&self) -> DCACHE_INVALIDATE_ENA_R {
23        DCACHE_INVALIDATE_ENA_R::new((self.bits & 1) != 0)
24    }
25    #[doc = "Bit 1 - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done."]
26    #[inline(always)]
27    pub fn dcache_writeback_ena(&self) -> DCACHE_WRITEBACK_ENA_R {
28        DCACHE_WRITEBACK_ENA_R::new(((self.bits >> 1) & 1) != 0)
29    }
30    #[doc = "Bit 2 - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done."]
31    #[inline(always)]
32    pub fn dcache_clean_ena(&self) -> DCACHE_CLEAN_ENA_R {
33        DCACHE_CLEAN_ENA_R::new(((self.bits >> 2) & 1) != 0)
34    }
35    #[doc = "Bit 3 - The bit is used to indicate clean/writeback/invalidate operation is finished."]
36    #[inline(always)]
37    pub fn dcache_sync_done(&self) -> DCACHE_SYNC_DONE_R {
38        DCACHE_SYNC_DONE_R::new(((self.bits >> 3) & 1) != 0)
39    }
40}
41#[cfg(feature = "impl-register-debug")]
42impl core::fmt::Debug for R {
43    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
44        f.debug_struct("DCACHE_SYNC_CTRL")
45            .field("dcache_invalidate_ena", &self.dcache_invalidate_ena())
46            .field("dcache_writeback_ena", &self.dcache_writeback_ena())
47            .field("dcache_clean_ena", &self.dcache_clean_ena())
48            .field("dcache_sync_done", &self.dcache_sync_done())
49            .finish()
50    }
51}
52impl W {
53    #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
54    #[inline(always)]
55    pub fn dcache_invalidate_ena(&mut self) -> DCACHE_INVALIDATE_ENA_W<DCACHE_SYNC_CTRL_SPEC> {
56        DCACHE_INVALIDATE_ENA_W::new(self, 0)
57    }
58    #[doc = "Bit 1 - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done."]
59    #[inline(always)]
60    pub fn dcache_writeback_ena(&mut self) -> DCACHE_WRITEBACK_ENA_W<DCACHE_SYNC_CTRL_SPEC> {
61        DCACHE_WRITEBACK_ENA_W::new(self, 1)
62    }
63    #[doc = "Bit 2 - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done."]
64    #[inline(always)]
65    pub fn dcache_clean_ena(&mut self) -> DCACHE_CLEAN_ENA_W<DCACHE_SYNC_CTRL_SPEC> {
66        DCACHE_CLEAN_ENA_W::new(self, 2)
67    }
68}
69#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_sync_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_sync_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
70pub struct DCACHE_SYNC_CTRL_SPEC;
71impl crate::RegisterSpec for DCACHE_SYNC_CTRL_SPEC {
72    type Ux = u32;
73}
74#[doc = "`read()` method returns [`dcache_sync_ctrl::R`](R) reader structure"]
75impl crate::Readable for DCACHE_SYNC_CTRL_SPEC {}
76#[doc = "`write(|w| ..)` method takes [`dcache_sync_ctrl::W`](W) writer structure"]
77impl crate::Writable for DCACHE_SYNC_CTRL_SPEC {
78    type Safety = crate::Unsafe;
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
81}
82#[doc = "`reset()` method sets DCACHE_SYNC_CTRL to value 0x01"]
83impl crate::Resettable for DCACHE_SYNC_CTRL_SPEC {
84    const RESET_VALUE: u32 = 0x01;
85}
esp32s3/extmem/dcache_sync_ctrl.rs

esp32s3/extmem/
dcache_sync_ctrl.rs
