esp32s3/lcd_cam/
lc_dma_int_clr.rs

1#[doc = "Register `LC_DMA_INT_CLR` writer"]
2pub type W = crate::W<LC_DMA_INT_CLR_SPEC>;
3#[doc = "Field `LCD_VSYNC_INT_CLR` writer - The clear bit for LCD_CAM_LCD_VSYNC_INT interrupt."]
4pub type LCD_VSYNC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `LCD_TRANS_DONE_INT_CLR` writer - The clear bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt."]
6pub type LCD_TRANS_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `CAM_VSYNC_INT_CLR` writer - The clear bit for LCD_CAM_CAM_VSYNC_INT interrupt."]
8pub type CAM_VSYNC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CAM_HS_INT_CLR` writer - The clear bit for LCD_CAM_CAM_HS_INT interrupt."]
10pub type CAM_HS_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[cfg(feature = "impl-register-debug")]
12impl core::fmt::Debug for crate::generic::Reg<LC_DMA_INT_CLR_SPEC> {
13    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
14        write!(f, "(not readable)")
15    }
16}
17impl W {
18    #[doc = "Bit 0 - The clear bit for LCD_CAM_LCD_VSYNC_INT interrupt."]
19    #[inline(always)]
20    pub fn lcd_vsync_int_clr(&mut self) -> LCD_VSYNC_INT_CLR_W<LC_DMA_INT_CLR_SPEC> {
21        LCD_VSYNC_INT_CLR_W::new(self, 0)
22    }
23    #[doc = "Bit 1 - The clear bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt."]
24    #[inline(always)]
25    pub fn lcd_trans_done_int_clr(&mut self) -> LCD_TRANS_DONE_INT_CLR_W<LC_DMA_INT_CLR_SPEC> {
26        LCD_TRANS_DONE_INT_CLR_W::new(self, 1)
27    }
28    #[doc = "Bit 2 - The clear bit for LCD_CAM_CAM_VSYNC_INT interrupt."]
29    #[inline(always)]
30    pub fn cam_vsync_int_clr(&mut self) -> CAM_VSYNC_INT_CLR_W<LC_DMA_INT_CLR_SPEC> {
31        CAM_VSYNC_INT_CLR_W::new(self, 2)
32    }
33    #[doc = "Bit 3 - The clear bit for LCD_CAM_CAM_HS_INT interrupt."]
34    #[inline(always)]
35    pub fn cam_hs_int_clr(&mut self) -> CAM_HS_INT_CLR_W<LC_DMA_INT_CLR_SPEC> {
36        CAM_HS_INT_CLR_W::new(self, 3)
37    }
38}
39#[doc = "LCD_CAM GDMA interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lc_dma_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
40pub struct LC_DMA_INT_CLR_SPEC;
41impl crate::RegisterSpec for LC_DMA_INT_CLR_SPEC {
42    type Ux = u32;
43}
44#[doc = "`write(|w| ..)` method takes [`lc_dma_int_clr::W`](W) writer structure"]
45impl crate::Writable for LC_DMA_INT_CLR_SPEC {
46    type Safety = crate::Unsafe;
47    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
48    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
49}
50#[doc = "`reset()` method sets LC_DMA_INT_CLR to value 0"]
51impl crate::Resettable for LC_DMA_INT_CLR_SPEC {
52    const RESET_VALUE: u32 = 0;
53}
esp32s3/lcd_cam/lc_dma_int_clr.rs

esp32s3/lcd_cam/
lc_dma_int_clr.rs
