esp32s3/rtc_cntl/
pg_ctrl.rs

1#[doc = "Register `PG_CTRL` reader"]
2pub type R = crate::R<PG_CTRL_SPEC>;
3#[doc = "Register `PG_CTRL` writer"]
4pub type W = crate::W<PG_CTRL_SPEC>;
5#[doc = "Field `POWER_GLITCH_DSENSE` reader - GLITCH_DSENSE"]
6pub type POWER_GLITCH_DSENSE_R = crate::FieldReader;
7#[doc = "Field `POWER_GLITCH_DSENSE` writer - GLITCH_DSENSE"]
8pub type POWER_GLITCH_DSENSE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `POWER_GLITCH_FORCE_PD` reader - force power glitch disable"]
10pub type POWER_GLITCH_FORCE_PD_R = crate::BitReader;
11#[doc = "Field `POWER_GLITCH_FORCE_PD` writer - force power glitch disable"]
12pub type POWER_GLITCH_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `POWER_GLITCH_FORCE_PU` reader - force power glitch enable"]
14pub type POWER_GLITCH_FORCE_PU_R = crate::BitReader;
15#[doc = "Field `POWER_GLITCH_FORCE_PU` writer - force power glitch enable"]
16pub type POWER_GLITCH_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `POWER_GLITCH_EFUSE_SEL` reader - select use analog fib signal"]
18pub type POWER_GLITCH_EFUSE_SEL_R = crate::BitReader;
19#[doc = "Field `POWER_GLITCH_EFUSE_SEL` writer - select use analog fib signal"]
20pub type POWER_GLITCH_EFUSE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `POWER_GLITCH_EN` reader - enable power glitch"]
22pub type POWER_GLITCH_EN_R = crate::BitReader;
23#[doc = "Field `POWER_GLITCH_EN` writer - enable power glitch"]
24pub type POWER_GLITCH_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bits 26:27 - GLITCH_DSENSE"]
27    #[inline(always)]
28    pub fn power_glitch_dsense(&self) -> POWER_GLITCH_DSENSE_R {
29        POWER_GLITCH_DSENSE_R::new(((self.bits >> 26) & 3) as u8)
30    }
31    #[doc = "Bit 28 - force power glitch disable"]
32    #[inline(always)]
33    pub fn power_glitch_force_pd(&self) -> POWER_GLITCH_FORCE_PD_R {
34        POWER_GLITCH_FORCE_PD_R::new(((self.bits >> 28) & 1) != 0)
35    }
36    #[doc = "Bit 29 - force power glitch enable"]
37    #[inline(always)]
38    pub fn power_glitch_force_pu(&self) -> POWER_GLITCH_FORCE_PU_R {
39        POWER_GLITCH_FORCE_PU_R::new(((self.bits >> 29) & 1) != 0)
40    }
41    #[doc = "Bit 30 - select use analog fib signal"]
42    #[inline(always)]
43    pub fn power_glitch_efuse_sel(&self) -> POWER_GLITCH_EFUSE_SEL_R {
44        POWER_GLITCH_EFUSE_SEL_R::new(((self.bits >> 30) & 1) != 0)
45    }
46    #[doc = "Bit 31 - enable power glitch"]
47    #[inline(always)]
48    pub fn power_glitch_en(&self) -> POWER_GLITCH_EN_R {
49        POWER_GLITCH_EN_R::new(((self.bits >> 31) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("PG_CTRL")
56            .field("power_glitch_dsense", &self.power_glitch_dsense())
57            .field("power_glitch_force_pd", &self.power_glitch_force_pd())
58            .field("power_glitch_force_pu", &self.power_glitch_force_pu())
59            .field("power_glitch_efuse_sel", &self.power_glitch_efuse_sel())
60            .field("power_glitch_en", &self.power_glitch_en())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bits 26:27 - GLITCH_DSENSE"]
66    #[inline(always)]
67    pub fn power_glitch_dsense(&mut self) -> POWER_GLITCH_DSENSE_W<PG_CTRL_SPEC> {
68        POWER_GLITCH_DSENSE_W::new(self, 26)
69    }
70    #[doc = "Bit 28 - force power glitch disable"]
71    #[inline(always)]
72    pub fn power_glitch_force_pd(&mut self) -> POWER_GLITCH_FORCE_PD_W<PG_CTRL_SPEC> {
73        POWER_GLITCH_FORCE_PD_W::new(self, 28)
74    }
75    #[doc = "Bit 29 - force power glitch enable"]
76    #[inline(always)]
77    pub fn power_glitch_force_pu(&mut self) -> POWER_GLITCH_FORCE_PU_W<PG_CTRL_SPEC> {
78        POWER_GLITCH_FORCE_PU_W::new(self, 29)
79    }
80    #[doc = "Bit 30 - select use analog fib signal"]
81    #[inline(always)]
82    pub fn power_glitch_efuse_sel(&mut self) -> POWER_GLITCH_EFUSE_SEL_W<PG_CTRL_SPEC> {
83        POWER_GLITCH_EFUSE_SEL_W::new(self, 30)
84    }
85    #[doc = "Bit 31 - enable power glitch"]
86    #[inline(always)]
87    pub fn power_glitch_en(&mut self) -> POWER_GLITCH_EN_W<PG_CTRL_SPEC> {
88        POWER_GLITCH_EN_W::new(self, 31)
89    }
90}
91#[doc = "configure power glitch\n\nYou can [`read`](crate::Reg::read) this register and get [`pg_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pg_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct PG_CTRL_SPEC;
93impl crate::RegisterSpec for PG_CTRL_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`pg_ctrl::R`](R) reader structure"]
97impl crate::Readable for PG_CTRL_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`pg_ctrl::W`](W) writer structure"]
99impl crate::Writable for PG_CTRL_SPEC {
100    type Safety = crate::Unsafe;
101    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets PG_CTRL to value 0"]
105impl crate::Resettable for PG_CTRL_SPEC {
106    const RESET_VALUE: u32 = 0;
107}
esp32s3/rtc_cntl/pg_ctrl.rs

esp32s3/rtc_cntl/
pg_ctrl.rs
