1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `CH_TX_END(0-3)` writer - Set this bit to clear theCH%s_TX_END_INT interrupt."]
4pub type CH_TX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `CH_TX_ERR(0-3)` writer - Set this bit to clear theCH%s_ERR_INT interrupt."]
6pub type CH_TX_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `CH_TX_THR_EVENT(0-3)` writer - Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt."]
8pub type CH_TX_THR_EVENT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CH_TX_LOOP(0-3)` writer - Set this bit to clear theCH%s_TX_LOOP_INT interrupt."]
10pub type CH_TX_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `CH_RX_END(4-7)` writer - Set this bit to clear theCH4_RX_END_INT interrupt."]
12pub type CH_RX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CH_RX_ERR(4-7)` writer - Set this bit to clear theCH4_ERR_INT interrupt."]
14pub type CH_RX_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `CH_RX_THR_EVENT(4-7)` writer - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
16pub type CH_RX_THR_EVENT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TX_CH3_DMA_ACCESS_FAIL` writer - Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt."]
18pub type TX_CH3_DMA_ACCESS_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `RX_CH7_DMA_ACCESS_FAIL` writer - Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt."]
20pub type RX_CH7_DMA_ACCESS_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[cfg(feature = "impl-register-debug")]
22impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
23 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
24 write!(f, "(not readable)")
25 }
26}
27impl W {
28 #[doc = "Set this bit to clear theCH(0-3)_TX_END_INT interrupt."]
29 #[doc = ""]
30 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
31 #[inline(always)]
32 pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_CLR_SPEC> {
33 #[allow(clippy::no_effect)]
34 [(); 4][n as usize];
35 CH_TX_END_W::new(self, n)
36 }
37 #[doc = "Bit 0 - Set this bit to clear theCH0_TX_END_INT interrupt."]
38 #[inline(always)]
39 pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
40 CH_TX_END_W::new(self, 0)
41 }
42 #[doc = "Bit 1 - Set this bit to clear theCH1_TX_END_INT interrupt."]
43 #[inline(always)]
44 pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
45 CH_TX_END_W::new(self, 1)
46 }
47 #[doc = "Bit 2 - Set this bit to clear theCH2_TX_END_INT interrupt."]
48 #[inline(always)]
49 pub fn ch2_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
50 CH_TX_END_W::new(self, 2)
51 }
52 #[doc = "Bit 3 - Set this bit to clear theCH3_TX_END_INT interrupt."]
53 #[inline(always)]
54 pub fn ch3_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
55 CH_TX_END_W::new(self, 3)
56 }
57 #[doc = "Set this bit to clear theCH(0-3)_ERR_INT interrupt."]
58 #[doc = ""]
59 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_ERR` field.</div>"]
60 #[inline(always)]
61 pub fn ch_tx_err(&mut self, n: u8) -> CH_TX_ERR_W<INT_CLR_SPEC> {
62 #[allow(clippy::no_effect)]
63 [(); 4][n as usize];
64 CH_TX_ERR_W::new(self, n + 4)
65 }
66 #[doc = "Bit 4 - Set this bit to clear theCH0_ERR_INT interrupt."]
67 #[inline(always)]
68 pub fn ch0_tx_err(&mut self) -> CH_TX_ERR_W<INT_CLR_SPEC> {
69 CH_TX_ERR_W::new(self, 4)
70 }
71 #[doc = "Bit 5 - Set this bit to clear theCH1_ERR_INT interrupt."]
72 #[inline(always)]
73 pub fn ch1_tx_err(&mut self) -> CH_TX_ERR_W<INT_CLR_SPEC> {
74 CH_TX_ERR_W::new(self, 5)
75 }
76 #[doc = "Bit 6 - Set this bit to clear theCH2_ERR_INT interrupt."]
77 #[inline(always)]
78 pub fn ch2_tx_err(&mut self) -> CH_TX_ERR_W<INT_CLR_SPEC> {
79 CH_TX_ERR_W::new(self, 6)
80 }
81 #[doc = "Bit 7 - Set this bit to clear theCH3_ERR_INT interrupt."]
82 #[inline(always)]
83 pub fn ch3_tx_err(&mut self) -> CH_TX_ERR_W<INT_CLR_SPEC> {
84 CH_TX_ERR_W::new(self, 7)
85 }
86 #[doc = "Set this bit to clear theCH(0-3)_TX_THR_EVENT_INT interrupt."]
87 #[doc = ""]
88 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
89 #[inline(always)]
90 pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
91 #[allow(clippy::no_effect)]
92 [(); 4][n as usize];
93 CH_TX_THR_EVENT_W::new(self, n + 8)
94 }
95 #[doc = "Bit 8 - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt."]
96 #[inline(always)]
97 pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
98 CH_TX_THR_EVENT_W::new(self, 8)
99 }
100 #[doc = "Bit 9 - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt."]
101 #[inline(always)]
102 pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
103 CH_TX_THR_EVENT_W::new(self, 9)
104 }
105 #[doc = "Bit 10 - Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt."]
106 #[inline(always)]
107 pub fn ch2_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
108 CH_TX_THR_EVENT_W::new(self, 10)
109 }
110 #[doc = "Bit 11 - Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt."]
111 #[inline(always)]
112 pub fn ch3_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
113 CH_TX_THR_EVENT_W::new(self, 11)
114 }
115 #[doc = "Set this bit to clear theCH(0-3)_TX_LOOP_INT interrupt."]
116 #[doc = ""]
117 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_LOOP` field.</div>"]
118 #[inline(always)]
119 pub fn ch_tx_loop(&mut self, n: u8) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
120 #[allow(clippy::no_effect)]
121 [(); 4][n as usize];
122 CH_TX_LOOP_W::new(self, n + 12)
123 }
124 #[doc = "Bit 12 - Set this bit to clear theCH0_TX_LOOP_INT interrupt."]
125 #[inline(always)]
126 pub fn ch0_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
127 CH_TX_LOOP_W::new(self, 12)
128 }
129 #[doc = "Bit 13 - Set this bit to clear theCH1_TX_LOOP_INT interrupt."]
130 #[inline(always)]
131 pub fn ch1_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
132 CH_TX_LOOP_W::new(self, 13)
133 }
134 #[doc = "Bit 14 - Set this bit to clear theCH2_TX_LOOP_INT interrupt."]
135 #[inline(always)]
136 pub fn ch2_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
137 CH_TX_LOOP_W::new(self, 14)
138 }
139 #[doc = "Bit 15 - Set this bit to clear theCH3_TX_LOOP_INT interrupt."]
140 #[inline(always)]
141 pub fn ch3_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
142 CH_TX_LOOP_W::new(self, 15)
143 }
144 #[doc = "Set this bit to clear theCH4_RX_END_INT interrupt."]
145 #[doc = ""]
146 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_END` field.</div>"]
147 #[inline(always)]
148 pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_CLR_SPEC> {
149 #[allow(clippy::no_effect)]
150 [(); 4][n as usize];
151 CH_RX_END_W::new(self, n + 16)
152 }
153 #[doc = "Bit 16 - Set this bit to clear theCH4_RX_END_INT interrupt."]
154 #[inline(always)]
155 pub fn ch4_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
156 CH_RX_END_W::new(self, 16)
157 }
158 #[doc = "Bit 17 - Set this bit to clear theCH4_RX_END_INT interrupt."]
159 #[inline(always)]
160 pub fn ch5_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
161 CH_RX_END_W::new(self, 17)
162 }
163 #[doc = "Bit 18 - Set this bit to clear theCH4_RX_END_INT interrupt."]
164 #[inline(always)]
165 pub fn ch6_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
166 CH_RX_END_W::new(self, 18)
167 }
168 #[doc = "Bit 19 - Set this bit to clear theCH4_RX_END_INT interrupt."]
169 #[inline(always)]
170 pub fn ch7_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
171 CH_RX_END_W::new(self, 19)
172 }
173 #[doc = "Set this bit to clear theCH4_ERR_INT interrupt."]
174 #[doc = ""]
175 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_ERR` field.</div>"]
176 #[inline(always)]
177 pub fn ch_rx_err(&mut self, n: u8) -> CH_RX_ERR_W<INT_CLR_SPEC> {
178 #[allow(clippy::no_effect)]
179 [(); 4][n as usize];
180 CH_RX_ERR_W::new(self, n + 20)
181 }
182 #[doc = "Bit 20 - Set this bit to clear theCH4_ERR_INT interrupt."]
183 #[inline(always)]
184 pub fn ch4_rx_err(&mut self) -> CH_RX_ERR_W<INT_CLR_SPEC> {
185 CH_RX_ERR_W::new(self, 20)
186 }
187 #[doc = "Bit 21 - Set this bit to clear theCH4_ERR_INT interrupt."]
188 #[inline(always)]
189 pub fn ch5_rx_err(&mut self) -> CH_RX_ERR_W<INT_CLR_SPEC> {
190 CH_RX_ERR_W::new(self, 21)
191 }
192 #[doc = "Bit 22 - Set this bit to clear theCH4_ERR_INT interrupt."]
193 #[inline(always)]
194 pub fn ch6_rx_err(&mut self) -> CH_RX_ERR_W<INT_CLR_SPEC> {
195 CH_RX_ERR_W::new(self, 22)
196 }
197 #[doc = "Bit 23 - Set this bit to clear theCH4_ERR_INT interrupt."]
198 #[inline(always)]
199 pub fn ch7_rx_err(&mut self) -> CH_RX_ERR_W<INT_CLR_SPEC> {
200 CH_RX_ERR_W::new(self, 23)
201 }
202 #[doc = "Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
203 #[doc = ""]
204 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_THR_EVENT` field.</div>"]
205 #[inline(always)]
206 pub fn ch_rx_thr_event(&mut self, n: u8) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
207 #[allow(clippy::no_effect)]
208 [(); 4][n as usize];
209 CH_RX_THR_EVENT_W::new(self, n + 24)
210 }
211 #[doc = "Bit 24 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
212 #[inline(always)]
213 pub fn ch4_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
214 CH_RX_THR_EVENT_W::new(self, 24)
215 }
216 #[doc = "Bit 25 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
217 #[inline(always)]
218 pub fn ch5_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
219 CH_RX_THR_EVENT_W::new(self, 25)
220 }
221 #[doc = "Bit 26 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
222 #[inline(always)]
223 pub fn ch6_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
224 CH_RX_THR_EVENT_W::new(self, 26)
225 }
226 #[doc = "Bit 27 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
227 #[inline(always)]
228 pub fn ch7_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
229 CH_RX_THR_EVENT_W::new(self, 27)
230 }
231 #[doc = "Bit 28 - Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt."]
232 #[inline(always)]
233 pub fn tx_ch3_dma_access_fail(&mut self) -> TX_CH3_DMA_ACCESS_FAIL_W<INT_CLR_SPEC> {
234 TX_CH3_DMA_ACCESS_FAIL_W::new(self, 28)
235 }
236 #[doc = "Bit 29 - Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt."]
237 #[inline(always)]
238 pub fn rx_ch7_dma_access_fail(&mut self) -> RX_CH7_DMA_ACCESS_FAIL_W<INT_CLR_SPEC> {
239 RX_CH7_DMA_ACCESS_FAIL_W::new(self, 29)
240 }
241}
242#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
243pub struct INT_CLR_SPEC;
244impl crate::RegisterSpec for INT_CLR_SPEC {
245 type Ux = u32;
246}
247#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
248impl crate::Writable for INT_CLR_SPEC {
249 type Safety = crate::Unsafe;
250 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
251 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
252}
253#[doc = "`reset()` method sets INT_CLR to value 0"]
254impl crate::Resettable for INT_CLR_SPEC {
255 const RESET_VALUE: u32 = 0;
256}