1#[doc = "Register `MISC` reader"]
2pub type R = crate::R<MISC_SPEC>;
3#[doc = "Register `MISC` writer"]
4pub type W = crate::W<MISC_SPEC>;
5#[doc = "Field `CS_DIS(0-1)` reader - Set this bit to raise high SPI_CS%s pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS%s is in low level when SPI1 transfer starts"]
6pub type CS_DIS_R = crate::BitReader;
7#[doc = "Field `CS_DIS(0-1)` writer - Set this bit to raise high SPI_CS%s pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS%s is in low level when SPI1 transfer starts"]
8pub type CS_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CK_IDLE_EDGE` reader - 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle."]
10pub type CK_IDLE_EDGE_R = crate::BitReader;
11#[doc = "Field `CK_IDLE_EDGE` writer - 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle."]
12pub type CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CS_KEEP_ACTIVE` reader - SPI_CS line keep low when the bit is set."]
14pub type CS_KEEP_ACTIVE_R = crate::BitReader;
15#[doc = "Field `CS_KEEP_ACTIVE` writer - SPI_CS line keep low when the bit is set."]
16pub type CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `AUTO_PER` reader - Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent."]
18pub type AUTO_PER_R = crate::BitReader;
19#[doc = "Field `AUTO_PER` writer - Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent."]
20pub type AUTO_PER_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22 #[doc = "Set this bit to raise high SPI_CS(0-1) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-1) is in low level when SPI1 transfer starts"]
23 #[doc = ""]
24 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
25 #[inline(always)]
26 pub fn cs_dis(&self, n: u8) -> CS_DIS_R {
27 #[allow(clippy::no_effect)]
28 [(); 2][n as usize];
29 CS_DIS_R::new(((self.bits >> n) & 1) != 0)
30 }
31 #[doc = "Iterator for array of:"]
32 #[doc = "Set this bit to raise high SPI_CS(0-1) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-1) is in low level when SPI1 transfer starts"]
33 #[inline(always)]
34 pub fn cs_dis_iter(&self) -> impl Iterator<Item = CS_DIS_R> + '_ {
35 (0..2).map(move |n| CS_DIS_R::new(((self.bits >> n) & 1) != 0))
36 }
37 #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
38 #[inline(always)]
39 pub fn cs0_dis(&self) -> CS_DIS_R {
40 CS_DIS_R::new((self.bits & 1) != 0)
41 }
42 #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
43 #[inline(always)]
44 pub fn cs1_dis(&self) -> CS_DIS_R {
45 CS_DIS_R::new(((self.bits >> 1) & 1) != 0)
46 }
47 #[doc = "Bit 9 - 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle."]
48 #[inline(always)]
49 pub fn ck_idle_edge(&self) -> CK_IDLE_EDGE_R {
50 CK_IDLE_EDGE_R::new(((self.bits >> 9) & 1) != 0)
51 }
52 #[doc = "Bit 10 - SPI_CS line keep low when the bit is set."]
53 #[inline(always)]
54 pub fn cs_keep_active(&self) -> CS_KEEP_ACTIVE_R {
55 CS_KEEP_ACTIVE_R::new(((self.bits >> 10) & 1) != 0)
56 }
57 #[doc = "Bit 11 - Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent."]
58 #[inline(always)]
59 pub fn auto_per(&self) -> AUTO_PER_R {
60 AUTO_PER_R::new(((self.bits >> 11) & 1) != 0)
61 }
62}
63#[cfg(feature = "impl-register-debug")]
64impl core::fmt::Debug for R {
65 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
66 f.debug_struct("MISC")
67 .field("ck_idle_edge", &self.ck_idle_edge())
68 .field("cs_keep_active", &self.cs_keep_active())
69 .field("auto_per", &self.auto_per())
70 .field("cs0_dis", &self.cs0_dis())
71 .field("cs1_dis", &self.cs1_dis())
72 .finish()
73 }
74}
75impl W {
76 #[doc = "Set this bit to raise high SPI_CS(0-1) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-1) is in low level when SPI1 transfer starts"]
77 #[doc = ""]
78 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
79 #[inline(always)]
80 pub fn cs_dis(&mut self, n: u8) -> CS_DIS_W<MISC_SPEC> {
81 #[allow(clippy::no_effect)]
82 [(); 2][n as usize];
83 CS_DIS_W::new(self, n)
84 }
85 #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
86 #[inline(always)]
87 pub fn cs0_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
88 CS_DIS_W::new(self, 0)
89 }
90 #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
91 #[inline(always)]
92 pub fn cs1_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
93 CS_DIS_W::new(self, 1)
94 }
95 #[doc = "Bit 9 - 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle."]
96 #[inline(always)]
97 pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
98 CK_IDLE_EDGE_W::new(self, 9)
99 }
100 #[doc = "Bit 10 - SPI_CS line keep low when the bit is set."]
101 #[inline(always)]
102 pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
103 CS_KEEP_ACTIVE_W::new(self, 10)
104 }
105 #[doc = "Bit 11 - Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent."]
106 #[inline(always)]
107 pub fn auto_per(&mut self) -> AUTO_PER_W<MISC_SPEC> {
108 AUTO_PER_W::new(self, 11)
109 }
110}
111#[doc = "SPI1 misc register.\n\nYou can [`read`](crate::Reg::read) this register and get [`misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
112pub struct MISC_SPEC;
113impl crate::RegisterSpec for MISC_SPEC {
114 type Ux = u32;
115}
116#[doc = "`read()` method returns [`misc::R`](R) reader structure"]
117impl crate::Readable for MISC_SPEC {}
118#[doc = "`write(|w| ..)` method takes [`misc::W`](W) writer structure"]
119impl crate::Writable for MISC_SPEC {
120 type Safety = crate::Unsafe;
121 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
122 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
123}
124#[doc = "`reset()` method sets MISC to value 0x02"]
125impl crate::Resettable for MISC_SPEC {
126 const RESET_VALUE: u32 = 0x02;
127}