esp32s3/
extmem.rs

1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    dcache_ctrl: DCACHE_CTRL,
6    dcache_ctrl1: DCACHE_CTRL1,
7    dcache_tag_power_ctrl: DCACHE_TAG_POWER_CTRL,
8    dcache_prelock_ctrl: DCACHE_PRELOCK_CTRL,
9    dcache_prelock_sct0_addr: DCACHE_PRELOCK_SCT0_ADDR,
10    dcache_prelock_sct1_addr: DCACHE_PRELOCK_SCT1_ADDR,
11    dcache_prelock_sct_size: DCACHE_PRELOCK_SCT_SIZE,
12    dcache_lock_ctrl: DCACHE_LOCK_CTRL,
13    dcache_lock_addr: DCACHE_LOCK_ADDR,
14    dcache_lock_size: DCACHE_LOCK_SIZE,
15    dcache_sync_ctrl: DCACHE_SYNC_CTRL,
16    dcache_sync_addr: DCACHE_SYNC_ADDR,
17    dcache_sync_size: DCACHE_SYNC_SIZE,
18    dcache_occupy_ctrl: DCACHE_OCCUPY_CTRL,
19    dcache_occupy_addr: DCACHE_OCCUPY_ADDR,
20    dcache_occupy_size: DCACHE_OCCUPY_SIZE,
21    dcache_preload_ctrl: DCACHE_PRELOAD_CTRL,
22    dcache_preload_addr: DCACHE_PRELOAD_ADDR,
23    dcache_preload_size: DCACHE_PRELOAD_SIZE,
24    dcache_autoload_ctrl: DCACHE_AUTOLOAD_CTRL,
25    dcache_autoload_sct0_addr: DCACHE_AUTOLOAD_SCT0_ADDR,
26    dcache_autoload_sct0_size: DCACHE_AUTOLOAD_SCT0_SIZE,
27    dcache_autoload_sct1_addr: DCACHE_AUTOLOAD_SCT1_ADDR,
28    dcache_autoload_sct1_size: DCACHE_AUTOLOAD_SCT1_SIZE,
29    icache_ctrl: ICACHE_CTRL,
30    icache_ctrl1: ICACHE_CTRL1,
31    icache_tag_power_ctrl: ICACHE_TAG_POWER_CTRL,
32    icache_prelock_ctrl: ICACHE_PRELOCK_CTRL,
33    icache_prelock_sct0_addr: ICACHE_PRELOCK_SCT0_ADDR,
34    icache_prelock_sct1_addr: ICACHE_PRELOCK_SCT1_ADDR,
35    icache_prelock_sct_size: ICACHE_PRELOCK_SCT_SIZE,
36    icache_lock_ctrl: ICACHE_LOCK_CTRL,
37    icache_lock_addr: ICACHE_LOCK_ADDR,
38    icache_lock_size: ICACHE_LOCK_SIZE,
39    icache_sync_ctrl: ICACHE_SYNC_CTRL,
40    icache_sync_addr: ICACHE_SYNC_ADDR,
41    icache_sync_size: ICACHE_SYNC_SIZE,
42    icache_preload_ctrl: ICACHE_PRELOAD_CTRL,
43    icache_preload_addr: ICACHE_PRELOAD_ADDR,
44    icache_preload_size: ICACHE_PRELOAD_SIZE,
45    icache_autoload_ctrl: ICACHE_AUTOLOAD_CTRL,
46    icache_autoload_sct0_addr: ICACHE_AUTOLOAD_SCT0_ADDR,
47    icache_autoload_sct0_size: ICACHE_AUTOLOAD_SCT0_SIZE,
48    icache_autoload_sct1_addr: ICACHE_AUTOLOAD_SCT1_ADDR,
49    icache_autoload_sct1_size: ICACHE_AUTOLOAD_SCT1_SIZE,
50    ibus_to_flash_start_vaddr: IBUS_TO_FLASH_START_VADDR,
51    ibus_to_flash_end_vaddr: IBUS_TO_FLASH_END_VADDR,
52    dbus_to_flash_start_vaddr: DBUS_TO_FLASH_START_VADDR,
53    dbus_to_flash_end_vaddr: DBUS_TO_FLASH_END_VADDR,
54    cache_acs_cnt_clr: CACHE_ACS_CNT_CLR,
55    ibus_acs_miss_cnt: IBUS_ACS_MISS_CNT,
56    ibus_acs_cnt: IBUS_ACS_CNT,
57    dbus_acs_flash_miss_cnt: DBUS_ACS_FLASH_MISS_CNT,
58    dbus_acs_spiram_miss_cnt: DBUS_ACS_SPIRAM_MISS_CNT,
59    dbus_acs_cnt: DBUS_ACS_CNT,
60    cache_ilg_int_ena: CACHE_ILG_INT_ENA,
61    cache_ilg_int_clr: CACHE_ILG_INT_CLR,
62    cache_ilg_int_st: CACHE_ILG_INT_ST,
63    core0_acs_cache_int_ena: CORE0_ACS_CACHE_INT_ENA,
64    core0_acs_cache_int_clr: CORE0_ACS_CACHE_INT_CLR,
65    core0_acs_cache_int_st: CORE0_ACS_CACHE_INT_ST,
66    core1_acs_cache_int_ena: CORE1_ACS_CACHE_INT_ENA,
67    core1_acs_cache_int_clr: CORE1_ACS_CACHE_INT_CLR,
68    core1_acs_cache_int_st: CORE1_ACS_CACHE_INT_ST,
69    core0_dbus_reject_st: CORE0_DBUS_REJECT_ST,
70    core0_dbus_reject_vaddr: CORE0_DBUS_REJECT_VADDR,
71    core0_ibus_reject_st: CORE0_IBUS_REJECT_ST,
72    core0_ibus_reject_vaddr: CORE0_IBUS_REJECT_VADDR,
73    core1_dbus_reject_st: CORE1_DBUS_REJECT_ST,
74    core1_dbus_reject_vaddr: CORE1_DBUS_REJECT_VADDR,
75    core1_ibus_reject_st: CORE1_IBUS_REJECT_ST,
76    core1_ibus_reject_vaddr: CORE1_IBUS_REJECT_VADDR,
77    cache_mmu_fault_content: CACHE_MMU_FAULT_CONTENT,
78    cache_mmu_fault_vaddr: CACHE_MMU_FAULT_VADDR,
79    cache_wrap_around_ctrl: CACHE_WRAP_AROUND_CTRL,
80    cache_mmu_power_ctrl: CACHE_MMU_POWER_CTRL,
81    cache_state: CACHE_STATE,
82    cache_encrypt_decrypt_record_disable: CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE,
83    cache_encrypt_decrypt_clk_force_on: CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON,
84    cache_bridge_arbiter_ctrl: CACHE_BRIDGE_ARBITER_CTRL,
85    cache_preload_int_ctrl: CACHE_PRELOAD_INT_CTRL,
86    cache_sync_int_ctrl: CACHE_SYNC_INT_CTRL,
87    cache_mmu_owner: CACHE_MMU_OWNER,
88    cache_conf_misc: CACHE_CONF_MISC,
89    dcache_freeze: DCACHE_FREEZE,
90    icache_freeze: ICACHE_FREEZE,
91    icache_atomic_operate_ena: ICACHE_ATOMIC_OPERATE_ENA,
92    dcache_atomic_operate_ena: DCACHE_ATOMIC_OPERATE_ENA,
93    cache_request: CACHE_REQUEST,
94    clock_gate: CLOCK_GATE,
95    _reserved90: [u8; 0x18],
96    cache_tag_object_ctrl: CACHE_TAG_OBJECT_CTRL,
97    cache_tag_way_object: CACHE_TAG_WAY_OBJECT,
98    cache_vaddr: CACHE_VADDR,
99    cache_tag_content: CACHE_TAG_CONTENT,
100    _reserved94: [u8; 0x026c],
101    date: DATE,
102}
103impl RegisterBlock {
104    #[doc = "0x00 - ******* Description ***********"]
105    #[inline(always)]
106    pub const fn dcache_ctrl(&self) -> &DCACHE_CTRL {
107        &self.dcache_ctrl
108    }
109    #[doc = "0x04 - ******* Description ***********"]
110    #[inline(always)]
111    pub const fn dcache_ctrl1(&self) -> &DCACHE_CTRL1 {
112        &self.dcache_ctrl1
113    }
114    #[doc = "0x08 - ******* Description ***********"]
115    #[inline(always)]
116    pub const fn dcache_tag_power_ctrl(&self) -> &DCACHE_TAG_POWER_CTRL {
117        &self.dcache_tag_power_ctrl
118    }
119    #[doc = "0x0c - ******* Description ***********"]
120    #[inline(always)]
121    pub const fn dcache_prelock_ctrl(&self) -> &DCACHE_PRELOCK_CTRL {
122        &self.dcache_prelock_ctrl
123    }
124    #[doc = "0x10 - ******* Description ***********"]
125    #[inline(always)]
126    pub const fn dcache_prelock_sct0_addr(&self) -> &DCACHE_PRELOCK_SCT0_ADDR {
127        &self.dcache_prelock_sct0_addr
128    }
129    #[doc = "0x14 - ******* Description ***********"]
130    #[inline(always)]
131    pub const fn dcache_prelock_sct1_addr(&self) -> &DCACHE_PRELOCK_SCT1_ADDR {
132        &self.dcache_prelock_sct1_addr
133    }
134    #[doc = "0x18 - ******* Description ***********"]
135    #[inline(always)]
136    pub const fn dcache_prelock_sct_size(&self) -> &DCACHE_PRELOCK_SCT_SIZE {
137        &self.dcache_prelock_sct_size
138    }
139    #[doc = "0x1c - ******* Description ***********"]
140    #[inline(always)]
141    pub const fn dcache_lock_ctrl(&self) -> &DCACHE_LOCK_CTRL {
142        &self.dcache_lock_ctrl
143    }
144    #[doc = "0x20 - ******* Description ***********"]
145    #[inline(always)]
146    pub const fn dcache_lock_addr(&self) -> &DCACHE_LOCK_ADDR {
147        &self.dcache_lock_addr
148    }
149    #[doc = "0x24 - ******* Description ***********"]
150    #[inline(always)]
151    pub const fn dcache_lock_size(&self) -> &DCACHE_LOCK_SIZE {
152        &self.dcache_lock_size
153    }
154    #[doc = "0x28 - ******* Description ***********"]
155    #[inline(always)]
156    pub const fn dcache_sync_ctrl(&self) -> &DCACHE_SYNC_CTRL {
157        &self.dcache_sync_ctrl
158    }
159    #[doc = "0x2c - ******* Description ***********"]
160    #[inline(always)]
161    pub const fn dcache_sync_addr(&self) -> &DCACHE_SYNC_ADDR {
162        &self.dcache_sync_addr
163    }
164    #[doc = "0x30 - ******* Description ***********"]
165    #[inline(always)]
166    pub const fn dcache_sync_size(&self) -> &DCACHE_SYNC_SIZE {
167        &self.dcache_sync_size
168    }
169    #[doc = "0x34 - ******* Description ***********"]
170    #[inline(always)]
171    pub const fn dcache_occupy_ctrl(&self) -> &DCACHE_OCCUPY_CTRL {
172        &self.dcache_occupy_ctrl
173    }
174    #[doc = "0x38 - ******* Description ***********"]
175    #[inline(always)]
176    pub const fn dcache_occupy_addr(&self) -> &DCACHE_OCCUPY_ADDR {
177        &self.dcache_occupy_addr
178    }
179    #[doc = "0x3c - ******* Description ***********"]
180    #[inline(always)]
181    pub const fn dcache_occupy_size(&self) -> &DCACHE_OCCUPY_SIZE {
182        &self.dcache_occupy_size
183    }
184    #[doc = "0x40 - ******* Description ***********"]
185    #[inline(always)]
186    pub const fn dcache_preload_ctrl(&self) -> &DCACHE_PRELOAD_CTRL {
187        &self.dcache_preload_ctrl
188    }
189    #[doc = "0x44 - ******* Description ***********"]
190    #[inline(always)]
191    pub const fn dcache_preload_addr(&self) -> &DCACHE_PRELOAD_ADDR {
192        &self.dcache_preload_addr
193    }
194    #[doc = "0x48 - ******* Description ***********"]
195    #[inline(always)]
196    pub const fn dcache_preload_size(&self) -> &DCACHE_PRELOAD_SIZE {
197        &self.dcache_preload_size
198    }
199    #[doc = "0x4c - ******* Description ***********"]
200    #[inline(always)]
201    pub const fn dcache_autoload_ctrl(&self) -> &DCACHE_AUTOLOAD_CTRL {
202        &self.dcache_autoload_ctrl
203    }
204    #[doc = "0x50 - ******* Description ***********"]
205    #[inline(always)]
206    pub const fn dcache_autoload_sct0_addr(&self) -> &DCACHE_AUTOLOAD_SCT0_ADDR {
207        &self.dcache_autoload_sct0_addr
208    }
209    #[doc = "0x54 - ******* Description ***********"]
210    #[inline(always)]
211    pub const fn dcache_autoload_sct0_size(&self) -> &DCACHE_AUTOLOAD_SCT0_SIZE {
212        &self.dcache_autoload_sct0_size
213    }
214    #[doc = "0x58 - ******* Description ***********"]
215    #[inline(always)]
216    pub const fn dcache_autoload_sct1_addr(&self) -> &DCACHE_AUTOLOAD_SCT1_ADDR {
217        &self.dcache_autoload_sct1_addr
218    }
219    #[doc = "0x5c - ******* Description ***********"]
220    #[inline(always)]
221    pub const fn dcache_autoload_sct1_size(&self) -> &DCACHE_AUTOLOAD_SCT1_SIZE {
222        &self.dcache_autoload_sct1_size
223    }
224    #[doc = "0x60 - ******* Description ***********"]
225    #[inline(always)]
226    pub const fn icache_ctrl(&self) -> &ICACHE_CTRL {
227        &self.icache_ctrl
228    }
229    #[doc = "0x64 - ******* Description ***********"]
230    #[inline(always)]
231    pub const fn icache_ctrl1(&self) -> &ICACHE_CTRL1 {
232        &self.icache_ctrl1
233    }
234    #[doc = "0x68 - ******* Description ***********"]
235    #[inline(always)]
236    pub const fn icache_tag_power_ctrl(&self) -> &ICACHE_TAG_POWER_CTRL {
237        &self.icache_tag_power_ctrl
238    }
239    #[doc = "0x6c - ******* Description ***********"]
240    #[inline(always)]
241    pub const fn icache_prelock_ctrl(&self) -> &ICACHE_PRELOCK_CTRL {
242        &self.icache_prelock_ctrl
243    }
244    #[doc = "0x70 - ******* Description ***********"]
245    #[inline(always)]
246    pub const fn icache_prelock_sct0_addr(&self) -> &ICACHE_PRELOCK_SCT0_ADDR {
247        &self.icache_prelock_sct0_addr
248    }
249    #[doc = "0x74 - ******* Description ***********"]
250    #[inline(always)]
251    pub const fn icache_prelock_sct1_addr(&self) -> &ICACHE_PRELOCK_SCT1_ADDR {
252        &self.icache_prelock_sct1_addr
253    }
254    #[doc = "0x78 - ******* Description ***********"]
255    #[inline(always)]
256    pub const fn icache_prelock_sct_size(&self) -> &ICACHE_PRELOCK_SCT_SIZE {
257        &self.icache_prelock_sct_size
258    }
259    #[doc = "0x7c - ******* Description ***********"]
260    #[inline(always)]
261    pub const fn icache_lock_ctrl(&self) -> &ICACHE_LOCK_CTRL {
262        &self.icache_lock_ctrl
263    }
264    #[doc = "0x80 - ******* Description ***********"]
265    #[inline(always)]
266    pub const fn icache_lock_addr(&self) -> &ICACHE_LOCK_ADDR {
267        &self.icache_lock_addr
268    }
269    #[doc = "0x84 - ******* Description ***********"]
270    #[inline(always)]
271    pub const fn icache_lock_size(&self) -> &ICACHE_LOCK_SIZE {
272        &self.icache_lock_size
273    }
274    #[doc = "0x88 - ******* Description ***********"]
275    #[inline(always)]
276    pub const fn icache_sync_ctrl(&self) -> &ICACHE_SYNC_CTRL {
277        &self.icache_sync_ctrl
278    }
279    #[doc = "0x8c - ******* Description ***********"]
280    #[inline(always)]
281    pub const fn icache_sync_addr(&self) -> &ICACHE_SYNC_ADDR {
282        &self.icache_sync_addr
283    }
284    #[doc = "0x90 - ******* Description ***********"]
285    #[inline(always)]
286    pub const fn icache_sync_size(&self) -> &ICACHE_SYNC_SIZE {
287        &self.icache_sync_size
288    }
289    #[doc = "0x94 - ******* Description ***********"]
290    #[inline(always)]
291    pub const fn icache_preload_ctrl(&self) -> &ICACHE_PRELOAD_CTRL {
292        &self.icache_preload_ctrl
293    }
294    #[doc = "0x98 - ******* Description ***********"]
295    #[inline(always)]
296    pub const fn icache_preload_addr(&self) -> &ICACHE_PRELOAD_ADDR {
297        &self.icache_preload_addr
298    }
299    #[doc = "0x9c - ******* Description ***********"]
300    #[inline(always)]
301    pub const fn icache_preload_size(&self) -> &ICACHE_PRELOAD_SIZE {
302        &self.icache_preload_size
303    }
304    #[doc = "0xa0 - ******* Description ***********"]
305    #[inline(always)]
306    pub const fn icache_autoload_ctrl(&self) -> &ICACHE_AUTOLOAD_CTRL {
307        &self.icache_autoload_ctrl
308    }
309    #[doc = "0xa4 - ******* Description ***********"]
310    #[inline(always)]
311    pub const fn icache_autoload_sct0_addr(&self) -> &ICACHE_AUTOLOAD_SCT0_ADDR {
312        &self.icache_autoload_sct0_addr
313    }
314    #[doc = "0xa8 - ******* Description ***********"]
315    #[inline(always)]
316    pub const fn icache_autoload_sct0_size(&self) -> &ICACHE_AUTOLOAD_SCT0_SIZE {
317        &self.icache_autoload_sct0_size
318    }
319    #[doc = "0xac - ******* Description ***********"]
320    #[inline(always)]
321    pub const fn icache_autoload_sct1_addr(&self) -> &ICACHE_AUTOLOAD_SCT1_ADDR {
322        &self.icache_autoload_sct1_addr
323    }
324    #[doc = "0xb0 - ******* Description ***********"]
325    #[inline(always)]
326    pub const fn icache_autoload_sct1_size(&self) -> &ICACHE_AUTOLOAD_SCT1_SIZE {
327        &self.icache_autoload_sct1_size
328    }
329    #[doc = "0xb4 - ******* Description ***********"]
330    #[inline(always)]
331    pub const fn ibus_to_flash_start_vaddr(&self) -> &IBUS_TO_FLASH_START_VADDR {
332        &self.ibus_to_flash_start_vaddr
333    }
334    #[doc = "0xb8 - ******* Description ***********"]
335    #[inline(always)]
336    pub const fn ibus_to_flash_end_vaddr(&self) -> &IBUS_TO_FLASH_END_VADDR {
337        &self.ibus_to_flash_end_vaddr
338    }
339    #[doc = "0xbc - ******* Description ***********"]
340    #[inline(always)]
341    pub const fn dbus_to_flash_start_vaddr(&self) -> &DBUS_TO_FLASH_START_VADDR {
342        &self.dbus_to_flash_start_vaddr
343    }
344    #[doc = "0xc0 - ******* Description ***********"]
345    #[inline(always)]
346    pub const fn dbus_to_flash_end_vaddr(&self) -> &DBUS_TO_FLASH_END_VADDR {
347        &self.dbus_to_flash_end_vaddr
348    }
349    #[doc = "0xc4 - ******* Description ***********"]
350    #[inline(always)]
351    pub const fn cache_acs_cnt_clr(&self) -> &CACHE_ACS_CNT_CLR {
352        &self.cache_acs_cnt_clr
353    }
354    #[doc = "0xc8 - ******* Description ***********"]
355    #[inline(always)]
356    pub const fn ibus_acs_miss_cnt(&self) -> &IBUS_ACS_MISS_CNT {
357        &self.ibus_acs_miss_cnt
358    }
359    #[doc = "0xcc - ******* Description ***********"]
360    #[inline(always)]
361    pub const fn ibus_acs_cnt(&self) -> &IBUS_ACS_CNT {
362        &self.ibus_acs_cnt
363    }
364    #[doc = "0xd0 - ******* Description ***********"]
365    #[inline(always)]
366    pub const fn dbus_acs_flash_miss_cnt(&self) -> &DBUS_ACS_FLASH_MISS_CNT {
367        &self.dbus_acs_flash_miss_cnt
368    }
369    #[doc = "0xd4 - ******* Description ***********"]
370    #[inline(always)]
371    pub const fn dbus_acs_spiram_miss_cnt(&self) -> &DBUS_ACS_SPIRAM_MISS_CNT {
372        &self.dbus_acs_spiram_miss_cnt
373    }
374    #[doc = "0xd8 - ******* Description ***********"]
375    #[inline(always)]
376    pub const fn dbus_acs_cnt(&self) -> &DBUS_ACS_CNT {
377        &self.dbus_acs_cnt
378    }
379    #[doc = "0xdc - ******* Description ***********"]
380    #[inline(always)]
381    pub const fn cache_ilg_int_ena(&self) -> &CACHE_ILG_INT_ENA {
382        &self.cache_ilg_int_ena
383    }
384    #[doc = "0xe0 - ******* Description ***********"]
385    #[inline(always)]
386    pub const fn cache_ilg_int_clr(&self) -> &CACHE_ILG_INT_CLR {
387        &self.cache_ilg_int_clr
388    }
389    #[doc = "0xe4 - ******* Description ***********"]
390    #[inline(always)]
391    pub const fn cache_ilg_int_st(&self) -> &CACHE_ILG_INT_ST {
392        &self.cache_ilg_int_st
393    }
394    #[doc = "0xe8 - ******* Description ***********"]
395    #[inline(always)]
396    pub const fn core0_acs_cache_int_ena(&self) -> &CORE0_ACS_CACHE_INT_ENA {
397        &self.core0_acs_cache_int_ena
398    }
399    #[doc = "0xec - ******* Description ***********"]
400    #[inline(always)]
401    pub const fn core0_acs_cache_int_clr(&self) -> &CORE0_ACS_CACHE_INT_CLR {
402        &self.core0_acs_cache_int_clr
403    }
404    #[doc = "0xf0 - ******* Description ***********"]
405    #[inline(always)]
406    pub const fn core0_acs_cache_int_st(&self) -> &CORE0_ACS_CACHE_INT_ST {
407        &self.core0_acs_cache_int_st
408    }
409    #[doc = "0xf4 - ******* Description ***********"]
410    #[inline(always)]
411    pub const fn core1_acs_cache_int_ena(&self) -> &CORE1_ACS_CACHE_INT_ENA {
412        &self.core1_acs_cache_int_ena
413    }
414    #[doc = "0xf8 - ******* Description ***********"]
415    #[inline(always)]
416    pub const fn core1_acs_cache_int_clr(&self) -> &CORE1_ACS_CACHE_INT_CLR {
417        &self.core1_acs_cache_int_clr
418    }
419    #[doc = "0xfc - ******* Description ***********"]
420    #[inline(always)]
421    pub const fn core1_acs_cache_int_st(&self) -> &CORE1_ACS_CACHE_INT_ST {
422        &self.core1_acs_cache_int_st
423    }
424    #[doc = "0x100 - ******* Description ***********"]
425    #[inline(always)]
426    pub const fn core0_dbus_reject_st(&self) -> &CORE0_DBUS_REJECT_ST {
427        &self.core0_dbus_reject_st
428    }
429    #[doc = "0x104 - ******* Description ***********"]
430    #[inline(always)]
431    pub const fn core0_dbus_reject_vaddr(&self) -> &CORE0_DBUS_REJECT_VADDR {
432        &self.core0_dbus_reject_vaddr
433    }
434    #[doc = "0x108 - ******* Description ***********"]
435    #[inline(always)]
436    pub const fn core0_ibus_reject_st(&self) -> &CORE0_IBUS_REJECT_ST {
437        &self.core0_ibus_reject_st
438    }
439    #[doc = "0x10c - ******* Description ***********"]
440    #[inline(always)]
441    pub const fn core0_ibus_reject_vaddr(&self) -> &CORE0_IBUS_REJECT_VADDR {
442        &self.core0_ibus_reject_vaddr
443    }
444    #[doc = "0x110 - ******* Description ***********"]
445    #[inline(always)]
446    pub const fn core1_dbus_reject_st(&self) -> &CORE1_DBUS_REJECT_ST {
447        &self.core1_dbus_reject_st
448    }
449    #[doc = "0x114 - ******* Description ***********"]
450    #[inline(always)]
451    pub const fn core1_dbus_reject_vaddr(&self) -> &CORE1_DBUS_REJECT_VADDR {
452        &self.core1_dbus_reject_vaddr
453    }
454    #[doc = "0x118 - ******* Description ***********"]
455    #[inline(always)]
456    pub const fn core1_ibus_reject_st(&self) -> &CORE1_IBUS_REJECT_ST {
457        &self.core1_ibus_reject_st
458    }
459    #[doc = "0x11c - ******* Description ***********"]
460    #[inline(always)]
461    pub const fn core1_ibus_reject_vaddr(&self) -> &CORE1_IBUS_REJECT_VADDR {
462        &self.core1_ibus_reject_vaddr
463    }
464    #[doc = "0x120 - ******* Description ***********"]
465    #[inline(always)]
466    pub const fn cache_mmu_fault_content(&self) -> &CACHE_MMU_FAULT_CONTENT {
467        &self.cache_mmu_fault_content
468    }
469    #[doc = "0x124 - ******* Description ***********"]
470    #[inline(always)]
471    pub const fn cache_mmu_fault_vaddr(&self) -> &CACHE_MMU_FAULT_VADDR {
472        &self.cache_mmu_fault_vaddr
473    }
474    #[doc = "0x128 - ******* Description ***********"]
475    #[inline(always)]
476    pub const fn cache_wrap_around_ctrl(&self) -> &CACHE_WRAP_AROUND_CTRL {
477        &self.cache_wrap_around_ctrl
478    }
479    #[doc = "0x12c - ******* Description ***********"]
480    #[inline(always)]
481    pub const fn cache_mmu_power_ctrl(&self) -> &CACHE_MMU_POWER_CTRL {
482        &self.cache_mmu_power_ctrl
483    }
484    #[doc = "0x130 - ******* Description ***********"]
485    #[inline(always)]
486    pub const fn cache_state(&self) -> &CACHE_STATE {
487        &self.cache_state
488    }
489    #[doc = "0x134 - ******* Description ***********"]
490    #[inline(always)]
491    pub const fn cache_encrypt_decrypt_record_disable(
492        &self,
493    ) -> &CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE {
494        &self.cache_encrypt_decrypt_record_disable
495    }
496    #[doc = "0x138 - ******* Description ***********"]
497    #[inline(always)]
498    pub const fn cache_encrypt_decrypt_clk_force_on(&self) -> &CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON {
499        &self.cache_encrypt_decrypt_clk_force_on
500    }
501    #[doc = "0x13c - ******* Description ***********"]
502    #[inline(always)]
503    pub const fn cache_bridge_arbiter_ctrl(&self) -> &CACHE_BRIDGE_ARBITER_CTRL {
504        &self.cache_bridge_arbiter_ctrl
505    }
506    #[doc = "0x140 - ******* Description ***********"]
507    #[inline(always)]
508    pub const fn cache_preload_int_ctrl(&self) -> &CACHE_PRELOAD_INT_CTRL {
509        &self.cache_preload_int_ctrl
510    }
511    #[doc = "0x144 - ******* Description ***********"]
512    #[inline(always)]
513    pub const fn cache_sync_int_ctrl(&self) -> &CACHE_SYNC_INT_CTRL {
514        &self.cache_sync_int_ctrl
515    }
516    #[doc = "0x148 - ******* Description ***********"]
517    #[inline(always)]
518    pub const fn cache_mmu_owner(&self) -> &CACHE_MMU_OWNER {
519        &self.cache_mmu_owner
520    }
521    #[doc = "0x14c - ******* Description ***********"]
522    #[inline(always)]
523    pub const fn cache_conf_misc(&self) -> &CACHE_CONF_MISC {
524        &self.cache_conf_misc
525    }
526    #[doc = "0x150 - ******* Description ***********"]
527    #[inline(always)]
528    pub const fn dcache_freeze(&self) -> &DCACHE_FREEZE {
529        &self.dcache_freeze
530    }
531    #[doc = "0x154 - ******* Description ***********"]
532    #[inline(always)]
533    pub const fn icache_freeze(&self) -> &ICACHE_FREEZE {
534        &self.icache_freeze
535    }
536    #[doc = "0x158 - ******* Description ***********"]
537    #[inline(always)]
538    pub const fn icache_atomic_operate_ena(&self) -> &ICACHE_ATOMIC_OPERATE_ENA {
539        &self.icache_atomic_operate_ena
540    }
541    #[doc = "0x15c - ******* Description ***********"]
542    #[inline(always)]
543    pub const fn dcache_atomic_operate_ena(&self) -> &DCACHE_ATOMIC_OPERATE_ENA {
544        &self.dcache_atomic_operate_ena
545    }
546    #[doc = "0x160 - ******* Description ***********"]
547    #[inline(always)]
548    pub const fn cache_request(&self) -> &CACHE_REQUEST {
549        &self.cache_request
550    }
551    #[doc = "0x164 - ******* Description ***********"]
552    #[inline(always)]
553    pub const fn clock_gate(&self) -> &CLOCK_GATE {
554        &self.clock_gate
555    }
556    #[doc = "0x180 - ******* Description ***********"]
557    #[inline(always)]
558    pub const fn cache_tag_object_ctrl(&self) -> &CACHE_TAG_OBJECT_CTRL {
559        &self.cache_tag_object_ctrl
560    }
561    #[doc = "0x184 - ******* Description ***********"]
562    #[inline(always)]
563    pub const fn cache_tag_way_object(&self) -> &CACHE_TAG_WAY_OBJECT {
564        &self.cache_tag_way_object
565    }
566    #[doc = "0x188 - ******* Description ***********"]
567    #[inline(always)]
568    pub const fn cache_vaddr(&self) -> &CACHE_VADDR {
569        &self.cache_vaddr
570    }
571    #[doc = "0x18c - ******* Description ***********"]
572    #[inline(always)]
573    pub const fn cache_tag_content(&self) -> &CACHE_TAG_CONTENT {
574        &self.cache_tag_content
575    }
576    #[doc = "0x3fc - ******* Description ***********"]
577    #[inline(always)]
578    pub const fn date(&self) -> &DATE {
579        &self.date
580    }
581}
582#[doc = "DCACHE_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_ctrl`] module"]
583pub type DCACHE_CTRL = crate::Reg<dcache_ctrl::DCACHE_CTRL_SPEC>;
584#[doc = "******* Description ***********"]
585pub mod dcache_ctrl;
586#[doc = "DCACHE_CTRL1 (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_ctrl1`] module"]
587pub type DCACHE_CTRL1 = crate::Reg<dcache_ctrl1::DCACHE_CTRL1_SPEC>;
588#[doc = "******* Description ***********"]
589pub mod dcache_ctrl1;
590#[doc = "DCACHE_TAG_POWER_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_tag_power_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_tag_power_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_tag_power_ctrl`] module"]
591pub type DCACHE_TAG_POWER_CTRL = crate::Reg<dcache_tag_power_ctrl::DCACHE_TAG_POWER_CTRL_SPEC>;
592#[doc = "******* Description ***********"]
593pub mod dcache_tag_power_ctrl;
594#[doc = "DCACHE_PRELOCK_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_prelock_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_prelock_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_prelock_ctrl`] module"]
595pub type DCACHE_PRELOCK_CTRL = crate::Reg<dcache_prelock_ctrl::DCACHE_PRELOCK_CTRL_SPEC>;
596#[doc = "******* Description ***********"]
597pub mod dcache_prelock_ctrl;
598#[doc = "DCACHE_PRELOCK_SCT0_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_prelock_sct0_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_prelock_sct0_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_prelock_sct0_addr`] module"]
599pub type DCACHE_PRELOCK_SCT0_ADDR =
600    crate::Reg<dcache_prelock_sct0_addr::DCACHE_PRELOCK_SCT0_ADDR_SPEC>;
601#[doc = "******* Description ***********"]
602pub mod dcache_prelock_sct0_addr;
603#[doc = "DCACHE_PRELOCK_SCT1_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_prelock_sct1_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_prelock_sct1_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_prelock_sct1_addr`] module"]
604pub type DCACHE_PRELOCK_SCT1_ADDR =
605    crate::Reg<dcache_prelock_sct1_addr::DCACHE_PRELOCK_SCT1_ADDR_SPEC>;
606#[doc = "******* Description ***********"]
607pub mod dcache_prelock_sct1_addr;
608#[doc = "DCACHE_PRELOCK_SCT_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_prelock_sct_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_prelock_sct_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_prelock_sct_size`] module"]
609pub type DCACHE_PRELOCK_SCT_SIZE =
610    crate::Reg<dcache_prelock_sct_size::DCACHE_PRELOCK_SCT_SIZE_SPEC>;
611#[doc = "******* Description ***********"]
612pub mod dcache_prelock_sct_size;
613#[doc = "DCACHE_LOCK_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_lock_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_lock_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_lock_ctrl`] module"]
614pub type DCACHE_LOCK_CTRL = crate::Reg<dcache_lock_ctrl::DCACHE_LOCK_CTRL_SPEC>;
615#[doc = "******* Description ***********"]
616pub mod dcache_lock_ctrl;
617#[doc = "DCACHE_LOCK_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_lock_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_lock_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_lock_addr`] module"]
618pub type DCACHE_LOCK_ADDR = crate::Reg<dcache_lock_addr::DCACHE_LOCK_ADDR_SPEC>;
619#[doc = "******* Description ***********"]
620pub mod dcache_lock_addr;
621#[doc = "DCACHE_LOCK_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_lock_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_lock_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_lock_size`] module"]
622pub type DCACHE_LOCK_SIZE = crate::Reg<dcache_lock_size::DCACHE_LOCK_SIZE_SPEC>;
623#[doc = "******* Description ***********"]
624pub mod dcache_lock_size;
625#[doc = "DCACHE_SYNC_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_sync_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_sync_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_sync_ctrl`] module"]
626pub type DCACHE_SYNC_CTRL = crate::Reg<dcache_sync_ctrl::DCACHE_SYNC_CTRL_SPEC>;
627#[doc = "******* Description ***********"]
628pub mod dcache_sync_ctrl;
629#[doc = "DCACHE_SYNC_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_sync_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_sync_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_sync_addr`] module"]
630pub type DCACHE_SYNC_ADDR = crate::Reg<dcache_sync_addr::DCACHE_SYNC_ADDR_SPEC>;
631#[doc = "******* Description ***********"]
632pub mod dcache_sync_addr;
633#[doc = "DCACHE_SYNC_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_sync_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_sync_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_sync_size`] module"]
634pub type DCACHE_SYNC_SIZE = crate::Reg<dcache_sync_size::DCACHE_SYNC_SIZE_SPEC>;
635#[doc = "******* Description ***********"]
636pub mod dcache_sync_size;
637#[doc = "DCACHE_OCCUPY_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_occupy_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_occupy_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_occupy_ctrl`] module"]
638pub type DCACHE_OCCUPY_CTRL = crate::Reg<dcache_occupy_ctrl::DCACHE_OCCUPY_CTRL_SPEC>;
639#[doc = "******* Description ***********"]
640pub mod dcache_occupy_ctrl;
641#[doc = "DCACHE_OCCUPY_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_occupy_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_occupy_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_occupy_addr`] module"]
642pub type DCACHE_OCCUPY_ADDR = crate::Reg<dcache_occupy_addr::DCACHE_OCCUPY_ADDR_SPEC>;
643#[doc = "******* Description ***********"]
644pub mod dcache_occupy_addr;
645#[doc = "DCACHE_OCCUPY_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_occupy_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_occupy_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_occupy_size`] module"]
646pub type DCACHE_OCCUPY_SIZE = crate::Reg<dcache_occupy_size::DCACHE_OCCUPY_SIZE_SPEC>;
647#[doc = "******* Description ***********"]
648pub mod dcache_occupy_size;
649#[doc = "DCACHE_PRELOAD_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_preload_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_preload_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_preload_ctrl`] module"]
650pub type DCACHE_PRELOAD_CTRL = crate::Reg<dcache_preload_ctrl::DCACHE_PRELOAD_CTRL_SPEC>;
651#[doc = "******* Description ***********"]
652pub mod dcache_preload_ctrl;
653#[doc = "DCACHE_PRELOAD_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_preload_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_preload_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_preload_addr`] module"]
654pub type DCACHE_PRELOAD_ADDR = crate::Reg<dcache_preload_addr::DCACHE_PRELOAD_ADDR_SPEC>;
655#[doc = "******* Description ***********"]
656pub mod dcache_preload_addr;
657#[doc = "DCACHE_PRELOAD_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_preload_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_preload_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_preload_size`] module"]
658pub type DCACHE_PRELOAD_SIZE = crate::Reg<dcache_preload_size::DCACHE_PRELOAD_SIZE_SPEC>;
659#[doc = "******* Description ***********"]
660pub mod dcache_preload_size;
661#[doc = "DCACHE_AUTOLOAD_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_autoload_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_autoload_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_autoload_ctrl`] module"]
662pub type DCACHE_AUTOLOAD_CTRL = crate::Reg<dcache_autoload_ctrl::DCACHE_AUTOLOAD_CTRL_SPEC>;
663#[doc = "******* Description ***********"]
664pub mod dcache_autoload_ctrl;
665#[doc = "DCACHE_AUTOLOAD_SCT0_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_autoload_sct0_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_autoload_sct0_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_autoload_sct0_addr`] module"]
666pub type DCACHE_AUTOLOAD_SCT0_ADDR =
667    crate::Reg<dcache_autoload_sct0_addr::DCACHE_AUTOLOAD_SCT0_ADDR_SPEC>;
668#[doc = "******* Description ***********"]
669pub mod dcache_autoload_sct0_addr;
670#[doc = "DCACHE_AUTOLOAD_SCT0_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_autoload_sct0_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_autoload_sct0_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_autoload_sct0_size`] module"]
671pub type DCACHE_AUTOLOAD_SCT0_SIZE =
672    crate::Reg<dcache_autoload_sct0_size::DCACHE_AUTOLOAD_SCT0_SIZE_SPEC>;
673#[doc = "******* Description ***********"]
674pub mod dcache_autoload_sct0_size;
675#[doc = "DCACHE_AUTOLOAD_SCT1_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_autoload_sct1_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_autoload_sct1_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_autoload_sct1_addr`] module"]
676pub type DCACHE_AUTOLOAD_SCT1_ADDR =
677    crate::Reg<dcache_autoload_sct1_addr::DCACHE_AUTOLOAD_SCT1_ADDR_SPEC>;
678#[doc = "******* Description ***********"]
679pub mod dcache_autoload_sct1_addr;
680#[doc = "DCACHE_AUTOLOAD_SCT1_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_autoload_sct1_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_autoload_sct1_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_autoload_sct1_size`] module"]
681pub type DCACHE_AUTOLOAD_SCT1_SIZE =
682    crate::Reg<dcache_autoload_sct1_size::DCACHE_AUTOLOAD_SCT1_SIZE_SPEC>;
683#[doc = "******* Description ***********"]
684pub mod dcache_autoload_sct1_size;
685#[doc = "ICACHE_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_ctrl`] module"]
686pub type ICACHE_CTRL = crate::Reg<icache_ctrl::ICACHE_CTRL_SPEC>;
687#[doc = "******* Description ***********"]
688pub mod icache_ctrl;
689#[doc = "ICACHE_CTRL1 (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_ctrl1`] module"]
690pub type ICACHE_CTRL1 = crate::Reg<icache_ctrl1::ICACHE_CTRL1_SPEC>;
691#[doc = "******* Description ***********"]
692pub mod icache_ctrl1;
693#[doc = "ICACHE_TAG_POWER_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_tag_power_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_tag_power_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_tag_power_ctrl`] module"]
694pub type ICACHE_TAG_POWER_CTRL = crate::Reg<icache_tag_power_ctrl::ICACHE_TAG_POWER_CTRL_SPEC>;
695#[doc = "******* Description ***********"]
696pub mod icache_tag_power_ctrl;
697#[doc = "ICACHE_PRELOCK_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_prelock_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_prelock_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_prelock_ctrl`] module"]
698pub type ICACHE_PRELOCK_CTRL = crate::Reg<icache_prelock_ctrl::ICACHE_PRELOCK_CTRL_SPEC>;
699#[doc = "******* Description ***********"]
700pub mod icache_prelock_ctrl;
701#[doc = "ICACHE_PRELOCK_SCT0_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_prelock_sct0_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_prelock_sct0_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_prelock_sct0_addr`] module"]
702pub type ICACHE_PRELOCK_SCT0_ADDR =
703    crate::Reg<icache_prelock_sct0_addr::ICACHE_PRELOCK_SCT0_ADDR_SPEC>;
704#[doc = "******* Description ***********"]
705pub mod icache_prelock_sct0_addr;
706#[doc = "ICACHE_PRELOCK_SCT1_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_prelock_sct1_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_prelock_sct1_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_prelock_sct1_addr`] module"]
707pub type ICACHE_PRELOCK_SCT1_ADDR =
708    crate::Reg<icache_prelock_sct1_addr::ICACHE_PRELOCK_SCT1_ADDR_SPEC>;
709#[doc = "******* Description ***********"]
710pub mod icache_prelock_sct1_addr;
711#[doc = "ICACHE_PRELOCK_SCT_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_prelock_sct_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_prelock_sct_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_prelock_sct_size`] module"]
712pub type ICACHE_PRELOCK_SCT_SIZE =
713    crate::Reg<icache_prelock_sct_size::ICACHE_PRELOCK_SCT_SIZE_SPEC>;
714#[doc = "******* Description ***********"]
715pub mod icache_prelock_sct_size;
716#[doc = "ICACHE_LOCK_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_lock_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_lock_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_lock_ctrl`] module"]
717pub type ICACHE_LOCK_CTRL = crate::Reg<icache_lock_ctrl::ICACHE_LOCK_CTRL_SPEC>;
718#[doc = "******* Description ***********"]
719pub mod icache_lock_ctrl;
720#[doc = "ICACHE_LOCK_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_lock_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_lock_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_lock_addr`] module"]
721pub type ICACHE_LOCK_ADDR = crate::Reg<icache_lock_addr::ICACHE_LOCK_ADDR_SPEC>;
722#[doc = "******* Description ***********"]
723pub mod icache_lock_addr;
724#[doc = "ICACHE_LOCK_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_lock_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_lock_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_lock_size`] module"]
725pub type ICACHE_LOCK_SIZE = crate::Reg<icache_lock_size::ICACHE_LOCK_SIZE_SPEC>;
726#[doc = "******* Description ***********"]
727pub mod icache_lock_size;
728#[doc = "ICACHE_SYNC_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_sync_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_sync_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_sync_ctrl`] module"]
729pub type ICACHE_SYNC_CTRL = crate::Reg<icache_sync_ctrl::ICACHE_SYNC_CTRL_SPEC>;
730#[doc = "******* Description ***********"]
731pub mod icache_sync_ctrl;
732#[doc = "ICACHE_SYNC_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_sync_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_sync_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_sync_addr`] module"]
733pub type ICACHE_SYNC_ADDR = crate::Reg<icache_sync_addr::ICACHE_SYNC_ADDR_SPEC>;
734#[doc = "******* Description ***********"]
735pub mod icache_sync_addr;
736#[doc = "ICACHE_SYNC_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_sync_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_sync_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_sync_size`] module"]
737pub type ICACHE_SYNC_SIZE = crate::Reg<icache_sync_size::ICACHE_SYNC_SIZE_SPEC>;
738#[doc = "******* Description ***********"]
739pub mod icache_sync_size;
740#[doc = "ICACHE_PRELOAD_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_preload_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_preload_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_preload_ctrl`] module"]
741pub type ICACHE_PRELOAD_CTRL = crate::Reg<icache_preload_ctrl::ICACHE_PRELOAD_CTRL_SPEC>;
742#[doc = "******* Description ***********"]
743pub mod icache_preload_ctrl;
744#[doc = "ICACHE_PRELOAD_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_preload_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_preload_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_preload_addr`] module"]
745pub type ICACHE_PRELOAD_ADDR = crate::Reg<icache_preload_addr::ICACHE_PRELOAD_ADDR_SPEC>;
746#[doc = "******* Description ***********"]
747pub mod icache_preload_addr;
748#[doc = "ICACHE_PRELOAD_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_preload_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_preload_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_preload_size`] module"]
749pub type ICACHE_PRELOAD_SIZE = crate::Reg<icache_preload_size::ICACHE_PRELOAD_SIZE_SPEC>;
750#[doc = "******* Description ***********"]
751pub mod icache_preload_size;
752#[doc = "ICACHE_AUTOLOAD_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_autoload_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_autoload_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_autoload_ctrl`] module"]
753pub type ICACHE_AUTOLOAD_CTRL = crate::Reg<icache_autoload_ctrl::ICACHE_AUTOLOAD_CTRL_SPEC>;
754#[doc = "******* Description ***********"]
755pub mod icache_autoload_ctrl;
756#[doc = "ICACHE_AUTOLOAD_SCT0_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_autoload_sct0_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_autoload_sct0_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_autoload_sct0_addr`] module"]
757pub type ICACHE_AUTOLOAD_SCT0_ADDR =
758    crate::Reg<icache_autoload_sct0_addr::ICACHE_AUTOLOAD_SCT0_ADDR_SPEC>;
759#[doc = "******* Description ***********"]
760pub mod icache_autoload_sct0_addr;
761#[doc = "ICACHE_AUTOLOAD_SCT0_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_autoload_sct0_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_autoload_sct0_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_autoload_sct0_size`] module"]
762pub type ICACHE_AUTOLOAD_SCT0_SIZE =
763    crate::Reg<icache_autoload_sct0_size::ICACHE_AUTOLOAD_SCT0_SIZE_SPEC>;
764#[doc = "******* Description ***********"]
765pub mod icache_autoload_sct0_size;
766#[doc = "ICACHE_AUTOLOAD_SCT1_ADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_autoload_sct1_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_autoload_sct1_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_autoload_sct1_addr`] module"]
767pub type ICACHE_AUTOLOAD_SCT1_ADDR =
768    crate::Reg<icache_autoload_sct1_addr::ICACHE_AUTOLOAD_SCT1_ADDR_SPEC>;
769#[doc = "******* Description ***********"]
770pub mod icache_autoload_sct1_addr;
771#[doc = "ICACHE_AUTOLOAD_SCT1_SIZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_autoload_sct1_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_autoload_sct1_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_autoload_sct1_size`] module"]
772pub type ICACHE_AUTOLOAD_SCT1_SIZE =
773    crate::Reg<icache_autoload_sct1_size::ICACHE_AUTOLOAD_SCT1_SIZE_SPEC>;
774#[doc = "******* Description ***********"]
775pub mod icache_autoload_sct1_size;
776#[doc = "IBUS_TO_FLASH_START_VADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus_to_flash_start_vaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibus_to_flash_start_vaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus_to_flash_start_vaddr`] module"]
777pub type IBUS_TO_FLASH_START_VADDR =
778    crate::Reg<ibus_to_flash_start_vaddr::IBUS_TO_FLASH_START_VADDR_SPEC>;
779#[doc = "******* Description ***********"]
780pub mod ibus_to_flash_start_vaddr;
781#[doc = "IBUS_TO_FLASH_END_VADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus_to_flash_end_vaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibus_to_flash_end_vaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus_to_flash_end_vaddr`] module"]
782pub type IBUS_TO_FLASH_END_VADDR =
783    crate::Reg<ibus_to_flash_end_vaddr::IBUS_TO_FLASH_END_VADDR_SPEC>;
784#[doc = "******* Description ***********"]
785pub mod ibus_to_flash_end_vaddr;
786#[doc = "DBUS_TO_FLASH_START_VADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus_to_flash_start_vaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbus_to_flash_start_vaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus_to_flash_start_vaddr`] module"]
787pub type DBUS_TO_FLASH_START_VADDR =
788    crate::Reg<dbus_to_flash_start_vaddr::DBUS_TO_FLASH_START_VADDR_SPEC>;
789#[doc = "******* Description ***********"]
790pub mod dbus_to_flash_start_vaddr;
791#[doc = "DBUS_TO_FLASH_END_VADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus_to_flash_end_vaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbus_to_flash_end_vaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus_to_flash_end_vaddr`] module"]
792pub type DBUS_TO_FLASH_END_VADDR =
793    crate::Reg<dbus_to_flash_end_vaddr::DBUS_TO_FLASH_END_VADDR_SPEC>;
794#[doc = "******* Description ***********"]
795pub mod dbus_to_flash_end_vaddr;
796#[doc = "CACHE_ACS_CNT_CLR (w) register accessor: ******* Description ***********\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_acs_cnt_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_acs_cnt_clr`] module"]
797pub type CACHE_ACS_CNT_CLR = crate::Reg<cache_acs_cnt_clr::CACHE_ACS_CNT_CLR_SPEC>;
798#[doc = "******* Description ***********"]
799pub mod cache_acs_cnt_clr;
800#[doc = "IBUS_ACS_MISS_CNT (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus_acs_miss_cnt`] module"]
801pub type IBUS_ACS_MISS_CNT = crate::Reg<ibus_acs_miss_cnt::IBUS_ACS_MISS_CNT_SPEC>;
802#[doc = "******* Description ***********"]
803pub mod ibus_acs_miss_cnt;
804#[doc = "IBUS_ACS_CNT (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus_acs_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus_acs_cnt`] module"]
805pub type IBUS_ACS_CNT = crate::Reg<ibus_acs_cnt::IBUS_ACS_CNT_SPEC>;
806#[doc = "******* Description ***********"]
807pub mod ibus_acs_cnt;
808#[doc = "DBUS_ACS_FLASH_MISS_CNT (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus_acs_flash_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus_acs_flash_miss_cnt`] module"]
809pub type DBUS_ACS_FLASH_MISS_CNT =
810    crate::Reg<dbus_acs_flash_miss_cnt::DBUS_ACS_FLASH_MISS_CNT_SPEC>;
811#[doc = "******* Description ***********"]
812pub mod dbus_acs_flash_miss_cnt;
813#[doc = "DBUS_ACS_SPIRAM_MISS_CNT (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus_acs_spiram_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus_acs_spiram_miss_cnt`] module"]
814pub type DBUS_ACS_SPIRAM_MISS_CNT =
815    crate::Reg<dbus_acs_spiram_miss_cnt::DBUS_ACS_SPIRAM_MISS_CNT_SPEC>;
816#[doc = "******* Description ***********"]
817pub mod dbus_acs_spiram_miss_cnt;
818#[doc = "DBUS_ACS_CNT (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus_acs_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus_acs_cnt`] module"]
819pub type DBUS_ACS_CNT = crate::Reg<dbus_acs_cnt::DBUS_ACS_CNT_SPEC>;
820#[doc = "******* Description ***********"]
821pub mod dbus_acs_cnt;
822#[doc = "CACHE_ILG_INT_ENA (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_ilg_int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_ilg_int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_ilg_int_ena`] module"]
823pub type CACHE_ILG_INT_ENA = crate::Reg<cache_ilg_int_ena::CACHE_ILG_INT_ENA_SPEC>;
824#[doc = "******* Description ***********"]
825pub mod cache_ilg_int_ena;
826#[doc = "CACHE_ILG_INT_CLR (w) register accessor: ******* Description ***********\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_ilg_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_ilg_int_clr`] module"]
827pub type CACHE_ILG_INT_CLR = crate::Reg<cache_ilg_int_clr::CACHE_ILG_INT_CLR_SPEC>;
828#[doc = "******* Description ***********"]
829pub mod cache_ilg_int_clr;
830#[doc = "CACHE_ILG_INT_ST (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_ilg_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_ilg_int_st`] module"]
831pub type CACHE_ILG_INT_ST = crate::Reg<cache_ilg_int_st::CACHE_ILG_INT_ST_SPEC>;
832#[doc = "******* Description ***********"]
833pub mod cache_ilg_int_st;
834#[doc = "CORE0_ACS_CACHE_INT_ENA (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_acs_cache_int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core0_acs_cache_int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core0_acs_cache_int_ena`] module"]
835pub type CORE0_ACS_CACHE_INT_ENA =
836    crate::Reg<core0_acs_cache_int_ena::CORE0_ACS_CACHE_INT_ENA_SPEC>;
837#[doc = "******* Description ***********"]
838pub mod core0_acs_cache_int_ena;
839#[doc = "CORE0_ACS_CACHE_INT_CLR (w) register accessor: ******* Description ***********\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core0_acs_cache_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core0_acs_cache_int_clr`] module"]
840pub type CORE0_ACS_CACHE_INT_CLR =
841    crate::Reg<core0_acs_cache_int_clr::CORE0_ACS_CACHE_INT_CLR_SPEC>;
842#[doc = "******* Description ***********"]
843pub mod core0_acs_cache_int_clr;
844#[doc = "CORE0_ACS_CACHE_INT_ST (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_acs_cache_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core0_acs_cache_int_st`] module"]
845pub type CORE0_ACS_CACHE_INT_ST = crate::Reg<core0_acs_cache_int_st::CORE0_ACS_CACHE_INT_ST_SPEC>;
846#[doc = "******* Description ***********"]
847pub mod core0_acs_cache_int_st;
848#[doc = "CORE1_ACS_CACHE_INT_ENA (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_acs_cache_int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core1_acs_cache_int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core1_acs_cache_int_ena`] module"]
849pub type CORE1_ACS_CACHE_INT_ENA =
850    crate::Reg<core1_acs_cache_int_ena::CORE1_ACS_CACHE_INT_ENA_SPEC>;
851#[doc = "******* Description ***********"]
852pub mod core1_acs_cache_int_ena;
853#[doc = "CORE1_ACS_CACHE_INT_CLR (w) register accessor: ******* Description ***********\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core1_acs_cache_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core1_acs_cache_int_clr`] module"]
854pub type CORE1_ACS_CACHE_INT_CLR =
855    crate::Reg<core1_acs_cache_int_clr::CORE1_ACS_CACHE_INT_CLR_SPEC>;
856#[doc = "******* Description ***********"]
857pub mod core1_acs_cache_int_clr;
858#[doc = "CORE1_ACS_CACHE_INT_ST (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_acs_cache_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core1_acs_cache_int_st`] module"]
859pub type CORE1_ACS_CACHE_INT_ST = crate::Reg<core1_acs_cache_int_st::CORE1_ACS_CACHE_INT_ST_SPEC>;
860#[doc = "******* Description ***********"]
861pub mod core1_acs_cache_int_st;
862#[doc = "CORE0_DBUS_REJECT_ST (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_dbus_reject_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core0_dbus_reject_st`] module"]
863pub type CORE0_DBUS_REJECT_ST = crate::Reg<core0_dbus_reject_st::CORE0_DBUS_REJECT_ST_SPEC>;
864#[doc = "******* Description ***********"]
865pub mod core0_dbus_reject_st;
866#[doc = "CORE0_DBUS_REJECT_VADDR (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_dbus_reject_vaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core0_dbus_reject_vaddr`] module"]
867pub type CORE0_DBUS_REJECT_VADDR =
868    crate::Reg<core0_dbus_reject_vaddr::CORE0_DBUS_REJECT_VADDR_SPEC>;
869#[doc = "******* Description ***********"]
870pub mod core0_dbus_reject_vaddr;
871#[doc = "CORE0_IBUS_REJECT_ST (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_ibus_reject_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core0_ibus_reject_st`] module"]
872pub type CORE0_IBUS_REJECT_ST = crate::Reg<core0_ibus_reject_st::CORE0_IBUS_REJECT_ST_SPEC>;
873#[doc = "******* Description ***********"]
874pub mod core0_ibus_reject_st;
875#[doc = "CORE0_IBUS_REJECT_VADDR (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_ibus_reject_vaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core0_ibus_reject_vaddr`] module"]
876pub type CORE0_IBUS_REJECT_VADDR =
877    crate::Reg<core0_ibus_reject_vaddr::CORE0_IBUS_REJECT_VADDR_SPEC>;
878#[doc = "******* Description ***********"]
879pub mod core0_ibus_reject_vaddr;
880#[doc = "CORE1_DBUS_REJECT_ST (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_dbus_reject_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core1_dbus_reject_st`] module"]
881pub type CORE1_DBUS_REJECT_ST = crate::Reg<core1_dbus_reject_st::CORE1_DBUS_REJECT_ST_SPEC>;
882#[doc = "******* Description ***********"]
883pub mod core1_dbus_reject_st;
884#[doc = "CORE1_DBUS_REJECT_VADDR (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_dbus_reject_vaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core1_dbus_reject_vaddr`] module"]
885pub type CORE1_DBUS_REJECT_VADDR =
886    crate::Reg<core1_dbus_reject_vaddr::CORE1_DBUS_REJECT_VADDR_SPEC>;
887#[doc = "******* Description ***********"]
888pub mod core1_dbus_reject_vaddr;
889#[doc = "CORE1_IBUS_REJECT_ST (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_ibus_reject_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core1_ibus_reject_st`] module"]
890pub type CORE1_IBUS_REJECT_ST = crate::Reg<core1_ibus_reject_st::CORE1_IBUS_REJECT_ST_SPEC>;
891#[doc = "******* Description ***********"]
892pub mod core1_ibus_reject_st;
893#[doc = "CORE1_IBUS_REJECT_VADDR (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_ibus_reject_vaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core1_ibus_reject_vaddr`] module"]
894pub type CORE1_IBUS_REJECT_VADDR =
895    crate::Reg<core1_ibus_reject_vaddr::CORE1_IBUS_REJECT_VADDR_SPEC>;
896#[doc = "******* Description ***********"]
897pub mod core1_ibus_reject_vaddr;
898#[doc = "CACHE_MMU_FAULT_CONTENT (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_fault_content::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_mmu_fault_content`] module"]
899pub type CACHE_MMU_FAULT_CONTENT =
900    crate::Reg<cache_mmu_fault_content::CACHE_MMU_FAULT_CONTENT_SPEC>;
901#[doc = "******* Description ***********"]
902pub mod cache_mmu_fault_content;
903#[doc = "CACHE_MMU_FAULT_VADDR (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_fault_vaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_mmu_fault_vaddr`] module"]
904pub type CACHE_MMU_FAULT_VADDR = crate::Reg<cache_mmu_fault_vaddr::CACHE_MMU_FAULT_VADDR_SPEC>;
905#[doc = "******* Description ***********"]
906pub mod cache_mmu_fault_vaddr;
907#[doc = "CACHE_WRAP_AROUND_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_wrap_around_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_wrap_around_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_wrap_around_ctrl`] module"]
908pub type CACHE_WRAP_AROUND_CTRL = crate::Reg<cache_wrap_around_ctrl::CACHE_WRAP_AROUND_CTRL_SPEC>;
909#[doc = "******* Description ***********"]
910pub mod cache_wrap_around_ctrl;
911#[doc = "CACHE_MMU_POWER_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_power_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_mmu_power_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_mmu_power_ctrl`] module"]
912pub type CACHE_MMU_POWER_CTRL = crate::Reg<cache_mmu_power_ctrl::CACHE_MMU_POWER_CTRL_SPEC>;
913#[doc = "******* Description ***********"]
914pub mod cache_mmu_power_ctrl;
915#[doc = "CACHE_STATE (r) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_state`] module"]
916pub type CACHE_STATE = crate::Reg<cache_state::CACHE_STATE_SPEC>;
917#[doc = "******* Description ***********"]
918pub mod cache_state;
919#[doc = "CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_encrypt_decrypt_record_disable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_encrypt_decrypt_record_disable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_encrypt_decrypt_record_disable`] module"]
920pub type CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE =
921    crate::Reg<cache_encrypt_decrypt_record_disable::CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC>;
922#[doc = "******* Description ***********"]
923pub mod cache_encrypt_decrypt_record_disable;
924#[doc = "CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_encrypt_decrypt_clk_force_on::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_encrypt_decrypt_clk_force_on::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_encrypt_decrypt_clk_force_on`] module"]
925pub type CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON =
926    crate::Reg<cache_encrypt_decrypt_clk_force_on::CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC>;
927#[doc = "******* Description ***********"]
928pub mod cache_encrypt_decrypt_clk_force_on;
929#[doc = "CACHE_BRIDGE_ARBITER_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_bridge_arbiter_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_bridge_arbiter_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_bridge_arbiter_ctrl`] module"]
930pub type CACHE_BRIDGE_ARBITER_CTRL =
931    crate::Reg<cache_bridge_arbiter_ctrl::CACHE_BRIDGE_ARBITER_CTRL_SPEC>;
932#[doc = "******* Description ***********"]
933pub mod cache_bridge_arbiter_ctrl;
934#[doc = "CACHE_PRELOAD_INT_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_preload_int_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_preload_int_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_preload_int_ctrl`] module"]
935pub type CACHE_PRELOAD_INT_CTRL = crate::Reg<cache_preload_int_ctrl::CACHE_PRELOAD_INT_CTRL_SPEC>;
936#[doc = "******* Description ***********"]
937pub mod cache_preload_int_ctrl;
938#[doc = "CACHE_SYNC_INT_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_sync_int_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_sync_int_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_sync_int_ctrl`] module"]
939pub type CACHE_SYNC_INT_CTRL = crate::Reg<cache_sync_int_ctrl::CACHE_SYNC_INT_CTRL_SPEC>;
940#[doc = "******* Description ***********"]
941pub mod cache_sync_int_ctrl;
942#[doc = "CACHE_MMU_OWNER (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_owner::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_mmu_owner::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_mmu_owner`] module"]
943pub type CACHE_MMU_OWNER = crate::Reg<cache_mmu_owner::CACHE_MMU_OWNER_SPEC>;
944#[doc = "******* Description ***********"]
945pub mod cache_mmu_owner;
946#[doc = "CACHE_CONF_MISC (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_conf_misc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_conf_misc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_conf_misc`] module"]
947pub type CACHE_CONF_MISC = crate::Reg<cache_conf_misc::CACHE_CONF_MISC_SPEC>;
948#[doc = "******* Description ***********"]
949pub mod cache_conf_misc;
950#[doc = "DCACHE_FREEZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_freeze::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_freeze::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_freeze`] module"]
951pub type DCACHE_FREEZE = crate::Reg<dcache_freeze::DCACHE_FREEZE_SPEC>;
952#[doc = "******* Description ***********"]
953pub mod dcache_freeze;
954#[doc = "ICACHE_FREEZE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_freeze::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_freeze::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_freeze`] module"]
955pub type ICACHE_FREEZE = crate::Reg<icache_freeze::ICACHE_FREEZE_SPEC>;
956#[doc = "******* Description ***********"]
957pub mod icache_freeze;
958#[doc = "ICACHE_ATOMIC_OPERATE_ENA (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_atomic_operate_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_atomic_operate_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icache_atomic_operate_ena`] module"]
959pub type ICACHE_ATOMIC_OPERATE_ENA =
960    crate::Reg<icache_atomic_operate_ena::ICACHE_ATOMIC_OPERATE_ENA_SPEC>;
961#[doc = "******* Description ***********"]
962pub mod icache_atomic_operate_ena;
963#[doc = "DCACHE_ATOMIC_OPERATE_ENA (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_atomic_operate_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_atomic_operate_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcache_atomic_operate_ena`] module"]
964pub type DCACHE_ATOMIC_OPERATE_ENA =
965    crate::Reg<dcache_atomic_operate_ena::DCACHE_ATOMIC_OPERATE_ENA_SPEC>;
966#[doc = "******* Description ***********"]
967pub mod dcache_atomic_operate_ena;
968#[doc = "CACHE_REQUEST (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_request::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_request::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_request`] module"]
969pub type CACHE_REQUEST = crate::Reg<cache_request::CACHE_REQUEST_SPEC>;
970#[doc = "******* Description ***********"]
971pub mod cache_request;
972#[doc = "CLOCK_GATE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"]
973pub type CLOCK_GATE = crate::Reg<clock_gate::CLOCK_GATE_SPEC>;
974#[doc = "******* Description ***********"]
975pub mod clock_gate;
976#[doc = "CACHE_TAG_OBJECT_CTRL (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_tag_object_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_tag_object_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_tag_object_ctrl`] module"]
977pub type CACHE_TAG_OBJECT_CTRL = crate::Reg<cache_tag_object_ctrl::CACHE_TAG_OBJECT_CTRL_SPEC>;
978#[doc = "******* Description ***********"]
979pub mod cache_tag_object_ctrl;
980#[doc = "CACHE_TAG_WAY_OBJECT (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_tag_way_object::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_tag_way_object::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_tag_way_object`] module"]
981pub type CACHE_TAG_WAY_OBJECT = crate::Reg<cache_tag_way_object::CACHE_TAG_WAY_OBJECT_SPEC>;
982#[doc = "******* Description ***********"]
983pub mod cache_tag_way_object;
984#[doc = "CACHE_VADDR (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_vaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_vaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_vaddr`] module"]
985pub type CACHE_VADDR = crate::Reg<cache_vaddr::CACHE_VADDR_SPEC>;
986#[doc = "******* Description ***********"]
987pub mod cache_vaddr;
988#[doc = "CACHE_TAG_CONTENT (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_tag_content::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_tag_content::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_tag_content`] module"]
989pub type CACHE_TAG_CONTENT = crate::Reg<cache_tag_content::CACHE_TAG_CONTENT_SPEC>;
990#[doc = "******* Description ***********"]
991pub mod cache_tag_content;
992#[doc = "DATE (rw) register accessor: ******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
993pub type DATE = crate::Reg<date::DATE_SPEC>;
994#[doc = "******* Description ***********"]
995pub mod date;