Struct R

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pub struct R<U, T> { /* private fields */ }

Expand description

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Implementations§

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impl<U, T> R<U, T>
where U: Copy,

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pub fn bits(&self) -> U

Read raw bits from register/field

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impl<FI> R<bool, FI>

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pub fn bit(&self) -> bool

Value of the field as raw bits

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pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0)

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pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1)

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Bits 0:3 - 3:0] SSI data size select (R/W) Reset value: 0x0 0000-0010: Reserved 0011: 4-bit data 0100: 5-bit data 0101: 6-bit data 0110: 7-bit data 0111: 8-bit data 1000: 9-bit data 1001: 10-bit data 1010: 11-bit data 1011: 12-bit data 1100: 13-bit data 1101: 14-bit data 1110: 15-bit data 1111: 16-bit data

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Bit 0 - 0:0] SSI loop-back mode (R/W) Reset value: 0x0 0: Normal serial port operation is enabled. 1: The output of the transmit serial shifter is connected to the input of the receive serial shift register internally.

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impl R<u32, Reg<u32, _DR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 16:31 - 31:16] Reserved

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pub fn data(&self) -> DATA_R

Bits 0:15 - 15:0] SSI receive/transmit data register (R/W) Reset value: 0xXXXX A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justified the data.

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pub fn reserved32(&self) -> RESERVED32_R

Bits 16:31 - 31:16] Reserved

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pub fn reserved16(&self) -> RESERVED16_R

Bits 8:15 - 15:8] Reserved, read unpredictable, should be written as 0.

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pub fn cpsdvsr(&self) -> CPSDVSR_R

Bits 0:7 - 7:0] SSI clock prescale divisor (R/W) Reset value: 0x0 This value must be an even number from 2 to 254, depending on the frequency of SSICLK. The LSB always returns zero on reads.

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impl R<u32, Reg<u32, _IM>>

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pub fn txim(&self) -> TXIM_R

Bit 3 - 3:3] SSI transmit FIFO interrupt mask (R/W) Reset value: 0x0 0: TX FIFO half empty or condition interrupt is masked. 1: TX FIFO half empty or less condition interrupt is not masked.

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pub fn rxim(&self) -> RXIM_R

Bit 2 - 2:2] SSI receive FIFO interrupt mask (R/W) Reset value: 0x0 0: RX FIFO half empty or condition interrupt is masked. 1: RX FIFO half empty or less condition interrupt is not masked.

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pub fn rtim(&self) -> RTIM_R

Bit 1 - 1:1] SSI receive time-out interrupt mask (R/W) Reset value: 0x0 0: RX FIFO time-out interrupt is masked. 1: RX FIFO time-out interrupt is not masked

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pub fn rorim(&self) -> RORIM_R

Bit 0 - 0:0] SSI receive overrun interrupt mask (R/W) Reset value: 0x0 0: RX FIFO Overrun interrupt is masked. 1: RX FIFO Overrun interrupt is not masked

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Bit 0 - 0:0] SSI SSIRORINTR raw state (RO) Reset value: 0x0 Gives the raw interrupt state (before masking) of SSIRORINTR

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Bit 0 - 0:0] SSI SSIRORINTR masked state (RO) Reset value: 0x0 Gives the interrupt state (after masking) of SSIRORINTR

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impl R<u32, Reg<u32, _ICR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 16:31 - 31:16] Reserved

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pub fn reserved16(&self) -> RESERVED16_R

Bits 0:3 - 3:0] SSI data size select (R/W) Reset value: 0x0 0000-0010: Reserved 0011: 4-bit data 0100: 5-bit data 0101: 6-bit data 0110: 7-bit data 0111: 8-bit data 1000: 9-bit data 1001: 10-bit data 1010: 11-bit data 1011: 12-bit data 1100: 13-bit data 1101: 14-bit data 1110: 15-bit data 1111: 16-bit data

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Bit 0 - 0:0] SSI loop-back mode (R/W) Reset value: 0x0 0: Normal serial port operation is enabled. 1: The output of the transmit serial shifter is connected to the input of the receive serial shift register internally.

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impl R<u32, Reg<u32, _DR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 16:31 - 31:16] Reserved

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pub fn data(&self) -> DATA_R

Bits 0:15 - 15:0] SSI receive/transmit data register (R/W) Reset value: 0xXXXX A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justified the data.

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pub fn reserved32(&self) -> RESERVED32_R

Bits 16:31 - 31:16] Reserved

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pub fn reserved16(&self) -> RESERVED16_R

Bits 8:15 - 15:8] Reserved, read unpredictable, should be written as 0.

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pub fn cpsdvsr(&self) -> CPSDVSR_R

Bits 0:7 - 7:0] SSI clock prescale divisor (R/W) Reset value: 0x0 This value must be an even number from 2 to 254, depending on the frequency of SSICLK. The LSB always returns zero on reads.

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impl R<u32, Reg<u32, _IM>>

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pub fn txim(&self) -> TXIM_R

Bit 3 - 3:3] SSI transmit FIFO interrupt mask (R/W) Reset value: 0x0 0: TX FIFO half empty or condition interrupt is masked. 1: TX FIFO half empty or less condition interrupt is not masked.

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pub fn rxim(&self) -> RXIM_R

Bit 2 - 2:2] SSI receive FIFO interrupt mask (R/W) Reset value: 0x0 0: RX FIFO half empty or condition interrupt is masked. 1: RX FIFO half empty or less condition interrupt is not masked.

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pub fn rtim(&self) -> RTIM_R

Bit 1 - 1:1] SSI receive time-out interrupt mask (R/W) Reset value: 0x0 0: RX FIFO time-out interrupt is masked. 1: RX FIFO time-out interrupt is not masked

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pub fn rorim(&self) -> RORIM_R

Bit 0 - 0:0] SSI receive overrun interrupt mask (R/W) Reset value: 0x0 0: RX FIFO Overrun interrupt is masked. 1: RX FIFO Overrun interrupt is not masked

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Bit 0 - 0:0] SSI SSIRORINTR raw state (RO) Reset value: 0x0 Gives the raw interrupt state (before masking) of SSIRORINTR

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Bit 0 - 0:0] SSI SSIRORINTR masked state (RO) Reset value: 0x0 Gives the interrupt state (after masking) of SSIRORINTR

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impl R<u32, Reg<u32, _ICR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 16:31 - 31:16] Reserved

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pub fn reserved16(&self) -> RESERVED16_R

Bits 0:7 - 7:0] Data transmitted or received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART.

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pub fn reserved24(&self) -> RESERVED24_R

Bits 8:31 - 31:8] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn data(&self) -> DATA_R

Bits 0:7 - 7:0] Error clear A write to this register of any data clears the framing, parity, break, and overrun flags.

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Bit 0 - 0:0] UART enable 1: The UART is enabled. 0: The UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping.

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impl R<u32, Reg<u32, _IFLS>>

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pub fn reserved26(&self) -> RESERVED26_R

Bits 6:31 - 31:6] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn rxiflsel(&self) -> RXIFLSEL_R

Bits 3:5 - 5:3] UART receive interrupt FIFO level select The trigger points for the receive interrupt are as follows: 0x0: RX FIFO >= 1/8 full 0x1: RX FIFO >= 1/4 full 0x2: RX FIFO >= 1/2 full (default) 0x3: RX FIFO >= 3/4 full 0x4: RX FIFO >= 7/8 full 0x5-0x7: Reserved

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pub fn txiflsel(&self) -> TXIFLSEL_R

Bits 0:2 - 2:0] UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: 0x0: TX FIFO <= 7/8 empty 0x1: TX FIFO <= 3/4 empty 0x2: TX FIFO <= 1/2 empty (default) 0x3: TX FIFO <= 1/4 empty 0x4: TX FIFO <= 1/8 empty 0x5-0x7: Reserved Note: If the EOT bit in UARTCTL is set, the transmit interrupt is generated once the FIFO is completely empty and all data including stop bits have left the transmit serializer. In this case, the setting of TXIFLSEL is ignored.

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Bits 0:3 - 3:0] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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Bits 0:3 - 3:0] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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Bits 0:3 - 3:0] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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Bits 0:3 - 3:0] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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impl R<u32, Reg<u32, _DMACTL>>

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pub fn reserved29(&self) -> RESERVED29_R

Bits 3:31 - 31:3] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn dmaerr(&self) -> DMAERR_R

Bit 2 - 2:2] DMA on error 1: uDMA receive requests are automatically disabled when a receive error occurs. 0: uDMA receive requests are unaffected when a receive error occurs.

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pub fn txdmae(&self) -> TXDMAE_R

Bit 1 - 1:1] Transmit DMA enable 1: uDMA for the transmit FIFO is enabled. 0: uDMA for the transmit FIFO is disabled.

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pub fn rxdmae(&self) -> RXDMAE_R

Bit 0 - 0:0] Receive DMA enable 1: uDMA for the receive FIFO is enabled. 0: uDMA for the receive FIFO is disabled.

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impl R<u32, Reg<u32, _LCTL>>

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pub fn reserved26(&self) -> RESERVED26_R

Bits 6:31 - 31:6] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn blen(&self) -> BLEN_R

pub fn cs(&self) -> CS_R

Bits 0:2 - 2:0] UART baud and system clock source The following bits determine the clock source that generates the baud and system clocks for the UART. bit0 (PIOSC): 1: The UART baud clock is determined by the IO DIV setting in the system controller. 0: The UART baud clock is determined by the SYS DIV setting in the system controller. bit1: Unused bit2: (DSEN) Only meaningful when the system is in deep sleep mode. This bit is a don’t care when not in sleep mode. 1: The UART system clock is running on the same clock as the baud clock, as per PIOSC setting above. 0: The UART system clock is determined by the SYS DIV setting in the system controller.

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Bits 0:7 - 7:0] Data transmitted or received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART.

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pub fn reserved24(&self) -> RESERVED24_R

Bits 8:31 - 31:8] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn data(&self) -> DATA_R

Bits 0:7 - 7:0] Error clear A write to this register of any data clears the framing, parity, break, and overrun flags.

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Bit 0 - 0:0] UART enable 1: The UART is enabled. 0: The UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping.

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impl R<u32, Reg<u32, _IFLS>>

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pub fn reserved26(&self) -> RESERVED26_R

Bits 6:31 - 31:6] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn rxiflsel(&self) -> RXIFLSEL_R

Bits 3:5 - 5:3] UART receive interrupt FIFO level select The trigger points for the receive interrupt are as follows: 0x0: RX FIFO >= 1/8 full 0x1: RX FIFO >= 1/4 full 0x2: RX FIFO >= 1/2 full (default) 0x3: RX FIFO >= 3/4 full 0x4: RX FIFO >= 7/8 full 0x5-0x7: Reserved

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pub fn txiflsel(&self) -> TXIFLSEL_R

Bits 0:2 - 2:0] UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: 0x0: TX FIFO <= 7/8 empty 0x1: TX FIFO <= 3/4 empty 0x2: TX FIFO <= 1/2 empty (default) 0x3: TX FIFO <= 1/4 empty 0x4: TX FIFO <= 1/8 empty 0x5-0x7: Reserved Note: If the EOT bit in UARTCTL is set, the transmit interrupt is generated once the FIFO is completely empty and all data including stop bits have left the transmit serializer. In this case, the setting of TXIFLSEL is ignored.

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Bits 0:3 - 3:0] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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Bits 0:3 - 3:0] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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Bits 0:3 - 3:0] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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Bits 0:3 - 3:0] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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impl R<u32, Reg<u32, _DMACTL>>

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pub fn reserved29(&self) -> RESERVED29_R

Bits 3:31 - 31:3] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn dmaerr(&self) -> DMAERR_R

Bit 2 - 2:2] DMA on error 1: uDMA receive requests are automatically disabled when a receive error occurs. 0: uDMA receive requests are unaffected when a receive error occurs.

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pub fn txdmae(&self) -> TXDMAE_R

Bit 1 - 1:1] Transmit DMA enable 1: uDMA for the transmit FIFO is enabled. 0: uDMA for the transmit FIFO is disabled.

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pub fn rxdmae(&self) -> RXDMAE_R

Bit 0 - 0:0] Receive DMA enable 1: uDMA for the receive FIFO is enabled. 0: uDMA for the receive FIFO is disabled.

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impl R<u32, Reg<u32, _LCTL>>

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pub fn reserved26(&self) -> RESERVED26_R

Bits 6:31 - 31:6] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn blen(&self) -> BLEN_R

pub fn reserved7(&self) -> RESERVED7_R

Bits 8:14 - 14:8] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn addr(&self) -> ADDR_R

Bits 0:7 - 7:0] Self address for 9-bit mode This field contains the address that should be matched when UART9BITAMASK is 0xFF.

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impl R<u32, Reg<u32, _NINEBITAMASK>>

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pub fn reserved16(&self) -> RESERVED16_R

Bits 16:31 - 31:16] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn range(&self) -> RANGE_R

Bits 8:15 - 15:8] Self address range for 9-bit mode Writing to the RANGE field does not have any effect; reading it reflects the ANDed output of the ADDR field in the UART9BITADDR register and the MASK field.

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pub fn mask(&self) -> MASK_R

Bits 0:7 - 7:0] Self Address Mask for 9-Bit Mode This field contains the address mask that creates a range of addresses that should be matched.

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impl R<u32, Reg<u32, _PP>>

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pub fn reserved30(&self) -> RESERVED30_R

pub fn rs(&self) -> RS_R

Bit 0 - 0:0] Receive and send The R/S bit specifies if the next operation is a receive (high) or transmit (low). 0: Transmit 1: Receive

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pub fn mfe(&self) -> MFE_R

pub fn treq(&self) -> TREQ_R

Bit 1 - 1:1] Transmit request 1: The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the I2CSDR register. 0: No outstanding transmit request.

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pub fn rreq(&self) -> RREQ_R

Bit 0 - 0:0] Receive request 1: The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until data has been read from the I2CSDR register. 0: No outstanding receive data

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impl R<u32, Reg<u32, _CTRL>>

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pub fn reserved31(&self) -> RESERVED31_R

Bits 1:31 - 31:1] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn da(&self) -> DA_R

Bit 0 - 0:0] Device active 0: Disables the I2C slave operation 1: Enables the I2C slave operation

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Bits 0:1 - 1:0] GPTM Timer B mode 0x0: Reserved 0x1: One-shot timer mode 0x2: Periodic timer mode 0x3: Capture mode The timer mode is based on the timer configuration defined by bits [2:0] in the GPTMCFG register.

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Bit 0 - 0:0] GPTM Timer A enable 0: Timer A is disabled. 1: Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.

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Bit 0 - 0:0] GPTM Timer A time-out raw interrupt

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Bits 0:15 - 15:0] GPTM B interval load register

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Bits 0:31 - 31:0] GPTM Timer A register

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impl R<u32, Reg<u32, _TBR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 16:31 - 31:16] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn tbr(&self) -> TBR_R

Bits 0:15 - 15:0] GPTM Timer B register

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Bits 7:31 - 31:7] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn altclk(&self) -> ALTCLK_R

Bit 6 - 6:6] Alternate clock source 0: Timer is not capable of using an alternate clock. 1: Timer is capable of using an alternate clock.

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pub fn syncnt(&self) -> SYNCNT_R

Bit 5 - 5:5] Synchronized start 0: Timer is not capable of synchronizing the count value with other timers. 1: Timer is capable of synchronizing the count value with other timers.

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pub fn chain(&self) -> CHAIN_R

Bit 4 - 4:4] Chain with other timers 0: Timer is not capable of chaining with previously numbered Timers. 1: Timer is capable of chaining with previously numbered timers.

Bits 0:1 - 1:0] GPTM Timer A mode 0x0: Reserved 0x1: One-shot mode 0x2: Periodic mode 0x3: Capture mode The timer mode is based on the timer configuration defined by bits [2:0] in the GPTMCFG register.

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Bits 0:1 - 1:0] GPTM Timer B mode 0x0: Reserved 0x1: One-shot timer mode 0x2: Periodic timer mode 0x3: Capture mode The timer mode is based on the timer configuration defined by bits [2:0] in the GPTMCFG register.

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Bit 0 - 0:0] GPTM Timer A enable 0: Timer A is disabled. 1: Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.

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Bit 0 - 0:0] GPTM Timer A time-out raw interrupt

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Bits 0:15 - 15:0] GPTM B interval load register

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Bits 0:31 - 31:0] GPTM Timer A register

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impl R<u32, Reg<u32, _TBR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 16:31 - 31:16] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn tbr(&self) -> TBR_R

Bits 0:15 - 15:0] GPTM Timer B register

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Bits 7:31 - 31:7] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn altclk(&self) -> ALTCLK_R

Bit 6 - 6:6] Alternate clock source 0: Timer is not capable of using an alternate clock. 1: Timer is capable of using an alternate clock.

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pub fn syncnt(&self) -> SYNCNT_R

Bit 5 - 5:5] Synchronized start 0: Timer is not capable of synchronizing the count value with other timers. 1: Timer is capable of synchronizing the count value with other timers.

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pub fn chain(&self) -> CHAIN_R

Bit 4 - 4:4] Chain with other timers 0: Timer is not capable of chaining with previously numbered Timers. 1: Timer is capable of chaining with previously numbered timers.

Bits 0:1 - 1:0] GPTM Timer A mode 0x0: Reserved 0x1: One-shot mode 0x2: Periodic mode 0x3: Capture mode The timer mode is based on the timer configuration defined by bits [2:0] in the GPTMCFG register.

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Bits 0:1 - 1:0] GPTM Timer B mode 0x0: Reserved 0x1: One-shot timer mode 0x2: Periodic timer mode 0x3: Capture mode The timer mode is based on the timer configuration defined by bits [2:0] in the GPTMCFG register.

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Bit 0 - 0:0] GPTM Timer A enable 0: Timer A is disabled. 1: Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.

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Bit 0 - 0:0] GPTM Timer A time-out raw interrupt

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Bits 0:15 - 15:0] GPTM B interval load register

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Bits 0:31 - 31:0] GPTM Timer A register

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impl R<u32, Reg<u32, _TBR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 16:31 - 31:16] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn tbr(&self) -> TBR_R

Bits 0:15 - 15:0] GPTM Timer B register

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Bits 7:31 - 31:7] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn altclk(&self) -> ALTCLK_R

Bit 6 - 6:6] Alternate clock source 0: Timer is not capable of using an alternate clock. 1: Timer is capable of using an alternate clock.

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pub fn syncnt(&self) -> SYNCNT_R

Bit 5 - 5:5] Synchronized start 0: Timer is not capable of synchronizing the count value with other timers. 1: Timer is capable of synchronizing the count value with other timers.

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pub fn chain(&self) -> CHAIN_R

Bit 4 - 4:4] Chain with other timers 0: Timer is not capable of chaining with previously numbered Timers. 1: Timer is capable of chaining with previously numbered timers.

Bits 0:1 - 1:0] GPTM Timer A mode 0x0: Reserved 0x1: One-shot mode 0x2: Periodic mode 0x3: Capture mode The timer mode is based on the timer configuration defined by bits [2:0] in the GPTMCFG register.

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Bits 0:1 - 1:0] GPTM Timer B mode 0x0: Reserved 0x1: One-shot timer mode 0x2: Periodic timer mode 0x3: Capture mode The timer mode is based on the timer configuration defined by bits [2:0] in the GPTMCFG register.

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Bit 0 - 0:0] GPTM Timer A enable 0: Timer A is disabled. 1: Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.

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Bit 0 - 0:0] GPTM Timer A time-out raw interrupt

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Bits 0:15 - 15:0] GPTM B interval load register

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Bits 0:31 - 31:0] GPTM Timer A register

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impl R<u32, Reg<u32, _TBR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 16:31 - 31:16] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn tbr(&self) -> TBR_R

Bits 0:15 - 15:0] GPTM Timer B register

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Bits 7:31 - 31:7] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn altclk(&self) -> ALTCLK_R

Bit 6 - 6:6] Alternate clock source 0: Timer is not capable of using an alternate clock. 1: Timer is capable of using an alternate clock.

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pub fn syncnt(&self) -> SYNCNT_R

Bit 5 - 5:5] Synchronized start 0: Timer is not capable of synchronizing the count value with other timers. 1: Timer is capable of synchronizing the count value with other timers.

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pub fn chain(&self) -> CHAIN_R

Bit 7 - 7:7] Reserved. Always read 0.

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pub fn fcf_reserved_mask(&self) -> FCF_RESERVED_MASK_R

Bits 4:6 - 6:4] Used for filtering on the reserved part of the frame control field (FCF) FCF_RESERVED_MASK[2:0] is ANDed with FCF[9:7]. If the result is nonzero and frame filtering is enabled, the frame is rejected.

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pub fn max_frame_version(&self) -> MAX_FRAME_VERSION_R

Bits 2:3 - 3:2] Used for filtering on the frame version field of the frame control field (FCF) If FCF[13:12] (the frame version subfield) is higher than MAX_FRAME_VERSION[1:0] and frame filtering is enabled, the frame is rejected.

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pub fn pan_coordinator(&self) -> PAN_COORDINATOR_R

Bit 1 - 1:1] Should be set high when the device is a PAN coordinator, to accept frames with no destination address (as specified in Section 7.5.6.2 in IEEE 802.15.4) 0: Device is not a PAN coordinator 1: Device is a PAN coordinator

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pub fn frame_filter_en(&self) -> FRAME_FILTER_EN_R

Bit 0 - 0:0] Enables frame filtering When this bit is set, the radio performs frame filtering as specified in section 7.5.6.2 of IEEE 802.15.4(b), third filtering level. FRMFILT0[6:1] and FRMFILT1[7:1], together with the local address information, define the behavior of the filtering algorithm. 0: Frame filtering off. (FRMFILT0[6:1], FRMFILT1[7:1] and SRCMATCH[2:0] are don’t care.) 1: Frame filtering on.

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Bit 0 - 0:0] Reserved. Always write 0.

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impl R<u32, Reg<u32, _SRCMATCH>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

Bits 3:7 - 7:3] Reserved. Always read 0.

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pub fn pend_datareq_only(&self) -> PEND_DATAREQ_ONLY_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

Bits 3:7 - 7:3] Reserved. Read as 0.

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pub fn pending_or(&self) -> PENDING_OR_R

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn cal_done(&self) -> CAL_DONE_R

Bit 7 - 7:7] Frequency synthesis calibration has been performed since the last time the FS was turned on.

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pub fn cal_running(&self) -> CAL_RUNNING_R

Bit 6 - 6:6] Frequency synthesis calibration status 0: Calibration is complete or not started. 1: Calibration is in progress.

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pub fn fsm_ffctrl_state(&self) -> FSM_FFCTRL_STATE_R

Bits 0:5 - 5:0] Gives the current state of the FIFO and frame control (FFCTRL) finite state-machine.

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pub fn rfirqm(&self) -> RFIRQM_R

Bits 0:5 - 5:0] Bit mask is masking out interrupt sources. Bit position: 5: CSP_WAIT 4: CSP_STOP 3: CSP_MANINT 2: RF_IDLE 1: TXDONE 0: TXACKDONE

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impl R<u32, Reg<u32, _RFERRM>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

Bit 7 - 7:7] 7: Reserved

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pub fn rferrm(&self) -> RFERRM_R

Bits 0:6 - 6:0] Bit mask is masking out interrupt sources. Bit position: 6: STROBE_ERR 5: TXUNDERF 4: TXOVERF 3: RXUNDERF 2: RXOVERF 1: RXABO 0: NLOCK

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impl R<u32, Reg<u32, _RFRND>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

Bits 2:7 - 7:2] Reserved. Always read 0.

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pub fn qrnd(&self) -> QRND_R

Bit 1 - 1:1] Random bit from the Q channel of the receiver

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pub fn irnd(&self) -> IRND_R

Bit 0 - 0:0] Random bit from the I channel of the receiver

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

Bits 6:7 - 7:6] Reserved. Always read 0.

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pub fn corr_thr_sfd(&self) -> CORR_THR_SFD_R

Bit 5 - 5:5] Defines requirements for SFD detection: 0: The correlation value of one of the zero symbols of the preamble must be above the correlation threshold. 1: The correlation value of one zero symbol of the preamble and both symbols in the SFD must be above the correlation threshold.

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pub fn corr_thr(&self) -> CORR_THR_R

Bits 0:4 - 4:0] Demodulator correlator threshold value, required before SFD search. Threshold value adjusts how the receiver synchronizes to data from the radio. If the threshold is set too low, sync can more easily be found on noise. If set too high, the sensitivity is reduced, but sync is not likely to be found on noise. In combination with DEM_NUM_ZEROS, the system can be tuned so sensitivity is high with less sync found on noise.

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impl R<u32, Reg<u32, _FREQEST>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn freqest(&self) -> FREQEST_R

Bits 0:7 - 7:0] Signed 2’s-complement value. Contains an estimate of the frequency offset between carrier and the receiver LO. The offset frequency is FREQEST x 7800 Hz. DEM_AVG_MODE controls when this estimate is updated. If DEM_AVG_MODE = 0, it is updated until sync is found. Then the frequency offset estimate is frozen until the end of the received frame. If DEM_AVG_MODE = 1, it is updated as long as the demodulator is enabled. To calculate the correct value, one must use an offset (FREQEST_offset), which can be found in the device data sheet. Real FREQEST value = FREQEST - FREQEST_offset.

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Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn vco_curr_cal_oe(&self) -> VCO_CURR_CAL_OE_R

Bit 7 - 7:7] Override current calibration

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pub fn vco_curr_cal(&self) -> VCO_CURR_CAL_R

Bits 2:6 - 6:2] Calibration result Override value if VCO_CURR_CAL_OE = 1

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pub fn vco_curr(&self) -> VCO_CURR_R

Bits 0:1 - 1:0] Defines current in VCO core Sets the multiplier between calibrated current and VCO current.

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impl R<u32, Reg<u32, _FSCAL2>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

Bit 7 - 7:7] Reserved. Always read 0.

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pub fn vco_caparr_oe(&self) -> VCO_CAPARR_OE_R

Bit 6 - 6:6] Override the calibration result with the value from VCO_CAPARR[5:0].

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pub fn vco_caparr(&self) -> VCO_CAPARR_R

Bits 0:5 - 5:0] VCO capacitor array setting Programmed during calibration Override value when VCO_CAPARR_OE = 1

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

Bit 7 - 7:7] Reserved. Always read 0.

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pub fn agc_dr_xtnd_en(&self) -> AGC_DR_XTND_EN_R

Bit 6 - 6:6] 0: The AGC performs no adjustment of attenuation in the AAF. 1: The AGC adjusts the gain in the AAF to achieve extra dynamic range for the receiver.

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pub fn agc_dr_xtnd_thr(&self) -> AGC_DR_XTND_THR_R

Bits 0:5 - 5:0] If the measured error between the AGC reference magnitude and the actual magnitude in dB is larger than this threshold, the extra attenuation is enabled in the front end. This threshold must be set higher than 0x0C. This feature is enabled by AGC_DR_XTND_EN.

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impl R<u32, Reg<u32, _AGCCTRL1>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

Bits 6:7 - 7:6] Reserved. Always read 0.

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pub fn agc_ref(&self) -> AGC_REF_R

Bits 0:5 - 5:0] Target value for the AGC control loop, given in 1-dB steps

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn adc_test_ctrl(&self) -> ADC_TEST_CTRL_R

Bits 4:7 - 7:4] ADC test mode selector

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pub fn adc_c2_adj(&self) -> ADC_C2_ADJ_R

Bits 2:3 - 3:2] Used to adjust capacitor values in ADC

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pub fn adc_c3_adj(&self) -> ADC_C3_ADJ_R

Bits 0:1 - 1:0] Used to adjust capacitor values in ADC

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Bit 0 - 0:0] Control of DAC DWA scheme 0 = DWA (scrambling) disabled 1 = DWA enabled

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impl R<u32, Reg<u32, _MDMTEST0>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn tx_tone(&self) -> TX_TONE_R

Bits 4:7 - 7:4] Enables the possibility to transmit a baseband tone by picking samples from the sine tables with a controllable phase step between the samples. The step size is controlled by TX_TONE. If MDMTEST1.MOD_IF is 0, the tone is superpositioned on the modulated data, effectively giving modulation with an IF. If MDMTEST1.MOD_IF is 1, only the tone is transmitted. 0000: -6 MHz 0001: -4 MHz 0010: -3 MHz 0011: -2 MHz 0100: -1 MHz 0101: -500 kHz 0110: -4 kHz 0111: 0 1000: 4 kHz 1001: 500 kHz 1010: 1 MHz 1011: 2 MHz 1100: 3 MHz 1101: 4 MHz 1110: 6 MHz Others: Reserved

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pub fn dc_win_size(&self) -> DC_WIN_SIZE_R

Bits 2:3 - 3:2] Controls the numbers of samples to be accumulated between each dump of the accumulate-and-dump filter used in DC removal 00: 32 samples 01: 64 samples 10: 128 samples 11: 256 samples

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pub fn dc_block_mode(&self) -> DC_BLOCK_MODE_R

Bits 0:1 - 1:0] Selects the mode of operation 00: The input signal to the DC blocker is passed to the output without any attempt to remove DC. 01: Enable DC cancellation. Normal operation 10: Freeze estimates of DC when sync is found. Resume estimating DC when searching for the next frame. 11: Reserved

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn dac_q_o(&self) -> DAC_Q_O_R

Bits 0:7 - 7:0] Q-branch DAC override value when DAC_SRC = 001 If DAC_SRC is set to be ADC data, CORDIC magnitude, or channel filtered data, then DAC_Q_O controls the part of the word in question that is actually multiplexed to the DAC, as described below. 000111: Bits 7:0 001000: Bits 8:1 001001: Bits 9:2 … If an invalid setting is chosen, the DAC outputs only zeros (minimum value).

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impl R<u32, Reg<u32, _DACTEST1>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn dac_i_o(&self) -> DAC_I_O_R

Bits 0:7 - 7:0] I-branch DAC override value when DAC_SRC = 001 If DAC_SRC is set to be ADC data, CORDIC magnitude, channel filtered data, or DC filtered data, then DAC_I_O controls the part of the word in question that is actually multiplexed to the DAC as described below. 000111: Bits 7:0 001000: Bits 8:1 001001: Bits 9:2 … If an invalid setting is chosen, then the DAC outputs only zeros (minimum value).

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

Bits 6:7 - 7:6] Reserved. Always read 0.

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pub fn atest_ctrl(&self) -> ATEST_CTRL_R

Bits 0:5 - 5:0] Controls the analog test mode: 00 0000: Disabled 00 0001: Enables the temperature sensor (see also the CCTEST_TR0 register description). Other values reserved.

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Bit 0 - 0:0] Antialiasing filter power-down signal When PD_OVERRIDE = 1

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impl R<u32, Reg<u32, _PTEST1>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

Bits 4:7 - 7:4] Reserved. Always read 0.

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pub fn pd_override(&self) -> PD_OVERRIDE_R

Bit 3 - 3:3] Override enabling and disabling of various modules (for debug and testing only) It is impossible to override hard-coded BIAS_PD[1:0] depenancy.

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pub fn pa_pd(&self) -> PA_PD_R

pub fn mcu_ctrl(&self) -> MCU_CTRL_R

Bit 0 - 0:0] CSP MCU control input

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impl R<u32, Reg<u32, _CSPSTAT>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

pub fn sync(&self) -> SYNC_R

Bit 1 - 1:1] 0: Starting and stopping of timer is immediate; that is, synchronous with clk_rf_32m. 1: Starting and stopping of timer occurs at the first positive edge of the 32-kHz clock. For more details regarding timer start and stop, see Section 22.4.

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pub fn run(&self) -> RUN_R

Bit 0 - 0:0] Write 1 to start timer, write 0 to stop timer. When read, it returns the last written value.

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Bit 0 - 0:0] Enables the MACTIMER_PER interrupt

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Bit 0 - 0:0] Set when the MAC Timer counter would have counted to a value equal to MT_per, but instead wraps to 0

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impl R<u32, Reg<u32, _MTMSEL>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn reserved8(&self) -> RESERVED8_R

Bit 7 - 7:7] Reserved. Always read 0.

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pub fn mtmovfsel(&self) -> MTMOVFSEL_R

pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn instr(&self) -> INSTR_R

Bits 0:7 - 7:0] Data written to this register is written to the CSP instruction memory. Reading this register returns the CSP instruction currently being executed.

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impl R<u32, Reg<u32, _ADDR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] Reserved

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pub fn update(&self) -> UPDATE_R

Bit 7 - 7:7] This bit is set by hardware when writing to this register, and is cleared by hardware when the new address becomes effective.

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pub fn usbaddr(&self) -> USBADDR_R

Bits 0:6 - 6:0] Device address. The address shall be updated upon successful completion of the status stage of the SET_ADDRESS request.

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Bit 0 - 0:0] Reserved

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Bit 0 - 0:0] Suspend interrupt flag Cleared by hardware when read

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Bit 0 - 0:0] Interrupt enable for endpoint 0 0: Interrupt disabled 1: Interrupt enabled

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Bit 0 - 0:0] Reserved

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Bit 0 - 0:0] Suspend interrupt enable 0: Interrupt disabled 1: Interrupt enabled

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Bit 0 - 0:0] USB enable The USB controller is reset when this bit is cleared

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impl R<u32, Reg<u32, _MAXI>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] Reserved

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pub fn usbmaxi(&self) -> USBMAXI_R

Bits 0:7 - 7:0] Maximum packet size, in units of 8 bytes, for the selected IN endpoint The value of this register should match the wMaxPacketSize field in the standard endpoint descriptor for the endpoint. The value must not exceed the available memory.

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impl R<u32, Reg<u32, _MAXO>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] Reserved

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pub fn usbmaxo(&self) -> USBMAXO_R

Bits 0:7 - 7:0] Maximum packet size, in units of 8 bytes, for the selected OUT endpoint The value of this register should match the wMaxPacketSize field in the standard endpoint descriptor for the endpoint. The value must not exceed the available memory.

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] Reserved

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pub fn fifocnt_or_fifocntl(&self) -> FIFOCNT_OR_FIFOCNTL_R

Bits 0:7 - 7:0] USB_CS0.FIFOCNT (USBINDEX = 0) [RO]: Number of bytes received in the packet in the endpoint 0 FIFO Valid only when USB_CS0.OUTPKTRDY is set USB_CSIL.FIFOCNTL (USBINDEX = 1 to 5) [RW]: Bits 7:0 of the of the number of bytes received in the packet in the OUT endpoint {1-5} FIFO Valid only when USB_CSOL.OUTPKTRDY is set

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impl R<u32, Reg<u32, _CNTH>>

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pub fn reserved32(&self) -> RESERVED32_R

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impl R<u32, Reg<u32, _DMAC_STATUS>>

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pub fn reserved14(&self) -> RESERVED14_R

Bits 18:31 - 31:18] Bits should be ignored on read.

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pub fn port_err(&self) -> PORT_ERR_R

Bit 17 - 17:17] Reflects possible transfer errors on the AHB port.

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pub fn reserved15(&self) -> RESERVED15_R

Bits 2:16 - 16:2] Bits should be ignored on read.

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pub fn ch1_act(&self) -> CH1_ACT_R

pub fn ahb_mst1_incr_en(&self) -> AHB_MST1_INCR_EN_R

Bit 10 - 10:10] Burst length type of AHB transfer 0: Unspecified length burst transfers 1: Fixed length burst or single transfers

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pub fn ahb_mst1_lock_en(&self) -> AHB_MST1_LOCK_EN_R

Bit 9 - 9:9] Locked transform on AHB 0: Transfers are not locked 1: Transfers are locked

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pub fn ahb_mst1_bigend(&self) -> AHB_MST1_BIGEND_R

Bit 8 - 8:8] Endianess for the AHB master 0: Little endian 1: Big endian

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pub fn reserved8(&self) -> RESERVED8_R

Bits 0:7 - 7:0] Should be written with 0s and ignored on read

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pub fn reserved20(&self) -> RESERVED20_R

Bits 12:31 - 31:12] Bits should be ignored on read

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pub fn nr_of_channels(&self) -> NR_OF_CHANNELS_R

Bits 8:11 - 11:8] Number of channels implemented, value in the range 1-8.

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pub fn reserved5(&self) -> RESERVED5_R

Bits 3:7 - 7:3] Bits should be ignored on read

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pub fn nr_of_ports(&self) -> NR_OF_PORTS_R

Bits 0:2 - 2:0] Number of ports implemented, value in range 1-4.

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Bits 0:7 - 7:0] Binary encoding of the EIP-number of this DMA controller (209)

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pub fn reserved1(&self) -> RESERVED1_R

Bits 2:31 - 31:2] Write 0s and ignore on reading

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pub fn key_size(&self) -> KEY_SIZE_R

Bits 0:1 - 1:0] Key size: 00: Reserved 01: 128 bits 10: 192 bits 11: 256 bits When writing this to this register, the KEY_STORE_WRITTEN_AREA register is reset.

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impl R<u32, Reg<u32, _KEY_STORE_READ_AREA>>

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pub fn busy(&self) -> BUSY_R

Bit 31 - 31:31] Key store operation busy status flag (read only): 0: Operation is complete. 1: Operation is not completed and the key store is busy.

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pub fn reserved1(&self) -> RESERVED1_R

Bit 0 - 0:0] Indicates that the output buffer registers (HASH_DIGEST_n) are available for reading by the host. When this bit reads 0, the output buffer registers are released; the hash engine is allowed to write new data to it. In this case, the registers should not be read by the host. When this bit reads 1, the hash engine has stored the result of the latest hash operation in the output buffer registers. As long as this bit reads 1, the host may read output buffer registers and the hash engine is prevented from writing new data to the output buffer. After retrieving the hash result data from the output buffer, the host must write a 1 to this bit to clear it. This makes the digest output buffer available for the hash engine to store new hash results. Writing 0 to this bit has no effect. Note: If this bit is asserted (1) no new operation should be started before the digest is retrieved from the hash engine and this bit is cleared (0).

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impl R<u32, Reg<u32, _HASH_MODE_IN>>

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pub fn reserved1(&self) -> RESERVED1_R

Bits 4:31 - 31:4] Write 0s and ignore on reading

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pub fn sha256_mode(&self) -> SHA256_MODE_R

Bit 3 - 3:3] The host must write this bit with 1 before processing a hash session.

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pub fn reserved2(&self) -> RESERVED2_R

Bits 3:30 - 30:3] Bits should be written with 0s and ignored on read.

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pub fn hash(&self) -> HASH_R

pub fn result_av(&self) -> RESULT_AV_R

Bit 0 - 0:0] If this bit is set to 0, the result available (irq_result_av) interrupt output is disabled and remains 0. If this bit is set to 1, the result available interrupt output is enabled.

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Bit 0 - 0:0] If 1 is written to this bit, the result available (irq_result_av) interrupt output is cleared. Writing 0 has no effect. Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to CTRL_INT_CFG).

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impl R<u32, Reg<u32, _CTRL_INT_SET>>

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pub fn reserved30(&self) -> RESERVED30_R

Bits 2:31 - 31:2] Bits should be written with 0s and ignored on read.

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pub fn dma_in_done(&self) -> DMA_IN_DONE_R

Bit 1 - 1:1] If 1 is written to this bit, the DMA data in done (irq_dma_in_done) interrupt output is set to one. Writing 0 has no effect. If the interrupt configuration register is programmed to pulse, clearing the DMA data in done (irq_dma_in_done) interrupt is not needed. If it is programmed to level, clearing the interrupt output should be done by writing the interrupt clear register (CTRL_INT_CLR).

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pub fn result_av(&self) -> RESULT_AV_R

Bit 0 - 0:0] If 1 is written to this bit, the result available (irq_result_av) interrupt output is set to one. Writing 0 has no effect. If the interrupt configuration register is programmed to pulse, clearing the result available (irq_result_av) interrupt is not needed. If it is programmed to level, clearing the interrupt output should be done by writing the interrupt clear register (CTRL_INT_CLR).

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Bit 0 - 0:0] This read only bit returns the actual result available (irq_result_av) interrupt status of the result available interrupt output pin (irq_result_av).

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Bits 0:2 - 2:0] System clock rate setting Cannot be higher than OSC setting 000: 32 MHz 001: 16 MHz 010: 8 MHz 011: 4 MHz 100: 2 MHz 101: 1 MHz 110: 0.5 MHz 111: 0.25 MHz

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Bits 0:2 - 2:0] Returns current functional frequency for system clock (may differ from setting in the CLOCK_CTRL register) 000: 32 MHz 001: 16 MHz 010: 8 MHz 011: 4 MHz 100: 2 MHz 101: 1 MHz 110: 0.5 MHz 111: 0.25 MHz

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Bits 4:31 - 31:4] This register is 8 bits in a 32-bit address space.

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pub fn gpt3(&self) -> GPT3_R

Bits 2:31 - 31:2] This register is 8 bits in a 32-bit address space.

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pub fn pm(&self) -> PM_R

Bits 0:1 - 1:0] 00: No action 01: PM1 10: PM2 11: PM3

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pub fn reserved32(&self) -> RESERVED32_R

Bits 17:31 - 31:17] Unused. These bits always reflect 0 on read back

pub fn en(&self) -> EN_R

pub fn stload(&self) -> STLOAD_R

Bit 0 - 0:0] Status signal for when STx registers have been uploaded to 32-kHz counter. 1: Load is complete 0: Load is busy and STx regs are blocked for writing

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impl R<u32, Reg<u32, _STCC>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 6:31

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pub fn port(&self) -> PORT_R

Bits 3:5 - 5:3] Port select Valid settings are 0-3, all others inhibit any capture from occurring 000: Port A selected 001: Port B selected 010: Port C selected 011: Port D selected

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pub fn pin(&self) -> PIN_R

Bits 0:2 - 2:0] Pin select Valid settings are 1-7 when either port A, B, C, or D is selected.

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impl R<u32, Reg<u32, _STCS>>

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pub fn reserved32(&self) -> RESERVED32_R

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn sref(&self) -> SREF_R

Bits 6:7 - 7:6] Selects reference voltage used for the sequence of conversions 00: Internal reference 01: External reference on AIN7 pin 10: AVDD5 pin 11: External reference on AIN6-AIN7 differential input

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pub fn sdiv(&self) -> SDIV_R

Bits 4:5 - 5:4] Sets the decimation rate for channels included in the sequence of conversions. The decimation rate also determines the resolution and time required to complete a conversion. 00: 64 decimation rate (7 bits ENOB setting) 01: 128 decimation rate (9 bits ENOB setting) 10: 256 decimation rate (10 bits ENOB setting) 11: 512 decimation rate (12 bits ENOB setting)

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pub fn sch(&self) -> SCH_R

Bits 0:3 - 3:0] Sequence channel select Selects the end of the sequence A sequence can either be from AIN0 to AIN7 (SCH <= 7) or from differential input AIN0-AIN1 to AIN6-AIN7 (8 <= SCH <= 11). For other settings, only one conversions is performed. When read, these bits indicate the channel number on which a conversion is ongoing: 0000: AIN0 0001: AIN1 0010: AIN2 0011: AIN3 0100: AIN4 0101: AIN5 0110: AIN6 0111: AIN7 1000: AIN0-AIN1 1001: AIN2-AIN3 1010: AIN4-AIN5 1011: AIN6-AIN7 1100: GND 1101: Reserved 1110: Temperature sensor 1111: VDD/3

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impl R<u32, Reg<u32, _ADCCON3>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] This register is 8 bits in a 32-bit address space.

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pub fn eref(&self) -> EREF_R

Bits 6:7 - 7:6] Selects reference voltage used for the extra conversion 00: Internal reference 01: External reference on AIN7 pin 10: AVDD5 pin 11: External reference on AIN6-AIN7 differential input

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pub fn ediv(&self) -> EDIV_R

Bits 4:5 - 5:4] Sets the decimation rate used for the extra conversion The decimation rate also determines the resolution and the time required to complete the conversion. 00: 64 decimation rate (7 bits ENOB) 01: 128 decimation rate (9 bits ENOB) 10: 256 decimation rate (10 bits ENOB) 11: 512 decimation rate (12 bits ENOB)

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pub fn ech(&self) -> ECH_R

Bits 0:3 - 3:0] Single channel select. Selects the channel number of the single conversion that is triggered by writing to ADCCON3. 0000: AIN0 0001: AIN1 0010: AIN2 0011: AIN3 0100: AIN4 0101: AIN5 0110: AIN6 0111: AIN7 1000: AIN0-AIN1 1001: AIN2-AIN3 1010: AIN4-AIN5 1011: AIN6-AIN7 1100: GND 1101: Reserved 1110: Temperature sensor 1111: VDD/3

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impl R<u32, Reg<u32, _ADCL>>

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pub fn reserved32(&self) -> RESERVED32_R

impl R<u32, Reg<u32, _GPIOCR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] Reserved bits return an indeterminate value, and should never be changed.

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pub fn cr(&self) -> CR_R

Bits 0:7 - 7:0] On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function.

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impl R<u32, Reg<u32, _USB_CTRL>>

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pub fn reserved31(&self) -> RESERVED31_R

Bits 1:31

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pub fn usb_edge_ctl(&self) -> USB_EDGE_CTL_R

Bit 0 - 0:0] Used to set the edge which triggers the USB power up interrupt 0: Rising 1: Falling

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Bit 0 - 0:0] Port A bit 0 interrupt enable: 1: Enabled 2: Disabled

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Bit 0 - 0:0] Port A bit 0 masked interrupt status: 1: Detected 0: Not detected

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impl R<u32, Reg<u32, _USB_IRQ_ACK>>

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pub fn reserved31(&self) -> RESERVED31_R

Bits 1:31

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pub fn usback(&self) -> USBACK_R

Bit 0 - 0:0] USB masked interrupt status: 1: Detected 0: Not detected

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impl R<u32, Reg<u32, _GPIOLOCK>>

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pub fn lock(&self) -> LOCK_R

Bits 0:31 - 31:0] A read of this register returns the following values: Locked: 0x00000001 Unlocked: 0x00000000

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impl R<u32, Reg<u32, _GPIOCR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] Reserved bits return an indeterminate value, and should never be changed.

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pub fn cr(&self) -> CR_R

Bits 0:7 - 7:0] On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function.

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impl R<u32, Reg<u32, _USB_CTRL>>

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pub fn reserved31(&self) -> RESERVED31_R

Bits 1:31

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pub fn usb_edge_ctl(&self) -> USB_EDGE_CTL_R

Bit 0 - 0:0] Used to set the edge which triggers the USB power up interrupt 0: Rising 1: Falling

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Bit 0 - 0:0] Port A bit 0 interrupt enable: 1: Enabled 2: Disabled

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Bit 0 - 0:0] Port A bit 0 masked interrupt status: 1: Detected 0: Not detected

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impl R<u32, Reg<u32, _USB_IRQ_ACK>>

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pub fn reserved31(&self) -> RESERVED31_R

Bits 1:31

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pub fn usback(&self) -> USBACK_R

Bit 0 - 0:0] USB masked interrupt status: 1: Detected 0: Not detected

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impl R<u32, Reg<u32, _GPIOLOCK>>

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pub fn lock(&self) -> LOCK_R

Bits 0:31 - 31:0] A read of this register returns the following values: Locked: 0x00000001 Unlocked: 0x00000000

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impl R<u32, Reg<u32, _GPIOCR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] Reserved bits return an indeterminate value, and should never be changed.

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pub fn cr(&self) -> CR_R

Bits 0:7 - 7:0] On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function.

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impl R<u32, Reg<u32, _USB_CTRL>>

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pub fn reserved31(&self) -> RESERVED31_R

Bits 1:31

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pub fn usb_edge_ctl(&self) -> USB_EDGE_CTL_R

Bit 0 - 0:0] Used to set the edge which triggers the USB power up interrupt 0: Rising 1: Falling

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Bit 0 - 0:0] Port A bit 0 interrupt enable: 1: Enabled 2: Disabled

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Bit 0 - 0:0] Port A bit 0 masked interrupt status: 1: Detected 0: Not detected

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impl R<u32, Reg<u32, _USB_IRQ_ACK>>

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pub fn reserved31(&self) -> RESERVED31_R

Bits 1:31

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pub fn usback(&self) -> USBACK_R

Bit 0 - 0:0] USB masked interrupt status: 1: Detected 0: Not detected

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impl R<u32, Reg<u32, _GPIOLOCK>>

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pub fn lock(&self) -> LOCK_R

Bits 0:31 - 31:0] A read of this register returns the following values: Locked: 0x00000001 Unlocked: 0x00000000

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impl R<u32, Reg<u32, _GPIOCR>>

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pub fn reserved32(&self) -> RESERVED32_R

Bits 8:31 - 31:8] Reserved bits return an indeterminate value, and should never be changed.

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pub fn cr(&self) -> CR_R

Bits 0:7 - 7:0] On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function.

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impl R<u32, Reg<u32, _USB_CTRL>>

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pub fn reserved31(&self) -> RESERVED31_R

Bits 1:31

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pub fn usb_edge_ctl(&self) -> USB_EDGE_CTL_R

Bit 0 - 0:0] Used to set the edge which triggers the USB power up interrupt 0: Rising 1: Falling

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Bit 0 - 0:0] Port A bit 0 interrupt enable: 1: Enabled 2: Disabled

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Bit 0 - 0:0] Port A bit 0 masked interrupt status: 1: Detected 0: Not detected

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impl R<u32, Reg<u32, _USB_IRQ_ACK>>

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pub fn reserved31(&self) -> RESERVED31_R

Bits 1:31

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pub fn usback(&self) -> USBACK_R

Bit 0 - 0:0] USB masked interrupt status: 1: Detected 0: Not detected

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Bit 0 - 0:0] Port A bit 0 unmasked interrupt status: 1: Detected 0: Undetected

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Bit 0 - 0:0] Master enable status 0: The uDMA controller is disabled. 1: The uDMA controller is enabled.

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impl R<u32, Reg<u32, _CFG>>

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pub fn reserved31(&self) -> RESERVED31_R

Bits 1:31 - 31:1] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn masten(&self) -> MASTEN_R

Bit 0 - 0:0] Controller master enable 0: Disables the uDMA controller. 1: Enables the uDMA controller.

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impl R<u32, Reg<u32, _CTLBASE>>

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pub fn addr(&self) -> ADDR_R

Bits 0:3 - 3:0] uDMA channel 8 source select See section titled “Channel Assignments” in Micro Direct Memory Access chapter.

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Bits 0:3 - 3:0] uDMA channel 16 source select See section titled “Channel Assignments” in Micro Direct Memory Access chapter.

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Bits 0:3 - 3:0] uDMA channel 24 source select See section titled “Channel Assignments” in Micro Direct Memory Access chapter.

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Bit 9 - 9:9] UART1 test mode enable

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pub fn uart0tme(&self) -> UART0TME_R

Bit 8 - 8:8] UART0 test mode enable

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pub fn reserved2(&self) -> RESERVED2_R

Bits 0:7 - 7:0] Reserved

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pub fn reserved1(&self) -> RESERVED1_R

Bits 9:31 - 31:9] Reserved

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pub fn gptidoe(&self) -> GPTIDOE_R

Bit 8 - 8:8] GPTimer increment/decrement override enable

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pub fn reserved2(&self) -> RESERVED2_R

Bits 5:7 - 7:5] Reserved

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pub fn sequencer_status(&self) -> SEQUENCER_STATUS_R

Bits 8:15 - 15:8] These read-only bits can be used by the sequencer to communicate status to the outside world. Bit [8] is also used as sequencer interrupt, with the complement of this bit ORed into the run bit in PKA_FUNCTION. This field should always be written with zeroes and ignored when reading this register.

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pub fn sw_control_status(&self) -> SW_CONTROL_STATUS_R

Bits 0:7 - 7:0] These bits can be used by software to trigger sequencer operations. External logic can set these bits by writing 1b, cannot reset them by writing 0b. The sequencer can reset these bits by writing 0b, cannot set them by writing 1b. Setting the run bit in PKA_FUNCTION together with a nonzero sequencer operations field automatically sets bit [0] here. This field should always be written with zeroes and ignored when reading this register.

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pub fn fw_capabilities(&self) -> FW_CAPABILITIES_R

Bits 28:31 - 31:28] 4-bit binary encoding for the functionality implemented in the firmware. Value 0 indicates basic ModExp with/without CRT. Value 1 adds Modular Inversion, value 2 adds Modular Inversion and ECC operations. Values 3-15 are reserved.

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pub fn major_fw_revision(&self) -> MAJOR_FW_REVISION_R

Bits 24:27 - 27:24] 4-bit binary encoding of the major firmware revision number

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pub fn minor_fw_revision(&self) -> MINOR_FW_REVISION_R

Bits 20:23 - 23:20] 4-bit binary encoding of the minor firmware revision number

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pub fn fw_patch_level(&self) -> FW_PATCH_LEVEL_R

Bits 16:19 - 19:16] 4-bit binary encoding of the firmware patch level, initial release will carry value zero Patches are used to remove bugs without changing the functionality or interface of a module.

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Bit 2 - 2:2] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

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pub fn adctm(&self) -> ADCTM_R

Bit 1 - 1:1] Set to 1 to connect the temperature sensor to the SOC_ADC. See also RFCORE_XREG_ATEST register description to enable the temperature sensor.

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pub fn reserved0(&self) -> RESERVED0_R

Bit 0 - 0:0] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

impl<T, U> TryFrom for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.

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fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

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impl<T, U> TryInto for T
where U: TryFrom<T>,

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type Error = >::Error

The type returned in the event of a conversion error.

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fn try_into(self) -> Result<U, >::Error>

Performs the conversion.

R

Struct R Copy item path

Implementations§

impl<U, T> R<U, T>where U: Copy,

pub fn bits(&self) -> U

impl<FI> R<bool, FI>

pub fn bit(&self) -> bool

pub fn bit_is_clear(&self) -> bool

pub fn bit_is_set(&self) -> bool

impl R<u32, Reg<u32, _CR0>>

pub fn reserved32(&self) -> RESERVED32_R

pub fn scr(&self) -> SCR_R

pub fn sph(&self) -> SPH_R

pub fn spo(&self) -> SPO_R

pub fn frf(&self) -> FRF_R

pub fn dss(&self) -> DSS_R

impl R<u32, Reg<u32, _CR1>>

pub fn reserved32(&self) -> RESERVED32_R

pub fn reserved16(&self) -> RESERVED16_R

pub fn sod(&self) -> SOD_R

pub fn ms(&self) -> MS_R

pub fn sse(&self) -> SSE_R

pub fn lbm(&self) -> LBM_R

impl R<u32, Reg<u32, _DR>>

pub fn reserved32(&self) -> RESERVED32_R

pub fn data(&self) -> DATA_R

impl R<u32, Reg<u32, _SR>>

pub fn reserved32(&self) -> RESERVED32_R

pub fn reserved16(&self) -> RESERVED16_R

pub fn bsy(&self) -> BSY_R

pub fn rff(&self) -> RFF_R

pub fn rne(&self) -> RNE_R

pub fn tnf(&self) -> TNF_R

pub fn tfe(&self) -> TFE_R

impl R<u32, Reg<u32, _CPSR>>

pub fn reserved32(&self) -> RESERVED32_R

pub fn reserved16(&self) -> RESERVED16_R

pub fn cpsdvsr(&self) -> CPSDVSR_R

impl R<u32, Reg<u32, _IM>>

pub fn txim(&self) -> TXIM_R

pub fn rxim(&self) -> RXIM_R

pub fn rtim(&self) -> RTIM_R

pub fn rorim(&self) -> RORIM_R

impl R<u32, Reg<u32, _RIS>>

pub fn reserved32(&self) -> RESERVED32_R

pub fn reserved11(&self) -> RESERVED11_R

pub fn txris(&self) -> TXRIS_R

pub fn rxris(&self) -> RXRIS_R

pub fn rtris(&self) -> RTRIS_R

pub fn rorris(&self) -> RORRIS_R

impl R<u32, Reg<u32, _MIS>>

pub fn reserved32(&self) -> RESERVED32_R

pub fn reserved16(&self) -> RESERVED16_R

pub fn txmis(&self) -> TXMIS_R

pub fn rxmis(&self) -> RXMIS_R

pub fn rtmis(&self) -> RTMIS_R

pub fn rormis(&self) -> RORMIS_R

impl R<u32, Reg<u32, _ICR>>

pub fn reserved32(&self) -> RESERVED32_R

pub fn reserved16(&self) -> RESERVED16_R

pub fn rtic(&self) -> RTIC_R

pub fn roric(&self) -> RORIC_R

impl R<u32, Reg<u32, _DMACTL>>

pub fn txdmae(&self) -> TXDMAE_R

pub fn rxdmae(&self) -> RXDMAE_R

impl R<u32, Reg<u32, _CC>>

pub fn reserved29(&self) -> RESERVED29_R

pub fn cs(&self) -> CS_R

impl R<u32, Reg<u32, _CR0>>

pub fn reserved32(&self) -> RESERVED32_R

pub fn scr(&self) -> SCR_R

pub fn sph(&self) -> SPH_R

pub fn spo(&self) -> SPO_R

pub fn frf(&self) -> FRF_R

pub fn dss(&self) -> DSS_R

impl R<u32, Reg<u32, _CR1>>

pub fn reserved32(&self) -> RESERVED32_R

pub fn reserved16(&self) -> RESERVED16_R

pub fn sod(&self) -> SOD_R

pub fn ms(&self) -> MS_R

Struct R

impl<U, T> R<U, T>
where U: Copy,