cc2538/rfcore_sfr/
mtctrl.rs1#[doc = "Reader of register MTCTRL"]
2pub type R = crate::R<u32, super::MTCTRL>;
3#[doc = "Writer for register MTCTRL"]
4pub type W = crate::W<u32, super::MTCTRL>;
5#[doc = "Register MTCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::MTCTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `Reserved32`"]
14pub type RESERVED32_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `Reserved32`"]
16pub struct RESERVED32_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> RESERVED32_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u32) -> &'a mut W {
23 self.w.bits = (self.w.bits & !(0x00ff_ffff << 8)) | (((value as u32) & 0x00ff_ffff) << 8);
24 self.w
25 }
26}
27#[doc = "Reader of field `Reserved8`"]
28pub type RESERVED8_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `Reserved8`"]
30pub struct RESERVED8_W<'a> {
31 w: &'a mut W,
32}
33impl<'a> RESERVED8_W<'a> {
34 #[doc = r"Writes raw bits to the field"]
35 #[inline(always)]
36 pub unsafe fn bits(self, value: u8) -> &'a mut W {
37 self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
38 self.w
39 }
40}
41#[doc = "Reader of field `LATCH_MODE`"]
42pub type LATCH_MODE_R = crate::R<bool, bool>;
43#[doc = "Write proxy for field `LATCH_MODE`"]
44pub struct LATCH_MODE_W<'a> {
45 w: &'a mut W,
46}
47impl<'a> LATCH_MODE_W<'a> {
48 #[doc = r"Sets the field bit"]
49 #[inline(always)]
50 pub fn set_bit(self) -> &'a mut W {
51 self.bit(true)
52 }
53 #[doc = r"Clears the field bit"]
54 #[inline(always)]
55 pub fn clear_bit(self) -> &'a mut W {
56 self.bit(false)
57 }
58 #[doc = r"Writes raw bits to the field"]
59 #[inline(always)]
60 pub fn bit(self, value: bool) -> &'a mut W {
61 self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
62 self.w
63 }
64}
65#[doc = "Reader of field `STATE`"]
66pub type STATE_R = crate::R<bool, bool>;
67#[doc = "Write proxy for field `STATE`"]
68pub struct STATE_W<'a> {
69 w: &'a mut W,
70}
71impl<'a> STATE_W<'a> {
72 #[doc = r"Sets the field bit"]
73 #[inline(always)]
74 pub fn set_bit(self) -> &'a mut W {
75 self.bit(true)
76 }
77 #[doc = r"Clears the field bit"]
78 #[inline(always)]
79 pub fn clear_bit(self) -> &'a mut W {
80 self.bit(false)
81 }
82 #[doc = r"Writes raw bits to the field"]
83 #[inline(always)]
84 pub fn bit(self, value: bool) -> &'a mut W {
85 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
86 self.w
87 }
88}
89#[doc = "Reader of field `SYNC`"]
90pub type SYNC_R = crate::R<bool, bool>;
91#[doc = "Write proxy for field `SYNC`"]
92pub struct SYNC_W<'a> {
93 w: &'a mut W,
94}
95impl<'a> SYNC_W<'a> {
96 #[doc = r"Sets the field bit"]
97 #[inline(always)]
98 pub fn set_bit(self) -> &'a mut W {
99 self.bit(true)
100 }
101 #[doc = r"Clears the field bit"]
102 #[inline(always)]
103 pub fn clear_bit(self) -> &'a mut W {
104 self.bit(false)
105 }
106 #[doc = r"Writes raw bits to the field"]
107 #[inline(always)]
108 pub fn bit(self, value: bool) -> &'a mut W {
109 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
110 self.w
111 }
112}
113#[doc = "Reader of field `RUN`"]
114pub type RUN_R = crate::R<bool, bool>;
115#[doc = "Write proxy for field `RUN`"]
116pub struct RUN_W<'a> {
117 w: &'a mut W,
118}
119impl<'a> RUN_W<'a> {
120 #[doc = r"Sets the field bit"]
121 #[inline(always)]
122 pub fn set_bit(self) -> &'a mut W {
123 self.bit(true)
124 }
125 #[doc = r"Clears the field bit"]
126 #[inline(always)]
127 pub fn clear_bit(self) -> &'a mut W {
128 self.bit(false)
129 }
130 #[doc = r"Writes raw bits to the field"]
131 #[inline(always)]
132 pub fn bit(self, value: bool) -> &'a mut W {
133 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
134 self.w
135 }
136}
137impl R {
138 #[doc = "Bits 8:31 - 31:8\\] This register is 8 bits in a 32-bit address space."]
139 #[inline(always)]
140 pub fn reserved32(&self) -> RESERVED32_R {
141 RESERVED32_R::new(((self.bits >> 8) & 0x00ff_ffff) as u32)
142 }
143 #[doc = "Bits 4:7 - 7:4\\] Reserved. Always read 0."]
144 #[inline(always)]
145 pub fn reserved8(&self) -> RESERVED8_R {
146 RESERVED8_R::new(((self.bits >> 4) & 0x0f) as u8)
147 }
148 #[doc = "Bit 3 - 3:3\\] 0: Reading MTM0 with MTMSEL.MTMSEL = 000 latches the high byte of the timer, making it ready to be read from MTM1. Reading MTMOVF0 with MTMSEL.MTMOVFSEL = 000 latches the two most-significant bytes of the overflow counter, making it possible to read these from MTMOVF1 and MTMOVF2. 1: Reading MTM0 with MTMSEL.MTMSEL = 000 latches the high byte of the timer and the entire overflow counter at once, making it possible to read the values from MTM1, MTMOVF0, MTMOVF1, and MTMOVF2."]
149 #[inline(always)]
150 pub fn latch_mode(&self) -> LATCH_MODE_R {
151 LATCH_MODE_R::new(((self.bits >> 3) & 0x01) != 0)
152 }
153 #[doc = "Bit 2 - 2:2\\] State of MAC Timer 0: Timer idle 1: Timer running"]
154 #[inline(always)]
155 pub fn state(&self) -> STATE_R {
156 STATE_R::new(((self.bits >> 2) & 0x01) != 0)
157 }
158 #[doc = "Bit 1 - 1:1\\] 0: Starting and stopping of timer is immediate; that is, synchronous with clk_rf_32m. 1: Starting and stopping of timer occurs at the first positive edge of the 32-kHz clock. For more details regarding timer start and stop, see Section 22.4."]
159 #[inline(always)]
160 pub fn sync(&self) -> SYNC_R {
161 SYNC_R::new(((self.bits >> 1) & 0x01) != 0)
162 }
163 #[doc = "Bit 0 - 0:0\\] Write 1 to start timer, write 0 to stop timer. When read, it returns the last written value."]
164 #[inline(always)]
165 pub fn run(&self) -> RUN_R {
166 RUN_R::new((self.bits & 0x01) != 0)
167 }
168}
169impl W {
170 #[doc = "Bits 8:31 - 31:8\\] This register is 8 bits in a 32-bit address space."]
171 #[inline(always)]
172 pub fn reserved32(&mut self) -> RESERVED32_W {
173 RESERVED32_W { w: self }
174 }
175 #[doc = "Bits 4:7 - 7:4\\] Reserved. Always read 0."]
176 #[inline(always)]
177 pub fn reserved8(&mut self) -> RESERVED8_W {
178 RESERVED8_W { w: self }
179 }
180 #[doc = "Bit 3 - 3:3\\] 0: Reading MTM0 with MTMSEL.MTMSEL = 000 latches the high byte of the timer, making it ready to be read from MTM1. Reading MTMOVF0 with MTMSEL.MTMOVFSEL = 000 latches the two most-significant bytes of the overflow counter, making it possible to read these from MTMOVF1 and MTMOVF2. 1: Reading MTM0 with MTMSEL.MTMSEL = 000 latches the high byte of the timer and the entire overflow counter at once, making it possible to read the values from MTM1, MTMOVF0, MTMOVF1, and MTMOVF2."]
181 #[inline(always)]
182 pub fn latch_mode(&mut self) -> LATCH_MODE_W {
183 LATCH_MODE_W { w: self }
184 }
185 #[doc = "Bit 2 - 2:2\\] State of MAC Timer 0: Timer idle 1: Timer running"]
186 #[inline(always)]
187 pub fn state(&mut self) -> STATE_W {
188 STATE_W { w: self }
189 }
190 #[doc = "Bit 1 - 1:1\\] 0: Starting and stopping of timer is immediate; that is, synchronous with clk_rf_32m. 1: Starting and stopping of timer occurs at the first positive edge of the 32-kHz clock. For more details regarding timer start and stop, see Section 22.4."]
191 #[inline(always)]
192 pub fn sync(&mut self) -> SYNC_W {
193 SYNC_W { w: self }
194 }
195 #[doc = "Bit 0 - 0:0\\] Write 1 to start timer, write 0 to stop timer. When read, it returns the last written value."]
196 #[inline(always)]
197 pub fn run(&mut self) -> RUN_W {
198 RUN_W { w: self }
199 }
200}