1#[doc = "Reader of register FR"]
2pub type R = crate::R<u32, super::FR>;
3#[doc = "Writer for register FR"]
4pub type W = crate::W<u32, super::FR>;
5#[doc = "Register FR `reset()`'s with value 0"]
6impl crate::ResetValue for super::FR {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `Reserved24`"]
14pub type RESERVED24_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `Reserved24`"]
16pub struct RESERVED24_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> RESERVED24_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u32) -> &'a mut W {
23 self.w.bits = (self.w.bits & !(0x00ff_ffff << 8)) | (((value as u32) & 0x00ff_ffff) << 8);
24 self.w
25 }
26}
27#[doc = "Reader of field `TXFE`"]
28pub type TXFE_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `TXFE`"]
30pub struct TXFE_W<'a> {
31 w: &'a mut W,
32}
33impl<'a> TXFE_W<'a> {
34 #[doc = r"Sets the field bit"]
35 #[inline(always)]
36 pub fn set_bit(self) -> &'a mut W {
37 self.bit(true)
38 }
39 #[doc = r"Clears the field bit"]
40 #[inline(always)]
41 pub fn clear_bit(self) -> &'a mut W {
42 self.bit(false)
43 }
44 #[doc = r"Writes raw bits to the field"]
45 #[inline(always)]
46 pub fn bit(self, value: bool) -> &'a mut W {
47 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
48 self.w
49 }
50}
51#[doc = "Reader of field `RXFF`"]
52pub type RXFF_R = crate::R<bool, bool>;
53#[doc = "Write proxy for field `RXFF`"]
54pub struct RXFF_W<'a> {
55 w: &'a mut W,
56}
57impl<'a> RXFF_W<'a> {
58 #[doc = r"Sets the field bit"]
59 #[inline(always)]
60 pub fn set_bit(self) -> &'a mut W {
61 self.bit(true)
62 }
63 #[doc = r"Clears the field bit"]
64 #[inline(always)]
65 pub fn clear_bit(self) -> &'a mut W {
66 self.bit(false)
67 }
68 #[doc = r"Writes raw bits to the field"]
69 #[inline(always)]
70 pub fn bit(self, value: bool) -> &'a mut W {
71 self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
72 self.w
73 }
74}
75#[doc = "Reader of field `TXFF`"]
76pub type TXFF_R = crate::R<bool, bool>;
77#[doc = "Write proxy for field `TXFF`"]
78pub struct TXFF_W<'a> {
79 w: &'a mut W,
80}
81impl<'a> TXFF_W<'a> {
82 #[doc = r"Sets the field bit"]
83 #[inline(always)]
84 pub fn set_bit(self) -> &'a mut W {
85 self.bit(true)
86 }
87 #[doc = r"Clears the field bit"]
88 #[inline(always)]
89 pub fn clear_bit(self) -> &'a mut W {
90 self.bit(false)
91 }
92 #[doc = r"Writes raw bits to the field"]
93 #[inline(always)]
94 pub fn bit(self, value: bool) -> &'a mut W {
95 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
96 self.w
97 }
98}
99#[doc = "Reader of field `RXFE`"]
100pub type RXFE_R = crate::R<bool, bool>;
101#[doc = "Write proxy for field `RXFE`"]
102pub struct RXFE_W<'a> {
103 w: &'a mut W,
104}
105impl<'a> RXFE_W<'a> {
106 #[doc = r"Sets the field bit"]
107 #[inline(always)]
108 pub fn set_bit(self) -> &'a mut W {
109 self.bit(true)
110 }
111 #[doc = r"Clears the field bit"]
112 #[inline(always)]
113 pub fn clear_bit(self) -> &'a mut W {
114 self.bit(false)
115 }
116 #[doc = r"Writes raw bits to the field"]
117 #[inline(always)]
118 pub fn bit(self, value: bool) -> &'a mut W {
119 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
120 self.w
121 }
122}
123#[doc = "Reader of field `BUSY`"]
124pub type BUSY_R = crate::R<bool, bool>;
125#[doc = "Write proxy for field `BUSY`"]
126pub struct BUSY_W<'a> {
127 w: &'a mut W,
128}
129impl<'a> BUSY_W<'a> {
130 #[doc = r"Sets the field bit"]
131 #[inline(always)]
132 pub fn set_bit(self) -> &'a mut W {
133 self.bit(true)
134 }
135 #[doc = r"Clears the field bit"]
136 #[inline(always)]
137 pub fn clear_bit(self) -> &'a mut W {
138 self.bit(false)
139 }
140 #[doc = r"Writes raw bits to the field"]
141 #[inline(always)]
142 pub fn bit(self, value: bool) -> &'a mut W {
143 self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
144 self.w
145 }
146}
147#[doc = "Reader of field `Reserved2`"]
148pub type RESERVED2_R = crate::R<u8, u8>;
149#[doc = "Write proxy for field `Reserved2`"]
150pub struct RESERVED2_W<'a> {
151 w: &'a mut W,
152}
153impl<'a> RESERVED2_W<'a> {
154 #[doc = r"Writes raw bits to the field"]
155 #[inline(always)]
156 pub unsafe fn bits(self, value: u8) -> &'a mut W {
157 self.w.bits = (self.w.bits & !(0x03 << 1)) | (((value as u32) & 0x03) << 1);
158 self.w
159 }
160}
161#[doc = "Reader of field `CTS`"]
162pub type CTS_R = crate::R<bool, bool>;
163#[doc = "Write proxy for field `CTS`"]
164pub struct CTS_W<'a> {
165 w: &'a mut W,
166}
167impl<'a> CTS_W<'a> {
168 #[doc = r"Sets the field bit"]
169 #[inline(always)]
170 pub fn set_bit(self) -> &'a mut W {
171 self.bit(true)
172 }
173 #[doc = r"Clears the field bit"]
174 #[inline(always)]
175 pub fn clear_bit(self) -> &'a mut W {
176 self.bit(false)
177 }
178 #[doc = r"Writes raw bits to the field"]
179 #[inline(always)]
180 pub fn bit(self, value: bool) -> &'a mut W {
181 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
182 self.w
183 }
184}
185impl R {
186 #[doc = "Bits 8:31 - 31:8\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."]
187 #[inline(always)]
188 pub fn reserved24(&self) -> RESERVED24_R {
189 RESERVED24_R::new(((self.bits >> 8) & 0x00ff_ffff) as u32)
190 }
191 #[doc = "Bit 7 - 7:7\\] UART transmit FIFO empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 1: If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. 0: The transmitter has data to transmit."]
192 #[inline(always)]
193 pub fn txfe(&self) -> TXFE_R {
194 TXFE_R::new(((self.bits >> 7) & 0x01) != 0)
195 }
196 #[doc = "Bit 6 - 6:6\\] UART receive FIFO full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 1: If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. 0: The receiver can receive data."]
197 #[inline(always)]
198 pub fn rxff(&self) -> RXFF_R {
199 RXFF_R::new(((self.bits >> 6) & 0x01) != 0)
200 }
201 #[doc = "Bit 5 - 5:5\\] UART transmit FIFO full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 1: If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0: The transmitter is not full."]
202 #[inline(always)]
203 pub fn txff(&self) -> TXFF_R {
204 TXFF_R::new(((self.bits >> 5) & 0x01) != 0)
205 }
206 #[doc = "Bit 4 - 4:4\\] UART receive FIFO empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 1: If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. 0: The receiver is not empty."]
207 #[inline(always)]
208 pub fn rxfe(&self) -> RXFE_R {
209 RXFE_R::new(((self.bits >> 4) & 0x01) != 0)
210 }
211 #[doc = "Bit 3 - 3:3\\] UART busy 1: The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. 0: The UART is not busy. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled)."]
212 #[inline(always)]
213 pub fn busy(&self) -> BUSY_R {
214 BUSY_R::new(((self.bits >> 3) & 0x01) != 0)
215 }
216 #[doc = "Bits 1:2 - 2:1\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."]
217 #[inline(always)]
218 pub fn reserved2(&self) -> RESERVED2_R {
219 RESERVED2_R::new(((self.bits >> 1) & 0x03) as u8)
220 }
221 #[doc = "Bit 0 - 0:0\\] Clear to send (UART1 only, reserved for UART0). 1: The U1CTS signal is asserted. 0: The U1CTS signal is not asserted."]
222 #[inline(always)]
223 pub fn cts(&self) -> CTS_R {
224 CTS_R::new((self.bits & 0x01) != 0)
225 }
226}
227impl W {
228 #[doc = "Bits 8:31 - 31:8\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."]
229 #[inline(always)]
230 pub fn reserved24(&mut self) -> RESERVED24_W {
231 RESERVED24_W { w: self }
232 }
233 #[doc = "Bit 7 - 7:7\\] UART transmit FIFO empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 1: If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. 0: The transmitter has data to transmit."]
234 #[inline(always)]
235 pub fn txfe(&mut self) -> TXFE_W {
236 TXFE_W { w: self }
237 }
238 #[doc = "Bit 6 - 6:6\\] UART receive FIFO full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 1: If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. 0: The receiver can receive data."]
239 #[inline(always)]
240 pub fn rxff(&mut self) -> RXFF_W {
241 RXFF_W { w: self }
242 }
243 #[doc = "Bit 5 - 5:5\\] UART transmit FIFO full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 1: If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0: The transmitter is not full."]
244 #[inline(always)]
245 pub fn txff(&mut self) -> TXFF_W {
246 TXFF_W { w: self }
247 }
248 #[doc = "Bit 4 - 4:4\\] UART receive FIFO empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. 1: If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. 0: The receiver is not empty."]
249 #[inline(always)]
250 pub fn rxfe(&mut self) -> RXFE_W {
251 RXFE_W { w: self }
252 }
253 #[doc = "Bit 3 - 3:3\\] UART busy 1: The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. 0: The UART is not busy. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled)."]
254 #[inline(always)]
255 pub fn busy(&mut self) -> BUSY_W {
256 BUSY_W { w: self }
257 }
258 #[doc = "Bits 1:2 - 2:1\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."]
259 #[inline(always)]
260 pub fn reserved2(&mut self) -> RESERVED2_W {
261 RESERVED2_W { w: self }
262 }
263 #[doc = "Bit 0 - 0:0\\] Clear to send (UART1 only, reserved for UART0). 1: The U1CTS signal is asserted. 0: The U1CTS signal is not asserted."]
264 #[inline(always)]
265 pub fn cts(&mut self) -> CTS_W {
266 CTS_W { w: self }
267 }
268}