1#[doc = "Reader of register IWE"]
2pub type R = crate::R<u32, super::IWE>;
3#[doc = "Writer for register IWE"]
4pub type W = crate::W<u32, super::IWE>;
5#[doc = "Register IWE `reset()`'s with value 0"]
6impl crate::ResetValue for super::IWE {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `Reserved32`"]
14pub type RESERVED32_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `Reserved32`"]
16pub struct RESERVED32_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> RESERVED32_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u32) -> &'a mut W {
23 self.w.bits = (self.w.bits & !(0x03ff_ffff << 6)) | (((value as u32) & 0x03ff_ffff) << 6);
24 self.w
25 }
26}
27#[doc = "Reader of field `SM_TIMER_IWE`"]
28pub type SM_TIMER_IWE_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `SM_TIMER_IWE`"]
30pub struct SM_TIMER_IWE_W<'a> {
31 w: &'a mut W,
32}
33impl<'a> SM_TIMER_IWE_W<'a> {
34 #[doc = r"Sets the field bit"]
35 #[inline(always)]
36 pub fn set_bit(self) -> &'a mut W {
37 self.bit(true)
38 }
39 #[doc = r"Clears the field bit"]
40 #[inline(always)]
41 pub fn clear_bit(self) -> &'a mut W {
42 self.bit(false)
43 }
44 #[doc = r"Writes raw bits to the field"]
45 #[inline(always)]
46 pub fn bit(self, value: bool) -> &'a mut W {
47 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
48 self.w
49 }
50}
51#[doc = "Reader of field `USB_IWE`"]
52pub type USB_IWE_R = crate::R<bool, bool>;
53#[doc = "Write proxy for field `USB_IWE`"]
54pub struct USB_IWE_W<'a> {
55 w: &'a mut W,
56}
57impl<'a> USB_IWE_W<'a> {
58 #[doc = r"Sets the field bit"]
59 #[inline(always)]
60 pub fn set_bit(self) -> &'a mut W {
61 self.bit(true)
62 }
63 #[doc = r"Clears the field bit"]
64 #[inline(always)]
65 pub fn clear_bit(self) -> &'a mut W {
66 self.bit(false)
67 }
68 #[doc = r"Writes raw bits to the field"]
69 #[inline(always)]
70 pub fn bit(self, value: bool) -> &'a mut W {
71 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
72 self.w
73 }
74}
75#[doc = "Reader of field `PORT_D_IWE`"]
76pub type PORT_D_IWE_R = crate::R<bool, bool>;
77#[doc = "Write proxy for field `PORT_D_IWE`"]
78pub struct PORT_D_IWE_W<'a> {
79 w: &'a mut W,
80}
81impl<'a> PORT_D_IWE_W<'a> {
82 #[doc = r"Sets the field bit"]
83 #[inline(always)]
84 pub fn set_bit(self) -> &'a mut W {
85 self.bit(true)
86 }
87 #[doc = r"Clears the field bit"]
88 #[inline(always)]
89 pub fn clear_bit(self) -> &'a mut W {
90 self.bit(false)
91 }
92 #[doc = r"Writes raw bits to the field"]
93 #[inline(always)]
94 pub fn bit(self, value: bool) -> &'a mut W {
95 self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
96 self.w
97 }
98}
99#[doc = "Reader of field `PORT_C_IWE`"]
100pub type PORT_C_IWE_R = crate::R<bool, bool>;
101#[doc = "Write proxy for field `PORT_C_IWE`"]
102pub struct PORT_C_IWE_W<'a> {
103 w: &'a mut W,
104}
105impl<'a> PORT_C_IWE_W<'a> {
106 #[doc = r"Sets the field bit"]
107 #[inline(always)]
108 pub fn set_bit(self) -> &'a mut W {
109 self.bit(true)
110 }
111 #[doc = r"Clears the field bit"]
112 #[inline(always)]
113 pub fn clear_bit(self) -> &'a mut W {
114 self.bit(false)
115 }
116 #[doc = r"Writes raw bits to the field"]
117 #[inline(always)]
118 pub fn bit(self, value: bool) -> &'a mut W {
119 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
120 self.w
121 }
122}
123#[doc = "Reader of field `PORT_B_IWE`"]
124pub type PORT_B_IWE_R = crate::R<bool, bool>;
125#[doc = "Write proxy for field `PORT_B_IWE`"]
126pub struct PORT_B_IWE_W<'a> {
127 w: &'a mut W,
128}
129impl<'a> PORT_B_IWE_W<'a> {
130 #[doc = r"Sets the field bit"]
131 #[inline(always)]
132 pub fn set_bit(self) -> &'a mut W {
133 self.bit(true)
134 }
135 #[doc = r"Clears the field bit"]
136 #[inline(always)]
137 pub fn clear_bit(self) -> &'a mut W {
138 self.bit(false)
139 }
140 #[doc = r"Writes raw bits to the field"]
141 #[inline(always)]
142 pub fn bit(self, value: bool) -> &'a mut W {
143 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
144 self.w
145 }
146}
147#[doc = "Reader of field `PORT_A_IWE`"]
148pub type PORT_A_IWE_R = crate::R<bool, bool>;
149#[doc = "Write proxy for field `PORT_A_IWE`"]
150pub struct PORT_A_IWE_W<'a> {
151 w: &'a mut W,
152}
153impl<'a> PORT_A_IWE_W<'a> {
154 #[doc = r"Sets the field bit"]
155 #[inline(always)]
156 pub fn set_bit(self) -> &'a mut W {
157 self.bit(true)
158 }
159 #[doc = r"Clears the field bit"]
160 #[inline(always)]
161 pub fn clear_bit(self) -> &'a mut W {
162 self.bit(false)
163 }
164 #[doc = r"Writes raw bits to the field"]
165 #[inline(always)]
166 pub fn bit(self, value: bool) -> &'a mut W {
167 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
168 self.w
169 }
170}
171impl R {
172 #[doc = "Bits 6:31 - 31:6\\] This register is 8 bits in a 32-bit address space."]
173 #[inline(always)]
174 pub fn reserved32(&self) -> RESERVED32_R {
175 RESERVED32_R::new(((self.bits >> 6) & 0x03ff_ffff) as u32)
176 }
177 #[doc = "Bit 5 - 5:5\\] 1: Enable SM Timer wake-up interrupt. 0: Disable SM Timer wake-up interrupt."]
178 #[inline(always)]
179 pub fn sm_timer_iwe(&self) -> SM_TIMER_IWE_R {
180 SM_TIMER_IWE_R::new(((self.bits >> 5) & 0x01) != 0)
181 }
182 #[doc = "Bit 4 - 4:4\\] 1: Enable USB wake-up interrupt. 0: Disable USB wake-up interrupt."]
183 #[inline(always)]
184 pub fn usb_iwe(&self) -> USB_IWE_R {
185 USB_IWE_R::new(((self.bits >> 4) & 0x01) != 0)
186 }
187 #[doc = "Bit 3 - 3:3\\] 1: Enable port D wake-up interrupt. 0: Disable port D wake-up interrupt."]
188 #[inline(always)]
189 pub fn port_d_iwe(&self) -> PORT_D_IWE_R {
190 PORT_D_IWE_R::new(((self.bits >> 3) & 0x01) != 0)
191 }
192 #[doc = "Bit 2 - 2:2\\] 1: Enable port C wake-up interrupt. 0: Disable port C wake-up interrupt."]
193 #[inline(always)]
194 pub fn port_c_iwe(&self) -> PORT_C_IWE_R {
195 PORT_C_IWE_R::new(((self.bits >> 2) & 0x01) != 0)
196 }
197 #[doc = "Bit 1 - 1:1\\] 1: Enable port B wake-up interrupt. 0: Disable port B wake-up interrupt."]
198 #[inline(always)]
199 pub fn port_b_iwe(&self) -> PORT_B_IWE_R {
200 PORT_B_IWE_R::new(((self.bits >> 1) & 0x01) != 0)
201 }
202 #[doc = "Bit 0 - 0:0\\] 1: Enable port A wake-up interrupt. 0: Disable port A wake-up interrupt."]
203 #[inline(always)]
204 pub fn port_a_iwe(&self) -> PORT_A_IWE_R {
205 PORT_A_IWE_R::new((self.bits & 0x01) != 0)
206 }
207}
208impl W {
209 #[doc = "Bits 6:31 - 31:6\\] This register is 8 bits in a 32-bit address space."]
210 #[inline(always)]
211 pub fn reserved32(&mut self) -> RESERVED32_W {
212 RESERVED32_W { w: self }
213 }
214 #[doc = "Bit 5 - 5:5\\] 1: Enable SM Timer wake-up interrupt. 0: Disable SM Timer wake-up interrupt."]
215 #[inline(always)]
216 pub fn sm_timer_iwe(&mut self) -> SM_TIMER_IWE_W {
217 SM_TIMER_IWE_W { w: self }
218 }
219 #[doc = "Bit 4 - 4:4\\] 1: Enable USB wake-up interrupt. 0: Disable USB wake-up interrupt."]
220 #[inline(always)]
221 pub fn usb_iwe(&mut self) -> USB_IWE_W {
222 USB_IWE_W { w: self }
223 }
224 #[doc = "Bit 3 - 3:3\\] 1: Enable port D wake-up interrupt. 0: Disable port D wake-up interrupt."]
225 #[inline(always)]
226 pub fn port_d_iwe(&mut self) -> PORT_D_IWE_W {
227 PORT_D_IWE_W { w: self }
228 }
229 #[doc = "Bit 2 - 2:2\\] 1: Enable port C wake-up interrupt. 0: Disable port C wake-up interrupt."]
230 #[inline(always)]
231 pub fn port_c_iwe(&mut self) -> PORT_C_IWE_W {
232 PORT_C_IWE_W { w: self }
233 }
234 #[doc = "Bit 1 - 1:1\\] 1: Enable port B wake-up interrupt. 0: Disable port B wake-up interrupt."]
235 #[inline(always)]
236 pub fn port_b_iwe(&mut self) -> PORT_B_IWE_W {
237 PORT_B_IWE_W { w: self }
238 }
239 #[doc = "Bit 0 - 0:0\\] 1: Enable port A wake-up interrupt. 0: Disable port A wake-up interrupt."]
240 #[inline(always)]
241 pub fn port_a_iwe(&mut self) -> PORT_A_IWE_W {
242 PORT_A_IWE_W { w: self }
243 }
244}