cc2538/ssi1/
cpsr.rs

1#[doc = "Reader of register CPSR"]
2pub type R = crate::R<u32, super::CPSR>;
3#[doc = "Writer for register CPSR"]
4pub type W = crate::W<u32, super::CPSR>;
5#[doc = "Register CPSR `reset()`'s with value 0"]
6impl crate::ResetValue for super::CPSR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `Reserved32`"]
14pub type RESERVED32_R = crate::R<u16, u16>;
15#[doc = "Write proxy for field `Reserved32`"]
16pub struct RESERVED32_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RESERVED32_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u16) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
24        self.w
25    }
26}
27#[doc = "Reader of field `Reserved16`"]
28pub type RESERVED16_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `Reserved16`"]
30pub struct RESERVED16_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> RESERVED16_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
38        self.w
39    }
40}
41#[doc = "Reader of field `CPSDVSR`"]
42pub type CPSDVSR_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `CPSDVSR`"]
44pub struct CPSDVSR_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> CPSDVSR_W<'a> {
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub unsafe fn bits(self, value: u8) -> &'a mut W {
51        self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
52        self.w
53    }
54}
55impl R {
56    #[doc = "Bits 16:31 - 31:16\\] Reserved"]
57    #[inline(always)]
58    pub fn reserved32(&self) -> RESERVED32_R {
59        RESERVED32_R::new(((self.bits >> 16) & 0xffff) as u16)
60    }
61    #[doc = "Bits 8:15 - 15:8\\] Reserved, read unpredictable, should be written as 0."]
62    #[inline(always)]
63    pub fn reserved16(&self) -> RESERVED16_R {
64        RESERVED16_R::new(((self.bits >> 8) & 0xff) as u8)
65    }
66    #[doc = "Bits 0:7 - 7:0\\] SSI clock prescale divisor (R/W) Reset value: 0x0 This value must be an even number from 2 to 254, depending on the frequency of SSICLK. The LSB always returns zero on reads."]
67    #[inline(always)]
68    pub fn cpsdvsr(&self) -> CPSDVSR_R {
69        CPSDVSR_R::new((self.bits & 0xff) as u8)
70    }
71}
72impl W {
73    #[doc = "Bits 16:31 - 31:16\\] Reserved"]
74    #[inline(always)]
75    pub fn reserved32(&mut self) -> RESERVED32_W {
76        RESERVED32_W { w: self }
77    }
78    #[doc = "Bits 8:15 - 15:8\\] Reserved, read unpredictable, should be written as 0."]
79    #[inline(always)]
80    pub fn reserved16(&mut self) -> RESERVED16_W {
81        RESERVED16_W { w: self }
82    }
83    #[doc = "Bits 0:7 - 7:0\\] SSI clock prescale divisor (R/W) Reset value: 0x0 This value must be an even number from 2 to 254, depending on the frequency of SSICLK. The LSB always returns zero on reads."]
84    #[inline(always)]
85    pub fn cpsdvsr(&mut self) -> CPSDVSR_W {
86        CPSDVSR_W { w: self }
87    }
88}
cc2538/ssi1/cpsr.rs

cc2538/ssi1/
cpsr.rs
