cc2538/rfcore_xreg/
rxenable.rs

1#[doc = "Reader of register RXENABLE"]
2pub type R = crate::R<u32, super::RXENABLE>;
3#[doc = "Writer for register RXENABLE"]
4pub type W = crate::W<u32, super::RXENABLE>;
5#[doc = "Register RXENABLE `reset()`'s with value 0"]
6impl crate::ResetValue for super::RXENABLE {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `Reserved32`"]
14pub type RESERVED32_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `Reserved32`"]
16pub struct RESERVED32_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RESERVED32_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u32) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x00ff_ffff << 8)) | (((value as u32) & 0x00ff_ffff) << 8);
24        self.w
25    }
26}
27#[doc = "Reader of field `RXENMASK`"]
28pub type RXENMASK_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `RXENMASK`"]
30pub struct RXENMASK_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> RXENMASK_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
38        self.w
39    }
40}
41impl R {
42    #[doc = "Bits 8:31 - 31:8\\] This register is 8 bits in a 32-bit address space."]
43    #[inline(always)]
44    pub fn reserved32(&self) -> RESERVED32_R {
45        RESERVED32_R::new(((self.bits >> 8) & 0x00ff_ffff) as u32)
46    }
47    #[doc = "Bits 0:7 - 7:0\\] RXENABLE enables the receiver. A nonzero value in this register causes FFCTRL to enable the receiver when in idle, after transmission and after acknowledgement transmission. The following strobes can modify RXENMASK: SRXON: Set bit 7 in RXENMASK. STXON: Set bit 6 in RXENMASK if SET_RXENMASK_ON_TX = 1. SRFOFF: Clears all bits in RXENMASK. SRXMASKBITSET: Set bit 5 in RXENMASK. SRXMASKBITCLR: Clear bit 5 in RXENMASK. There could be conflicts between the CSP and xreg_bus write operations if both operations try to modify RXENMASK simultaneously. To handle the case of simultaneous access to RXENMASK the following rules apply: - If the two sources agree (they modify different parts of the register) both of their requests to modify RXENMASK are processed. - If both operations try to modify the mask simultaneously, bus write operations to RXMASKSET and RXMASKCLR have priority over the CSP. This situation must be avoided."]
48    #[inline(always)]
49    pub fn rxenmask(&self) -> RXENMASK_R {
50        RXENMASK_R::new((self.bits & 0xff) as u8)
51    }
52}
53impl W {
54    #[doc = "Bits 8:31 - 31:8\\] This register is 8 bits in a 32-bit address space."]
55    #[inline(always)]
56    pub fn reserved32(&mut self) -> RESERVED32_W {
57        RESERVED32_W { w: self }
58    }
59    #[doc = "Bits 0:7 - 7:0\\] RXENABLE enables the receiver. A nonzero value in this register causes FFCTRL to enable the receiver when in idle, after transmission and after acknowledgement transmission. The following strobes can modify RXENMASK: SRXON: Set bit 7 in RXENMASK. STXON: Set bit 6 in RXENMASK if SET_RXENMASK_ON_TX = 1. SRFOFF: Clears all bits in RXENMASK. SRXMASKBITSET: Set bit 5 in RXENMASK. SRXMASKBITCLR: Clear bit 5 in RXENMASK. There could be conflicts between the CSP and xreg_bus write operations if both operations try to modify RXENMASK simultaneously. To handle the case of simultaneous access to RXENMASK the following rules apply: - If the two sources agree (they modify different parts of the register) both of their requests to modify RXENMASK are processed. - If both operations try to modify the mask simultaneously, bus write operations to RXMASKSET and RXMASKCLR have priority over the CSP. This situation must be avoided."]
60    #[inline(always)]
61    pub fn rxenmask(&mut self) -> RXENMASK_W {
62        RXENMASK_W { w: self }
63    }
64}
cc2538/rfcore_xreg/rxenable.rs

cc2538/rfcore_xreg/
rxenable.rs
