cc2538/sys_ctrl/
scgcrfc.rs

1#[doc = "Reader of register SCGCRFC"]
2pub type R = crate::R<u32, super::SCGCRFC>;
3#[doc = "Writer for register SCGCRFC"]
4pub type W = crate::W<u32, super::SCGCRFC>;
5#[doc = "Register SCGCRFC `reset()`'s with value 0"]
6impl crate::ResetValue for super::SCGCRFC {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `Reserved32`"]
14pub type RESERVED32_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `Reserved32`"]
16pub struct RESERVED32_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RESERVED32_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u32) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x7fff_ffff << 1)) | (((value as u32) & 0x7fff_ffff) << 1);
24        self.w
25    }
26}
27#[doc = "Reader of field `RFC0`"]
28pub type RFC0_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `RFC0`"]
30pub struct RFC0_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> RFC0_W<'a> {
34    #[doc = r"Sets the field bit"]
35    #[inline(always)]
36    pub fn set_bit(self) -> &'a mut W {
37        self.bit(true)
38    }
39    #[doc = r"Clears the field bit"]
40    #[inline(always)]
41    pub fn clear_bit(self) -> &'a mut W {
42        self.bit(false)
43    }
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub fn bit(self, value: bool) -> &'a mut W {
47        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
48        self.w
49    }
50}
51impl R {
52    #[doc = "Bits 1:31 - 31:1\\] This register is 8 bits in a 32-bit address space."]
53    #[inline(always)]
54    pub fn reserved32(&self) -> RESERVED32_R {
55        RESERVED32_R::new(((self.bits >> 1) & 0x7fff_ffff) as u32)
56    }
57    #[doc = "Bit 0 - 0:0\\] 0: Clock for RF CORE is gated. 1: Clock for RF CORE is enabled."]
58    #[inline(always)]
59    pub fn rfc0(&self) -> RFC0_R {
60        RFC0_R::new((self.bits & 0x01) != 0)
61    }
62}
63impl W {
64    #[doc = "Bits 1:31 - 31:1\\] This register is 8 bits in a 32-bit address space."]
65    #[inline(always)]
66    pub fn reserved32(&mut self) -> RESERVED32_W {
67        RESERVED32_W { w: self }
68    }
69    #[doc = "Bit 0 - 0:0\\] 0: Clock for RF CORE is gated. 1: Clock for RF CORE is enabled."]
70    #[inline(always)]
71    pub fn rfc0(&mut self) -> RFC0_W {
72        RFC0_W { w: self }
73    }
74}
cc2538/sys_ctrl/scgcrfc.rs

cc2538/sys_ctrl/
scgcrfc.rs
