cc2538/aes/
dmac_ch0_ctrl.rs

1#[doc = "Reader of register DMAC_CH0_CTRL"]
2pub type R = crate::R<u32, super::DMAC_CH0_CTRL>;
3#[doc = "Writer for register DMAC_CH0_CTRL"]
4pub type W = crate::W<u32, super::DMAC_CH0_CTRL>;
5#[doc = "Register DMAC_CH0_CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::DMAC_CH0_CTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `Reserved30`"]
14pub type RESERVED30_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `Reserved30`"]
16pub struct RESERVED30_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RESERVED30_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u32) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x3fff_ffff << 2)) | (((value as u32) & 0x3fff_ffff) << 2);
24        self.w
25    }
26}
27#[doc = "Reader of field `PRIO`"]
28pub type PRIO_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `PRIO`"]
30pub struct PRIO_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> PRIO_W<'a> {
34    #[doc = r"Sets the field bit"]
35    #[inline(always)]
36    pub fn set_bit(self) -> &'a mut W {
37        self.bit(true)
38    }
39    #[doc = r"Clears the field bit"]
40    #[inline(always)]
41    pub fn clear_bit(self) -> &'a mut W {
42        self.bit(false)
43    }
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub fn bit(self, value: bool) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
48        self.w
49    }
50}
51#[doc = "Reader of field `EN`"]
52pub type EN_R = crate::R<bool, bool>;
53#[doc = "Write proxy for field `EN`"]
54pub struct EN_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> EN_W<'a> {
58    #[doc = r"Sets the field bit"]
59    #[inline(always)]
60    pub fn set_bit(self) -> &'a mut W {
61        self.bit(true)
62    }
63    #[doc = r"Clears the field bit"]
64    #[inline(always)]
65    pub fn clear_bit(self) -> &'a mut W {
66        self.bit(false)
67    }
68    #[doc = r"Writes raw bits to the field"]
69    #[inline(always)]
70    pub fn bit(self, value: bool) -> &'a mut W {
71        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
72        self.w
73    }
74}
75impl R {
76    #[doc = "Bits 2:31 - 31:2\\] Should be written with 0s and ignored on read"]
77    #[inline(always)]
78    pub fn reserved30(&self) -> RESERVED30_R {
79        RESERVED30_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32)
80    }
81    #[doc = "Bit 1 - 1:1\\] Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests."]
82    #[inline(always)]
83    pub fn prio(&self) -> PRIO_R {
84        PRIO_R::new(((self.bits >> 1) & 0x01) != 0)
85    }
86    #[doc = "Bit 0 - 0:0\\] Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested."]
87    #[inline(always)]
88    pub fn en(&self) -> EN_R {
89        EN_R::new((self.bits & 0x01) != 0)
90    }
91}
92impl W {
93    #[doc = "Bits 2:31 - 31:2\\] Should be written with 0s and ignored on read"]
94    #[inline(always)]
95    pub fn reserved30(&mut self) -> RESERVED30_W {
96        RESERVED30_W { w: self }
97    }
98    #[doc = "Bit 1 - 1:1\\] Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests."]
99    #[inline(always)]
100    pub fn prio(&mut self) -> PRIO_W {
101        PRIO_W { w: self }
102    }
103    #[doc = "Bit 0 - 0:0\\] Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested."]
104    #[inline(always)]
105    pub fn en(&mut self) -> EN_W {
106        EN_W { w: self }
107    }
108}
cc2538/aes/dmac_ch0_ctrl.rs

cc2538/aes/
dmac_ch0_ctrl.rs
