cc2538/rfcore_xreg/
adctest0.rs

1#[doc = "Reader of register ADCTEST0"]
2pub type R = crate::R<u32, super::ADCTEST0>;
3#[doc = "Writer for register ADCTEST0"]
4pub type W = crate::W<u32, super::ADCTEST0>;
5#[doc = "Register ADCTEST0 `reset()`'s with value 0"]
6impl crate::ResetValue for super::ADCTEST0 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `Reserved32`"]
14pub type RESERVED32_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `Reserved32`"]
16pub struct RESERVED32_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RESERVED32_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u32) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x00ff_ffff << 8)) | (((value as u32) & 0x00ff_ffff) << 8);
24        self.w
25    }
26}
27#[doc = "Reader of field `ADC_VREF_ADJ`"]
28pub type ADC_VREF_ADJ_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `ADC_VREF_ADJ`"]
30pub struct ADC_VREF_ADJ_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> ADC_VREF_ADJ_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
38        self.w
39    }
40}
41#[doc = "Reader of field `ADC_QUANT_ADJ`"]
42pub type ADC_QUANT_ADJ_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `ADC_QUANT_ADJ`"]
44pub struct ADC_QUANT_ADJ_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> ADC_QUANT_ADJ_W<'a> {
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub unsafe fn bits(self, value: u8) -> &'a mut W {
51        self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
52        self.w
53    }
54}
55#[doc = "Reader of field `ADC_GM_ADJ`"]
56pub type ADC_GM_ADJ_R = crate::R<u8, u8>;
57#[doc = "Write proxy for field `ADC_GM_ADJ`"]
58pub struct ADC_GM_ADJ_W<'a> {
59    w: &'a mut W,
60}
61impl<'a> ADC_GM_ADJ_W<'a> {
62    #[doc = r"Writes raw bits to the field"]
63    #[inline(always)]
64    pub unsafe fn bits(self, value: u8) -> &'a mut W {
65        self.w.bits = (self.w.bits & !(0x07 << 1)) | (((value as u32) & 0x07) << 1);
66        self.w
67    }
68}
69#[doc = "Reader of field `ADC_DAC2_EN`"]
70pub type ADC_DAC2_EN_R = crate::R<bool, bool>;
71#[doc = "Write proxy for field `ADC_DAC2_EN`"]
72pub struct ADC_DAC2_EN_W<'a> {
73    w: &'a mut W,
74}
75impl<'a> ADC_DAC2_EN_W<'a> {
76    #[doc = r"Sets the field bit"]
77    #[inline(always)]
78    pub fn set_bit(self) -> &'a mut W {
79        self.bit(true)
80    }
81    #[doc = r"Clears the field bit"]
82    #[inline(always)]
83    pub fn clear_bit(self) -> &'a mut W {
84        self.bit(false)
85    }
86    #[doc = r"Writes raw bits to the field"]
87    #[inline(always)]
88    pub fn bit(self, value: bool) -> &'a mut W {
89        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
90        self.w
91    }
92}
93impl R {
94    #[doc = "Bits 8:31 - 31:8\\] This register is 8 bits in a 32-bit address space."]
95    #[inline(always)]
96    pub fn reserved32(&self) -> RESERVED32_R {
97        RESERVED32_R::new(((self.bits >> 8) & 0x00ff_ffff) as u32)
98    }
99    #[doc = "Bits 6:7 - 7:6\\] Quantizer threshold control for test and debug"]
100    #[inline(always)]
101    pub fn adc_vref_adj(&self) -> ADC_VREF_ADJ_R {
102        ADC_VREF_ADJ_R::new(((self.bits >> 6) & 0x03) as u8)
103    }
104    #[doc = "Bits 4:5 - 5:4\\] Quantizer threshold control for test and debug"]
105    #[inline(always)]
106    pub fn adc_quant_adj(&self) -> ADC_QUANT_ADJ_R {
107        ADC_QUANT_ADJ_R::new(((self.bits >> 4) & 0x03) as u8)
108    }
109    #[doc = "Bits 1:3 - 3:1\\] Gm-control for test and debug"]
110    #[inline(always)]
111    pub fn adc_gm_adj(&self) -> ADC_GM_ADJ_R {
112        ADC_GM_ADJ_R::new(((self.bits >> 1) & 0x07) as u8)
113    }
114    #[doc = "Bit 0 - 0:0\\] Enables DAC2 for enhanced ADC stability"]
115    #[inline(always)]
116    pub fn adc_dac2_en(&self) -> ADC_DAC2_EN_R {
117        ADC_DAC2_EN_R::new((self.bits & 0x01) != 0)
118    }
119}
120impl W {
121    #[doc = "Bits 8:31 - 31:8\\] This register is 8 bits in a 32-bit address space."]
122    #[inline(always)]
123    pub fn reserved32(&mut self) -> RESERVED32_W {
124        RESERVED32_W { w: self }
125    }
126    #[doc = "Bits 6:7 - 7:6\\] Quantizer threshold control for test and debug"]
127    #[inline(always)]
128    pub fn adc_vref_adj(&mut self) -> ADC_VREF_ADJ_W {
129        ADC_VREF_ADJ_W { w: self }
130    }
131    #[doc = "Bits 4:5 - 5:4\\] Quantizer threshold control for test and debug"]
132    #[inline(always)]
133    pub fn adc_quant_adj(&mut self) -> ADC_QUANT_ADJ_W {
134        ADC_QUANT_ADJ_W { w: self }
135    }
136    #[doc = "Bits 1:3 - 3:1\\] Gm-control for test and debug"]
137    #[inline(always)]
138    pub fn adc_gm_adj(&mut self) -> ADC_GM_ADJ_W {
139        ADC_GM_ADJ_W { w: self }
140    }
141    #[doc = "Bit 0 - 0:0\\] Enables DAC2 for enhanced ADC stability"]
142    #[inline(always)]
143    pub fn adc_dac2_en(&mut self) -> ADC_DAC2_EN_W {
144        ADC_DAC2_EN_W { w: self }
145    }
146}
cc2538/rfcore_xreg/adctest0.rs

cc2538/rfcore_xreg/
adctest0.rs
