cc2538/uart0/
dmactl.rs

1#[doc = "Reader of register DMACTL"]
2pub type R = crate::R<u32, super::DMACTL>;
3#[doc = "Writer for register DMACTL"]
4pub type W = crate::W<u32, super::DMACTL>;
5#[doc = "Register DMACTL `reset()`'s with value 0"]
6impl crate::ResetValue for super::DMACTL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `Reserved29`"]
14pub type RESERVED29_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `Reserved29`"]
16pub struct RESERVED29_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RESERVED29_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u32) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x1fff_ffff << 3)) | (((value as u32) & 0x1fff_ffff) << 3);
24        self.w
25    }
26}
27#[doc = "Reader of field `DMAERR`"]
28pub type DMAERR_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `DMAERR`"]
30pub struct DMAERR_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> DMAERR_W<'a> {
34    #[doc = r"Sets the field bit"]
35    #[inline(always)]
36    pub fn set_bit(self) -> &'a mut W {
37        self.bit(true)
38    }
39    #[doc = r"Clears the field bit"]
40    #[inline(always)]
41    pub fn clear_bit(self) -> &'a mut W {
42        self.bit(false)
43    }
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub fn bit(self, value: bool) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
48        self.w
49    }
50}
51#[doc = "Reader of field `TXDMAE`"]
52pub type TXDMAE_R = crate::R<bool, bool>;
53#[doc = "Write proxy for field `TXDMAE`"]
54pub struct TXDMAE_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> TXDMAE_W<'a> {
58    #[doc = r"Sets the field bit"]
59    #[inline(always)]
60    pub fn set_bit(self) -> &'a mut W {
61        self.bit(true)
62    }
63    #[doc = r"Clears the field bit"]
64    #[inline(always)]
65    pub fn clear_bit(self) -> &'a mut W {
66        self.bit(false)
67    }
68    #[doc = r"Writes raw bits to the field"]
69    #[inline(always)]
70    pub fn bit(self, value: bool) -> &'a mut W {
71        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
72        self.w
73    }
74}
75#[doc = "Reader of field `RXDMAE`"]
76pub type RXDMAE_R = crate::R<bool, bool>;
77#[doc = "Write proxy for field `RXDMAE`"]
78pub struct RXDMAE_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> RXDMAE_W<'a> {
82    #[doc = r"Sets the field bit"]
83    #[inline(always)]
84    pub fn set_bit(self) -> &'a mut W {
85        self.bit(true)
86    }
87    #[doc = r"Clears the field bit"]
88    #[inline(always)]
89    pub fn clear_bit(self) -> &'a mut W {
90        self.bit(false)
91    }
92    #[doc = r"Writes raw bits to the field"]
93    #[inline(always)]
94    pub fn bit(self, value: bool) -> &'a mut W {
95        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
96        self.w
97    }
98}
99impl R {
100    #[doc = "Bits 3:31 - 31:3\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."]
101    #[inline(always)]
102    pub fn reserved29(&self) -> RESERVED29_R {
103        RESERVED29_R::new(((self.bits >> 3) & 0x1fff_ffff) as u32)
104    }
105    #[doc = "Bit 2 - 2:2\\] DMA on error 1: uDMA receive requests are automatically disabled when a receive error occurs. 0: uDMA receive requests are unaffected when a receive error occurs."]
106    #[inline(always)]
107    pub fn dmaerr(&self) -> DMAERR_R {
108        DMAERR_R::new(((self.bits >> 2) & 0x01) != 0)
109    }
110    #[doc = "Bit 1 - 1:1\\] Transmit DMA enable 1: uDMA for the transmit FIFO is enabled. 0: uDMA for the transmit FIFO is disabled."]
111    #[inline(always)]
112    pub fn txdmae(&self) -> TXDMAE_R {
113        TXDMAE_R::new(((self.bits >> 1) & 0x01) != 0)
114    }
115    #[doc = "Bit 0 - 0:0\\] Receive DMA enable 1: uDMA for the receive FIFO is enabled. 0: uDMA for the receive FIFO is disabled."]
116    #[inline(always)]
117    pub fn rxdmae(&self) -> RXDMAE_R {
118        RXDMAE_R::new((self.bits & 0x01) != 0)
119    }
120}
121impl W {
122    #[doc = "Bits 3:31 - 31:3\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."]
123    #[inline(always)]
124    pub fn reserved29(&mut self) -> RESERVED29_W {
125        RESERVED29_W { w: self }
126    }
127    #[doc = "Bit 2 - 2:2\\] DMA on error 1: uDMA receive requests are automatically disabled when a receive error occurs. 0: uDMA receive requests are unaffected when a receive error occurs."]
128    #[inline(always)]
129    pub fn dmaerr(&mut self) -> DMAERR_W {
130        DMAERR_W { w: self }
131    }
132    #[doc = "Bit 1 - 1:1\\] Transmit DMA enable 1: uDMA for the transmit FIFO is enabled. 0: uDMA for the transmit FIFO is disabled."]
133    #[inline(always)]
134    pub fn txdmae(&mut self) -> TXDMAE_W {
135        TXDMAE_W { w: self }
136    }
137    #[doc = "Bit 0 - 0:0\\] Receive DMA enable 1: uDMA for the receive FIFO is enabled. 0: uDMA for the receive FIFO is disabled."]
138    #[inline(always)]
139    pub fn rxdmae(&mut self) -> RXDMAE_W {
140        RXDMAE_W { w: self }
141    }
142}
cc2538/uart0/dmactl.rs

cc2538/uart0/
dmactl.rs
