cc2538/uart1/
lctl.rs

1#[doc = "Reader of register LCTL"]
2pub type R = crate::R<u32, super::LCTL>;
3#[doc = "Writer for register LCTL"]
4pub type W = crate::W<u32, super::LCTL>;
5#[doc = "Register LCTL `reset()`'s with value 0"]
6impl crate::ResetValue for super::LCTL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `Reserved26`"]
14pub type RESERVED26_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `Reserved26`"]
16pub struct RESERVED26_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RESERVED26_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u32) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x03ff_ffff << 6)) | (((value as u32) & 0x03ff_ffff) << 6);
24        self.w
25    }
26}
27#[doc = "Reader of field `BLEN`"]
28pub type BLEN_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `BLEN`"]
30pub struct BLEN_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> BLEN_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
38        self.w
39    }
40}
41#[doc = "Reader of field `Reserved3`"]
42pub type RESERVED3_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `Reserved3`"]
44pub struct RESERVED3_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> RESERVED3_W<'a> {
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub unsafe fn bits(self, value: u8) -> &'a mut W {
51        self.w.bits = (self.w.bits & !(0x07 << 1)) | (((value as u32) & 0x07) << 1);
52        self.w
53    }
54}
55#[doc = "Reader of field `MASTER`"]
56pub type MASTER_R = crate::R<bool, bool>;
57#[doc = "Write proxy for field `MASTER`"]
58pub struct MASTER_W<'a> {
59    w: &'a mut W,
60}
61impl<'a> MASTER_W<'a> {
62    #[doc = r"Sets the field bit"]
63    #[inline(always)]
64    pub fn set_bit(self) -> &'a mut W {
65        self.bit(true)
66    }
67    #[doc = r"Clears the field bit"]
68    #[inline(always)]
69    pub fn clear_bit(self) -> &'a mut W {
70        self.bit(false)
71    }
72    #[doc = r"Writes raw bits to the field"]
73    #[inline(always)]
74    pub fn bit(self, value: bool) -> &'a mut W {
75        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
76        self.w
77    }
78}
79impl R {
80    #[doc = "Bits 6:31 - 31:6\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."]
81    #[inline(always)]
82    pub fn reserved26(&self) -> RESERVED26_R {
83        RESERVED26_R::new(((self.bits >> 6) & 0x03ff_ffff) as u32)
84    }
85    #[doc = "Bits 4:5 - 5:4\\] Sync break length 0x3: Sync break length is 16T bits 0x2: Sync break length is 15T bits 0x1: Sync break length is 14T bits 0x0: Sync break length is 13T bits (default)"]
86    #[inline(always)]
87    pub fn blen(&self) -> BLEN_R {
88        BLEN_R::new(((self.bits >> 4) & 0x03) as u8)
89    }
90    #[doc = "Bits 1:3 - 3:1\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."]
91    #[inline(always)]
92    pub fn reserved3(&self) -> RESERVED3_R {
93        RESERVED3_R::new(((self.bits >> 1) & 0x07) as u8)
94    }
95    #[doc = "Bit 0 - 0:0\\] LIN master enable 1: The UART operates as a LIN master. 0: The UART operates as a LIN slave."]
96    #[inline(always)]
97    pub fn master(&self) -> MASTER_R {
98        MASTER_R::new((self.bits & 0x01) != 0)
99    }
100}
101impl W {
102    #[doc = "Bits 6:31 - 31:6\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."]
103    #[inline(always)]
104    pub fn reserved26(&mut self) -> RESERVED26_W {
105        RESERVED26_W { w: self }
106    }
107    #[doc = "Bits 4:5 - 5:4\\] Sync break length 0x3: Sync break length is 16T bits 0x2: Sync break length is 15T bits 0x1: Sync break length is 14T bits 0x0: Sync break length is 13T bits (default)"]
108    #[inline(always)]
109    pub fn blen(&mut self) -> BLEN_W {
110        BLEN_W { w: self }
111    }
112    #[doc = "Bits 1:3 - 3:1\\] Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation."]
113    #[inline(always)]
114    pub fn reserved3(&mut self) -> RESERVED3_W {
115        RESERVED3_W { w: self }
116    }
117    #[doc = "Bit 0 - 0:0\\] LIN master enable 1: The UART operates as a LIN master. 0: The UART operates as a LIN slave."]
118    #[inline(always)]
119    pub fn master(&mut self) -> MASTER_W {
120        MASTER_W { w: self }
121    }
122}
cc2538/uart1/lctl.rs

cc2538/uart1/
lctl.rs
