stm32ral/stm32f4/stm32f427/
interrupts.rs

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1#[cfg(feature = "rt")]
2extern "C" {
3    fn WWDG();
4    fn PVD();
5    fn TAMP_STAMP();
6    fn RTC_WKUP();
7    fn FLASH();
8    fn RCC();
9    fn EXTI0();
10    fn EXTI1();
11    fn EXTI2();
12    fn EXTI3();
13    fn EXTI4();
14    fn DMA1_Stream0();
15    fn DMA1_Stream1();
16    fn DMA1_Stream2();
17    fn DMA1_Stream3();
18    fn DMA1_Stream4();
19    fn DMA1_Stream5();
20    fn DMA1_Stream6();
21    fn ADC();
22    fn CAN1_TX();
23    fn CAN1_RX0();
24    fn CAN1_RX1();
25    fn CAN1_SCE();
26    fn EXTI9_5();
27    fn TIM1_BRK_TIM9();
28    fn TIM1_UP_TIM10();
29    fn TIM1_TRG_COM_TIM11();
30    fn TIM1_CC();
31    fn TIM2();
32    fn TIM3();
33    fn TIM4();
34    fn I2C1_EV();
35    fn I2C1_ER();
36    fn I2C2_EV();
37    fn I2C2_ER();
38    fn SPI1();
39    fn SPI2();
40    fn USART1();
41    fn USART2();
42    fn USART3();
43    fn EXTI15_10();
44    fn RTC_Alarm();
45    fn OTG_FS_WKUP();
46    fn TIM8_BRK_TIM12();
47    fn TIM8_UP_TIM13();
48    fn TIM8_TRG_COM_TIM14();
49    fn TIM8_CC();
50    fn DMA1_Stream7();
51    fn FMC();
52    fn SDIO();
53    fn TIM5();
54    fn SPI3();
55    fn UART4();
56    fn UART5();
57    fn TIM6_DAC();
58    fn TIM7();
59    fn DMA2_Stream0();
60    fn DMA2_Stream1();
61    fn DMA2_Stream2();
62    fn DMA2_Stream3();
63    fn DMA2_Stream4();
64    fn ETH();
65    fn ETH_WKUP();
66    fn CAN2_TX();
67    fn CAN2_RX0();
68    fn CAN2_RX1();
69    fn CAN2_SCE();
70    fn OTG_FS();
71    fn DMA2_Stream5();
72    fn DMA2_Stream6();
73    fn DMA2_Stream7();
74    fn USART6();
75    fn I2C3_EV();
76    fn I2C3_ER();
77    fn OTG_HS_EP1_OUT();
78    fn OTG_HS_EP1_IN();
79    fn OTG_HS_WKUP();
80    fn OTG_HS();
81    fn DCMI();
82    fn CRYP();
83    fn HASH_RNG();
84    fn FPU();
85    fn UART7();
86    fn UART8();
87    fn SPI4();
88    fn SPI5();
89    fn SPI6();
90    fn LCD_TFT();
91    fn LCD_TFT_1();
92}
93
94#[doc(hidden)]
95pub union Vector {
96    _handler: unsafe extern "C" fn(),
97    _reserved: u32,
98}
99
100#[cfg(feature = "rt")]
101#[doc(hidden)]
102#[link_section = ".vector_table.interrupts"]
103#[no_mangle]
104pub static __INTERRUPTS: [Vector; 90] = [
105    Vector { _handler: WWDG },
106    Vector { _handler: PVD },
107    Vector {
108        _handler: TAMP_STAMP,
109    },
110    Vector { _handler: RTC_WKUP },
111    Vector { _handler: FLASH },
112    Vector { _handler: RCC },
113    Vector { _handler: EXTI0 },
114    Vector { _handler: EXTI1 },
115    Vector { _handler: EXTI2 },
116    Vector { _handler: EXTI3 },
117    Vector { _handler: EXTI4 },
118    Vector {
119        _handler: DMA1_Stream0,
120    },
121    Vector {
122        _handler: DMA1_Stream1,
123    },
124    Vector {
125        _handler: DMA1_Stream2,
126    },
127    Vector {
128        _handler: DMA1_Stream3,
129    },
130    Vector {
131        _handler: DMA1_Stream4,
132    },
133    Vector {
134        _handler: DMA1_Stream5,
135    },
136    Vector {
137        _handler: DMA1_Stream6,
138    },
139    Vector { _handler: ADC },
140    Vector { _handler: CAN1_TX },
141    Vector { _handler: CAN1_RX0 },
142    Vector { _handler: CAN1_RX1 },
143    Vector { _handler: CAN1_SCE },
144    Vector { _handler: EXTI9_5 },
145    Vector {
146        _handler: TIM1_BRK_TIM9,
147    },
148    Vector {
149        _handler: TIM1_UP_TIM10,
150    },
151    Vector {
152        _handler: TIM1_TRG_COM_TIM11,
153    },
154    Vector { _handler: TIM1_CC },
155    Vector { _handler: TIM2 },
156    Vector { _handler: TIM3 },
157    Vector { _handler: TIM4 },
158    Vector { _handler: I2C1_EV },
159    Vector { _handler: I2C1_ER },
160    Vector { _handler: I2C2_EV },
161    Vector { _handler: I2C2_ER },
162    Vector { _handler: SPI1 },
163    Vector { _handler: SPI2 },
164    Vector { _handler: USART1 },
165    Vector { _handler: USART2 },
166    Vector { _handler: USART3 },
167    Vector {
168        _handler: EXTI15_10,
169    },
170    Vector {
171        _handler: RTC_Alarm,
172    },
173    Vector {
174        _handler: OTG_FS_WKUP,
175    },
176    Vector {
177        _handler: TIM8_BRK_TIM12,
178    },
179    Vector {
180        _handler: TIM8_UP_TIM13,
181    },
182    Vector {
183        _handler: TIM8_TRG_COM_TIM14,
184    },
185    Vector { _handler: TIM8_CC },
186    Vector {
187        _handler: DMA1_Stream7,
188    },
189    Vector { _handler: FMC },
190    Vector { _handler: SDIO },
191    Vector { _handler: TIM5 },
192    Vector { _handler: SPI3 },
193    Vector { _handler: UART4 },
194    Vector { _handler: UART5 },
195    Vector { _handler: TIM6_DAC },
196    Vector { _handler: TIM7 },
197    Vector {
198        _handler: DMA2_Stream0,
199    },
200    Vector {
201        _handler: DMA2_Stream1,
202    },
203    Vector {
204        _handler: DMA2_Stream2,
205    },
206    Vector {
207        _handler: DMA2_Stream3,
208    },
209    Vector {
210        _handler: DMA2_Stream4,
211    },
212    Vector { _handler: ETH },
213    Vector { _handler: ETH_WKUP },
214    Vector { _handler: CAN2_TX },
215    Vector { _handler: CAN2_RX0 },
216    Vector { _handler: CAN2_RX1 },
217    Vector { _handler: CAN2_SCE },
218    Vector { _handler: OTG_FS },
219    Vector {
220        _handler: DMA2_Stream5,
221    },
222    Vector {
223        _handler: DMA2_Stream6,
224    },
225    Vector {
226        _handler: DMA2_Stream7,
227    },
228    Vector { _handler: USART6 },
229    Vector { _handler: I2C3_EV },
230    Vector { _handler: I2C3_ER },
231    Vector {
232        _handler: OTG_HS_EP1_OUT,
233    },
234    Vector {
235        _handler: OTG_HS_EP1_IN,
236    },
237    Vector {
238        _handler: OTG_HS_WKUP,
239    },
240    Vector { _handler: OTG_HS },
241    Vector { _handler: DCMI },
242    Vector { _handler: CRYP },
243    Vector { _handler: HASH_RNG },
244    Vector { _handler: FPU },
245    Vector { _handler: UART7 },
246    Vector { _handler: UART8 },
247    Vector { _handler: SPI4 },
248    Vector { _handler: SPI5 },
249    Vector { _handler: SPI6 },
250    Vector { _reserved: 0 },
251    Vector { _handler: LCD_TFT },
252    Vector {
253        _handler: LCD_TFT_1,
254    },
255];
256
257/// Available interrupts for this device
258#[repr(u16)]
259#[derive(Copy, Clone, Debug, PartialEq, Eq)]
260#[allow(non_camel_case_types)]
261pub enum Interrupt {
262    /// 0: Window Watchdog interrupt
263    WWDG = 0,
264    /// 1: PVD through EXTI line detection interrupt
265    PVD = 1,
266    /// 2: Tamper and TimeStamp interrupts through the EXTI line
267    TAMP_STAMP = 2,
268    /// 3: RTC Wakeup interrupt through the EXTI line
269    RTC_WKUP = 3,
270    /// 4: Flash global interrupt
271    FLASH = 4,
272    /// 5: RCC global interrupt
273    RCC = 5,
274    /// 6: EXTI Line0 interrupt
275    EXTI0 = 6,
276    /// 7: EXTI Line1 interrupt
277    EXTI1 = 7,
278    /// 8: EXTI Line2 interrupt
279    EXTI2 = 8,
280    /// 9: EXTI Line3 interrupt
281    EXTI3 = 9,
282    /// 10: EXTI Line4 interrupt
283    EXTI4 = 10,
284    /// 11: DMA1 Stream0 global interrupt
285    DMA1_Stream0 = 11,
286    /// 12: DMA1 Stream1 global interrupt
287    DMA1_Stream1 = 12,
288    /// 13: DMA1 Stream2 global interrupt
289    DMA1_Stream2 = 13,
290    /// 14: DMA1 Stream3 global interrupt
291    DMA1_Stream3 = 14,
292    /// 15: DMA1 Stream4 global interrupt
293    DMA1_Stream4 = 15,
294    /// 16: DMA1 Stream5 global interrupt
295    DMA1_Stream5 = 16,
296    /// 17: DMA1 Stream6 global interrupt
297    DMA1_Stream6 = 17,
298    /// 18: ADC3 global interrupts
299    ADC = 18,
300    /// 19: CAN1 TX interrupts
301    CAN1_TX = 19,
302    /// 20: CAN1 RX0 interrupts
303    CAN1_RX0 = 20,
304    /// 21: CAN1 RX1 interrupts
305    CAN1_RX1 = 21,
306    /// 22: CAN1 SCE interrupt
307    CAN1_SCE = 22,
308    /// 23: EXTI Line\[9:5\] interrupts
309    EXTI9_5 = 23,
310    /// 24: TIM1 Break interrupt and TIM9 global interrupt
311    TIM1_BRK_TIM9 = 24,
312    /// 25: TIM1 Update interrupt and TIM10 global interrupt
313    TIM1_UP_TIM10 = 25,
314    /// 26: TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
315    TIM1_TRG_COM_TIM11 = 26,
316    /// 27: TIM1 Capture Compare interrupt
317    TIM1_CC = 27,
318    /// 28: TIM2 global interrupt
319    TIM2 = 28,
320    /// 29: TIM3 global interrupt
321    TIM3 = 29,
322    /// 30: TIM4 global interrupt
323    TIM4 = 30,
324    /// 31: I2C1 event interrupt
325    I2C1_EV = 31,
326    /// 32: I2C1 error interrupt
327    I2C1_ER = 32,
328    /// 33: I2C2 event interrupt
329    I2C2_EV = 33,
330    /// 34: I2C2 error interrupt
331    I2C2_ER = 34,
332    /// 35: SPI1 global interrupt
333    SPI1 = 35,
334    /// 36: SPI2 global interrupt
335    SPI2 = 36,
336    /// 37: USART1 global interrupt
337    USART1 = 37,
338    /// 38: USART2 global interrupt
339    USART2 = 38,
340    /// 39: USART3 global interrupt
341    USART3 = 39,
342    /// 40: EXTI Line\[15:10\] interrupts
343    EXTI15_10 = 40,
344    /// 41: RTC Alarms (A and B) through EXTI line interrupt
345    RTC_Alarm = 41,
346    /// 42: USB On-The-Go FS Wakeup through EXTI line interrupt
347    OTG_FS_WKUP = 42,
348    /// 43: TIM8 Break interrupt and TIM12 global interrupt
349    TIM8_BRK_TIM12 = 43,
350    /// 44: TIM8 Update interrupt and TIM13 global interrupt
351    TIM8_UP_TIM13 = 44,
352    /// 45: TIM8 Trigger and Commutation interrupts and TIM14 global interrupt
353    TIM8_TRG_COM_TIM14 = 45,
354    /// 46: TIM8 Capture Compare interrupt
355    TIM8_CC = 46,
356    /// 47: DMA1 Stream7 global interrupt
357    DMA1_Stream7 = 47,
358    /// 48: FSMC global interrupt
359    FMC = 48,
360    /// 49: SDIO global interrupt
361    SDIO = 49,
362    /// 50: TIM5 global interrupt
363    TIM5 = 50,
364    /// 51: SPI3 global interrupt
365    SPI3 = 51,
366    /// 52: UART4 global interrupt
367    UART4 = 52,
368    /// 53: UART5 global interrupt
369    UART5 = 53,
370    /// 54: TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt
371    TIM6_DAC = 54,
372    /// 55: TIM7 global interrupt
373    TIM7 = 55,
374    /// 56: DMA2 Stream0 global interrupt
375    DMA2_Stream0 = 56,
376    /// 57: DMA2 Stream1 global interrupt
377    DMA2_Stream1 = 57,
378    /// 58: DMA2 Stream2 global interrupt
379    DMA2_Stream2 = 58,
380    /// 59: DMA2 Stream3 global interrupt
381    DMA2_Stream3 = 59,
382    /// 60: DMA2 Stream4 global interrupt
383    DMA2_Stream4 = 60,
384    /// 61: Ethernet global interrupt
385    ETH = 61,
386    /// 62: Ethernet Wakeup through EXTI line interrupt
387    ETH_WKUP = 62,
388    /// 63: CAN2 TX interrupts
389    CAN2_TX = 63,
390    /// 64: CAN2 RX0 interrupts
391    CAN2_RX0 = 64,
392    /// 65: CAN2 RX1 interrupts
393    CAN2_RX1 = 65,
394    /// 66: CAN2 SCE interrupt
395    CAN2_SCE = 66,
396    /// 67: USB On The Go FS global interrupt
397    OTG_FS = 67,
398    /// 68: DMA2 Stream5 global interrupt
399    DMA2_Stream5 = 68,
400    /// 69: DMA2 Stream6 global interrupt
401    DMA2_Stream6 = 69,
402    /// 70: DMA2 Stream7 global interrupt
403    DMA2_Stream7 = 70,
404    /// 71: USART6 global interrupt
405    USART6 = 71,
406    /// 72: I2C3 event interrupt
407    I2C3_EV = 72,
408    /// 73: I2C3 error interrupt
409    I2C3_ER = 73,
410    /// 74: USB On The Go HS End Point 1 Out global interrupt
411    OTG_HS_EP1_OUT = 74,
412    /// 75: USB On The Go HS End Point 1 In global interrupt
413    OTG_HS_EP1_IN = 75,
414    /// 76: USB On The Go HS Wakeup through EXTI interrupt
415    OTG_HS_WKUP = 76,
416    /// 77: USB On The Go HS global interrupt
417    OTG_HS = 77,
418    /// 78: DCMI global interrupt
419    DCMI = 78,
420    /// 79: CRYP crypto global interrupt
421    CRYP = 79,
422    /// 80: Hash and Rng global interrupt
423    HASH_RNG = 80,
424    /// 81: FPU interrupt
425    FPU = 81,
426    /// 82: UART 7 global interrupt
427    UART7 = 82,
428    /// 83: UART 8 global interrupt
429    UART8 = 83,
430    /// 84: SPI 4 global interrupt
431    SPI4 = 84,
432    /// 85: SPI 5 global interrupt
433    SPI5 = 85,
434    /// 86: SPI 6 global interrupt
435    SPI6 = 86,
436    /// 88: LTDC global interrupt
437    LCD_TFT = 88,
438    /// 89: LTDC global error interrupt
439    LCD_TFT_1 = 89,
440}
441unsafe impl external_cortex_m::interrupt::InterruptNumber for Interrupt {
442    #[inline(always)]
443    fn number(self) -> u16 {
444        self as u16
445    }
446}
stm32ral/stm32f4/stm32f427/interrupts.rs

stm32ral/stm32f4/stm32f427/
interrupts.rs
