stm32ral/stm32l4/stm32l4r9/flash.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Flash
4
5use crate::{RWRegister, WORegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// Access control register
10pub mod ACR {
11
12 /// Latency
13 pub mod LATENCY {
14 /// Offset (0 bits)
15 pub const offset: u32 = 0;
16 /// Mask (3 bits: 0b111 << 0)
17 pub const mask: u32 = 0b111 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25
26 /// Prefetch enable
27 pub mod PRFTEN {
28 /// Offset (8 bits)
29 pub const offset: u32 = 8;
30 /// Mask (1 bit: 1 << 8)
31 pub const mask: u32 = 1 << offset;
32 /// Read-only values (empty)
33 pub mod R {}
34 /// Write-only values (empty)
35 pub mod W {}
36 /// Read-write values (empty)
37 pub mod RW {}
38 }
39
40 /// Instruction cache enable
41 pub mod ICEN {
42 /// Offset (9 bits)
43 pub const offset: u32 = 9;
44 /// Mask (1 bit: 1 << 9)
45 pub const mask: u32 = 1 << offset;
46 /// Read-only values (empty)
47 pub mod R {}
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53
54 /// Data cache enable
55 pub mod DCEN {
56 /// Offset (10 bits)
57 pub const offset: u32 = 10;
58 /// Mask (1 bit: 1 << 10)
59 pub const mask: u32 = 1 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// Instruction cache reset
69 pub mod ICRST {
70 /// Offset (11 bits)
71 pub const offset: u32 = 11;
72 /// Mask (1 bit: 1 << 11)
73 pub const mask: u32 = 1 << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// Data cache reset
83 pub mod DCRST {
84 /// Offset (12 bits)
85 pub const offset: u32 = 12;
86 /// Mask (1 bit: 1 << 12)
87 pub const mask: u32 = 1 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 /// Read-write values (empty)
93 pub mod RW {}
94 }
95
96 /// Flash Power-down mode during Low-power run mode
97 pub mod RUN_PD {
98 /// Offset (13 bits)
99 pub const offset: u32 = 13;
100 /// Mask (1 bit: 1 << 13)
101 pub const mask: u32 = 1 << offset;
102 /// Read-only values (empty)
103 pub mod R {}
104 /// Write-only values (empty)
105 pub mod W {}
106 /// Read-write values (empty)
107 pub mod RW {}
108 }
109
110 /// Flash Power-down mode during Low-power sleep mode
111 pub mod SLEEP_PD {
112 /// Offset (14 bits)
113 pub const offset: u32 = 14;
114 /// Mask (1 bit: 1 << 14)
115 pub const mask: u32 = 1 << offset;
116 /// Read-only values (empty)
117 pub mod R {}
118 /// Write-only values (empty)
119 pub mod W {}
120 /// Read-write values (empty)
121 pub mod RW {}
122 }
123}
124
125/// Power down key register
126pub mod PDKEYR {
127
128 /// RUN_PD in FLASH_ACR key
129 pub mod PDKEYR {
130 /// Offset (0 bits)
131 pub const offset: u32 = 0;
132 /// Mask (32 bits: 0xffffffff << 0)
133 pub const mask: u32 = 0xffffffff << offset;
134 /// Read-only values (empty)
135 pub mod R {}
136 /// Write-only values (empty)
137 pub mod W {}
138 /// Read-write values (empty)
139 pub mod RW {}
140 }
141}
142
143/// Flash key register
144pub mod KEYR {
145
146 /// KEYR
147 pub mod KEYR {
148 /// Offset (0 bits)
149 pub const offset: u32 = 0;
150 /// Mask (32 bits: 0xffffffff << 0)
151 pub const mask: u32 = 0xffffffff << offset;
152 /// Read-only values (empty)
153 pub mod R {}
154 /// Write-only values (empty)
155 pub mod W {}
156 /// Read-write values (empty)
157 pub mod RW {}
158 }
159}
160
161/// Option byte key register
162pub mod OPTKEYR {
163
164 /// Option byte key
165 pub mod OPTKEYR {
166 /// Offset (0 bits)
167 pub const offset: u32 = 0;
168 /// Mask (32 bits: 0xffffffff << 0)
169 pub const mask: u32 = 0xffffffff << offset;
170 /// Read-only values (empty)
171 pub mod R {}
172 /// Write-only values (empty)
173 pub mod W {}
174 /// Read-write values (empty)
175 pub mod RW {}
176 }
177}
178
179/// Status register
180pub mod SR {
181
182 /// End of operation
183 pub mod EOP {
184 /// Offset (0 bits)
185 pub const offset: u32 = 0;
186 /// Mask (1 bit: 1 << 0)
187 pub const mask: u32 = 1 << offset;
188 /// Read-only values (empty)
189 pub mod R {}
190 /// Write-only values (empty)
191 pub mod W {}
192 /// Read-write values (empty)
193 pub mod RW {}
194 }
195
196 /// Operation error
197 pub mod OPERR {
198 /// Offset (1 bits)
199 pub const offset: u32 = 1;
200 /// Mask (1 bit: 1 << 1)
201 pub const mask: u32 = 1 << offset;
202 /// Read-only values (empty)
203 pub mod R {}
204 /// Write-only values (empty)
205 pub mod W {}
206 /// Read-write values (empty)
207 pub mod RW {}
208 }
209
210 /// Programming error
211 pub mod PROGERR {
212 /// Offset (3 bits)
213 pub const offset: u32 = 3;
214 /// Mask (1 bit: 1 << 3)
215 pub const mask: u32 = 1 << offset;
216 /// Read-only values (empty)
217 pub mod R {}
218 /// Write-only values (empty)
219 pub mod W {}
220 /// Read-write values (empty)
221 pub mod RW {}
222 }
223
224 /// Write protected error
225 pub mod WRPERR {
226 /// Offset (4 bits)
227 pub const offset: u32 = 4;
228 /// Mask (1 bit: 1 << 4)
229 pub const mask: u32 = 1 << offset;
230 /// Read-only values (empty)
231 pub mod R {}
232 /// Write-only values (empty)
233 pub mod W {}
234 /// Read-write values (empty)
235 pub mod RW {}
236 }
237
238 /// Programming alignment error
239 pub mod PGAERR {
240 /// Offset (5 bits)
241 pub const offset: u32 = 5;
242 /// Mask (1 bit: 1 << 5)
243 pub const mask: u32 = 1 << offset;
244 /// Read-only values (empty)
245 pub mod R {}
246 /// Write-only values (empty)
247 pub mod W {}
248 /// Read-write values (empty)
249 pub mod RW {}
250 }
251
252 /// Size error
253 pub mod SIZERR {
254 /// Offset (6 bits)
255 pub const offset: u32 = 6;
256 /// Mask (1 bit: 1 << 6)
257 pub const mask: u32 = 1 << offset;
258 /// Read-only values (empty)
259 pub mod R {}
260 /// Write-only values (empty)
261 pub mod W {}
262 /// Read-write values (empty)
263 pub mod RW {}
264 }
265
266 /// Programming sequence error
267 pub mod PGSERR {
268 /// Offset (7 bits)
269 pub const offset: u32 = 7;
270 /// Mask (1 bit: 1 << 7)
271 pub const mask: u32 = 1 << offset;
272 /// Read-only values (empty)
273 pub mod R {}
274 /// Write-only values (empty)
275 pub mod W {}
276 /// Read-write values (empty)
277 pub mod RW {}
278 }
279
280 /// Fast programming data miss error
281 pub mod MISERR {
282 /// Offset (8 bits)
283 pub const offset: u32 = 8;
284 /// Mask (1 bit: 1 << 8)
285 pub const mask: u32 = 1 << offset;
286 /// Read-only values (empty)
287 pub mod R {}
288 /// Write-only values (empty)
289 pub mod W {}
290 /// Read-write values (empty)
291 pub mod RW {}
292 }
293
294 /// Fast programming error
295 pub mod FASTERR {
296 /// Offset (9 bits)
297 pub const offset: u32 = 9;
298 /// Mask (1 bit: 1 << 9)
299 pub const mask: u32 = 1 << offset;
300 /// Read-only values (empty)
301 pub mod R {}
302 /// Write-only values (empty)
303 pub mod W {}
304 /// Read-write values (empty)
305 pub mod RW {}
306 }
307
308 /// PCROP read error
309 pub mod RDERR {
310 /// Offset (14 bits)
311 pub const offset: u32 = 14;
312 /// Mask (1 bit: 1 << 14)
313 pub const mask: u32 = 1 << offset;
314 /// Read-only values (empty)
315 pub mod R {}
316 /// Write-only values (empty)
317 pub mod W {}
318 /// Read-write values (empty)
319 pub mod RW {}
320 }
321
322 /// Option validity error
323 pub mod OPTVERR {
324 /// Offset (15 bits)
325 pub const offset: u32 = 15;
326 /// Mask (1 bit: 1 << 15)
327 pub const mask: u32 = 1 << offset;
328 /// Read-only values (empty)
329 pub mod R {}
330 /// Write-only values (empty)
331 pub mod W {}
332 /// Read-write values (empty)
333 pub mod RW {}
334 }
335
336 /// Busy
337 pub mod BSY {
338 /// Offset (16 bits)
339 pub const offset: u32 = 16;
340 /// Mask (1 bit: 1 << 16)
341 pub const mask: u32 = 1 << offset;
342 /// Read-only values (empty)
343 pub mod R {}
344 /// Write-only values (empty)
345 pub mod W {}
346 /// Read-write values (empty)
347 pub mod RW {}
348 }
349}
350
351/// Flash control register
352pub mod CR {
353
354 /// Programming
355 pub mod PG {
356 /// Offset (0 bits)
357 pub const offset: u32 = 0;
358 /// Mask (1 bit: 1 << 0)
359 pub const mask: u32 = 1 << offset;
360 /// Read-only values (empty)
361 pub mod R {}
362 /// Write-only values (empty)
363 pub mod W {}
364 /// Read-write values (empty)
365 pub mod RW {}
366 }
367
368 /// Page erase
369 pub mod PER {
370 /// Offset (1 bits)
371 pub const offset: u32 = 1;
372 /// Mask (1 bit: 1 << 1)
373 pub const mask: u32 = 1 << offset;
374 /// Read-only values (empty)
375 pub mod R {}
376 /// Write-only values (empty)
377 pub mod W {}
378 /// Read-write values (empty)
379 pub mod RW {}
380 }
381
382 /// Bank 1 Mass erase
383 pub mod MER1 {
384 /// Offset (2 bits)
385 pub const offset: u32 = 2;
386 /// Mask (1 bit: 1 << 2)
387 pub const mask: u32 = 1 << offset;
388 /// Read-only values (empty)
389 pub mod R {}
390 /// Write-only values (empty)
391 pub mod W {}
392 /// Read-write values (empty)
393 pub mod RW {}
394 }
395
396 /// Page number
397 pub mod PNB {
398 /// Offset (3 bits)
399 pub const offset: u32 = 3;
400 /// Mask (8 bits: 0xff << 3)
401 pub const mask: u32 = 0xff << offset;
402 /// Read-only values (empty)
403 pub mod R {}
404 /// Write-only values (empty)
405 pub mod W {}
406 /// Read-write values (empty)
407 pub mod RW {}
408 }
409
410 /// Bank erase
411 pub mod BKER {
412 /// Offset (11 bits)
413 pub const offset: u32 = 11;
414 /// Mask (1 bit: 1 << 11)
415 pub const mask: u32 = 1 << offset;
416 /// Read-only values (empty)
417 pub mod R {}
418 /// Write-only values (empty)
419 pub mod W {}
420 /// Read-write values (empty)
421 pub mod RW {}
422 }
423
424 /// Bank 2 Mass erase
425 pub mod MER2 {
426 /// Offset (15 bits)
427 pub const offset: u32 = 15;
428 /// Mask (1 bit: 1 << 15)
429 pub const mask: u32 = 1 << offset;
430 /// Read-only values (empty)
431 pub mod R {}
432 /// Write-only values (empty)
433 pub mod W {}
434 /// Read-write values (empty)
435 pub mod RW {}
436 }
437
438 /// Start
439 pub mod START {
440 /// Offset (16 bits)
441 pub const offset: u32 = 16;
442 /// Mask (1 bit: 1 << 16)
443 pub const mask: u32 = 1 << offset;
444 /// Read-only values (empty)
445 pub mod R {}
446 /// Write-only values (empty)
447 pub mod W {}
448 /// Read-write values (empty)
449 pub mod RW {}
450 }
451
452 /// Options modification start
453 pub mod OPTSTRT {
454 /// Offset (17 bits)
455 pub const offset: u32 = 17;
456 /// Mask (1 bit: 1 << 17)
457 pub const mask: u32 = 1 << offset;
458 /// Read-only values (empty)
459 pub mod R {}
460 /// Write-only values (empty)
461 pub mod W {}
462 /// Read-write values (empty)
463 pub mod RW {}
464 }
465
466 /// Fast programming
467 pub mod FSTPG {
468 /// Offset (18 bits)
469 pub const offset: u32 = 18;
470 /// Mask (1 bit: 1 << 18)
471 pub const mask: u32 = 1 << offset;
472 /// Read-only values (empty)
473 pub mod R {}
474 /// Write-only values (empty)
475 pub mod W {}
476 /// Read-write values (empty)
477 pub mod RW {}
478 }
479
480 /// End of operation interrupt enable
481 pub mod EOPIE {
482 /// Offset (24 bits)
483 pub const offset: u32 = 24;
484 /// Mask (1 bit: 1 << 24)
485 pub const mask: u32 = 1 << offset;
486 /// Read-only values (empty)
487 pub mod R {}
488 /// Write-only values (empty)
489 pub mod W {}
490 /// Read-write values (empty)
491 pub mod RW {}
492 }
493
494 /// Error interrupt enable
495 pub mod ERRIE {
496 /// Offset (25 bits)
497 pub const offset: u32 = 25;
498 /// Mask (1 bit: 1 << 25)
499 pub const mask: u32 = 1 << offset;
500 /// Read-only values (empty)
501 pub mod R {}
502 /// Write-only values (empty)
503 pub mod W {}
504 /// Read-write values (empty)
505 pub mod RW {}
506 }
507
508 /// PCROP read error interrupt enable
509 pub mod RDERRIE {
510 /// Offset (26 bits)
511 pub const offset: u32 = 26;
512 /// Mask (1 bit: 1 << 26)
513 pub const mask: u32 = 1 << offset;
514 /// Read-only values (empty)
515 pub mod R {}
516 /// Write-only values (empty)
517 pub mod W {}
518 /// Read-write values (empty)
519 pub mod RW {}
520 }
521
522 /// Force the option byte loading
523 pub mod OBL_LAUNCH {
524 /// Offset (27 bits)
525 pub const offset: u32 = 27;
526 /// Mask (1 bit: 1 << 27)
527 pub const mask: u32 = 1 << offset;
528 /// Read-only values (empty)
529 pub mod R {}
530 /// Write-only values (empty)
531 pub mod W {}
532 /// Read-write values (empty)
533 pub mod RW {}
534 }
535
536 /// Options Lock
537 pub mod OPTLOCK {
538 /// Offset (30 bits)
539 pub const offset: u32 = 30;
540 /// Mask (1 bit: 1 << 30)
541 pub const mask: u32 = 1 << offset;
542 /// Read-only values (empty)
543 pub mod R {}
544 /// Write-only values (empty)
545 pub mod W {}
546 /// Read-write values (empty)
547 pub mod RW {}
548 }
549
550 /// FLASH_CR Lock
551 pub mod LOCK {
552 /// Offset (31 bits)
553 pub const offset: u32 = 31;
554 /// Mask (1 bit: 1 << 31)
555 pub const mask: u32 = 1 << offset;
556 /// Read-only values (empty)
557 pub mod R {}
558 /// Write-only values (empty)
559 pub mod W {}
560 /// Read-write values (empty)
561 pub mod RW {}
562 }
563}
564
565/// Flash ECC register
566pub mod ECCR {
567
568 /// ECC fail address
569 pub mod ADDR_ECC {
570 /// Offset (0 bits)
571 pub const offset: u32 = 0;
572 /// Mask (19 bits: 0x7ffff << 0)
573 pub const mask: u32 = 0x7ffff << offset;
574 /// Read-only values (empty)
575 pub mod R {}
576 /// Write-only values (empty)
577 pub mod W {}
578 /// Read-write values (empty)
579 pub mod RW {}
580 }
581
582 /// ECC fail bank
583 pub mod BK_ECC {
584 /// Offset (19 bits)
585 pub const offset: u32 = 19;
586 /// Mask (1 bit: 1 << 19)
587 pub const mask: u32 = 1 << offset;
588 /// Read-only values (empty)
589 pub mod R {}
590 /// Write-only values (empty)
591 pub mod W {}
592 /// Read-write values (empty)
593 pub mod RW {}
594 }
595
596 /// System Flash ECC fail
597 pub mod SYSF_ECC {
598 /// Offset (20 bits)
599 pub const offset: u32 = 20;
600 /// Mask (1 bit: 1 << 20)
601 pub const mask: u32 = 1 << offset;
602 /// Read-only values (empty)
603 pub mod R {}
604 /// Write-only values (empty)
605 pub mod W {}
606 /// Read-write values (empty)
607 pub mod RW {}
608 }
609
610 /// ECC correction interrupt enable
611 pub mod ECCIE {
612 /// Offset (24 bits)
613 pub const offset: u32 = 24;
614 /// Mask (1 bit: 1 << 24)
615 pub const mask: u32 = 1 << offset;
616 /// Read-only values (empty)
617 pub mod R {}
618 /// Write-only values (empty)
619 pub mod W {}
620 /// Read-write values (empty)
621 pub mod RW {}
622 }
623
624 /// ECC correction
625 pub mod ECCC {
626 /// Offset (30 bits)
627 pub const offset: u32 = 30;
628 /// Mask (1 bit: 1 << 30)
629 pub const mask: u32 = 1 << offset;
630 /// Read-only values (empty)
631 pub mod R {}
632 /// Write-only values (empty)
633 pub mod W {}
634 /// Read-write values (empty)
635 pub mod RW {}
636 }
637
638 /// ECC detection
639 pub mod ECCD {
640 /// Offset (31 bits)
641 pub const offset: u32 = 31;
642 /// Mask (1 bit: 1 << 31)
643 pub const mask: u32 = 1 << offset;
644 /// Read-only values (empty)
645 pub mod R {}
646 /// Write-only values (empty)
647 pub mod W {}
648 /// Read-write values (empty)
649 pub mod RW {}
650 }
651}
652
653/// Flash option register
654pub mod OPTR {
655
656 /// Read protection level
657 pub mod RDP {
658 /// Offset (0 bits)
659 pub const offset: u32 = 0;
660 /// Mask (8 bits: 0xff << 0)
661 pub const mask: u32 = 0xff << offset;
662 /// Read-only values (empty)
663 pub mod R {}
664 /// Write-only values (empty)
665 pub mod W {}
666 /// Read-write values (empty)
667 pub mod RW {}
668 }
669
670 /// BOR reset Level
671 pub mod BOR_LEV {
672 /// Offset (8 bits)
673 pub const offset: u32 = 8;
674 /// Mask (3 bits: 0b111 << 8)
675 pub const mask: u32 = 0b111 << offset;
676 /// Read-only values (empty)
677 pub mod R {}
678 /// Write-only values (empty)
679 pub mod W {}
680 /// Read-write values (empty)
681 pub mod RW {}
682 }
683
684 /// nRST_STOP
685 pub mod nRST_STOP {
686 /// Offset (12 bits)
687 pub const offset: u32 = 12;
688 /// Mask (1 bit: 1 << 12)
689 pub const mask: u32 = 1 << offset;
690 /// Read-only values (empty)
691 pub mod R {}
692 /// Write-only values (empty)
693 pub mod W {}
694 /// Read-write values (empty)
695 pub mod RW {}
696 }
697
698 /// nRST_STDBY
699 pub mod nRST_STDBY {
700 /// Offset (13 bits)
701 pub const offset: u32 = 13;
702 /// Mask (1 bit: 1 << 13)
703 pub const mask: u32 = 1 << offset;
704 /// Read-only values (empty)
705 pub mod R {}
706 /// Write-only values (empty)
707 pub mod W {}
708 /// Read-write values (empty)
709 pub mod RW {}
710 }
711
712 /// Independent watchdog selection
713 pub mod IDWG_SW {
714 /// Offset (16 bits)
715 pub const offset: u32 = 16;
716 /// Mask (1 bit: 1 << 16)
717 pub const mask: u32 = 1 << offset;
718 /// Read-only values (empty)
719 pub mod R {}
720 /// Write-only values (empty)
721 pub mod W {}
722 /// Read-write values (empty)
723 pub mod RW {}
724 }
725
726 /// Independent watchdog counter freeze in Stop mode
727 pub mod IWDG_STOP {
728 /// Offset (17 bits)
729 pub const offset: u32 = 17;
730 /// Mask (1 bit: 1 << 17)
731 pub const mask: u32 = 1 << offset;
732 /// Read-only values (empty)
733 pub mod R {}
734 /// Write-only values (empty)
735 pub mod W {}
736 /// Read-write values (empty)
737 pub mod RW {}
738 }
739
740 /// Independent watchdog counter freeze in Standby mode
741 pub mod IWDG_STDBY {
742 /// Offset (18 bits)
743 pub const offset: u32 = 18;
744 /// Mask (1 bit: 1 << 18)
745 pub const mask: u32 = 1 << offset;
746 /// Read-only values (empty)
747 pub mod R {}
748 /// Write-only values (empty)
749 pub mod W {}
750 /// Read-write values (empty)
751 pub mod RW {}
752 }
753
754 /// Window watchdog selection
755 pub mod WWDG_SW {
756 /// Offset (19 bits)
757 pub const offset: u32 = 19;
758 /// Mask (1 bit: 1 << 19)
759 pub const mask: u32 = 1 << offset;
760 /// Read-only values (empty)
761 pub mod R {}
762 /// Write-only values (empty)
763 pub mod W {}
764 /// Read-write values (empty)
765 pub mod RW {}
766 }
767
768 /// Dual-bank boot
769 pub mod BFB2 {
770 /// Offset (20 bits)
771 pub const offset: u32 = 20;
772 /// Mask (1 bit: 1 << 20)
773 pub const mask: u32 = 1 << offset;
774 /// Read-only values (empty)
775 pub mod R {}
776 /// Write-only values (empty)
777 pub mod W {}
778 /// Read-write values (empty)
779 pub mod RW {}
780 }
781
782 /// Dual-Bank on 512 KB or 256 KB Flash memory devices
783 pub mod DUALBANK {
784 /// Offset (21 bits)
785 pub const offset: u32 = 21;
786 /// Mask (1 bit: 1 << 21)
787 pub const mask: u32 = 1 << offset;
788 /// Read-only values (empty)
789 pub mod R {}
790 /// Write-only values (empty)
791 pub mod W {}
792 /// Read-write values (empty)
793 pub mod RW {}
794 }
795
796 /// Boot configuration
797 pub mod nBOOT1 {
798 /// Offset (23 bits)
799 pub const offset: u32 = 23;
800 /// Mask (1 bit: 1 << 23)
801 pub const mask: u32 = 1 << offset;
802 /// Read-only values (empty)
803 pub mod R {}
804 /// Write-only values (empty)
805 pub mod W {}
806 /// Read-write values (empty)
807 pub mod RW {}
808 }
809
810 /// SRAM2 parity check enable
811 pub mod SRAM2_PE {
812 /// Offset (24 bits)
813 pub const offset: u32 = 24;
814 /// Mask (1 bit: 1 << 24)
815 pub const mask: u32 = 1 << offset;
816 /// Read-only values (empty)
817 pub mod R {}
818 /// Write-only values (empty)
819 pub mod W {}
820 /// Read-write values (empty)
821 pub mod RW {}
822 }
823
824 /// SRAM2 Erase when system reset
825 pub mod SRAM2_RST {
826 /// Offset (25 bits)
827 pub const offset: u32 = 25;
828 /// Mask (1 bit: 1 << 25)
829 pub const mask: u32 = 1 << offset;
830 /// Read-only values (empty)
831 pub mod R {}
832 /// Write-only values (empty)
833 pub mod W {}
834 /// Read-write values (empty)
835 pub mod RW {}
836 }
837
838 /// Software BOOT0
839 pub mod nSWBOOT0 {
840 /// Offset (26 bits)
841 pub const offset: u32 = 26;
842 /// Mask (1 bit: 1 << 26)
843 pub const mask: u32 = 1 << offset;
844 /// Read-only values (empty)
845 pub mod R {}
846 /// Write-only values (empty)
847 pub mod W {}
848 /// Read-write values (empty)
849 pub mod RW {}
850 }
851
852 /// nBOOT0 option bit
853 pub mod nBOOT0 {
854 /// Offset (27 bits)
855 pub const offset: u32 = 27;
856 /// Mask (1 bit: 1 << 27)
857 pub const mask: u32 = 1 << offset;
858 /// Read-only values (empty)
859 pub mod R {}
860 /// Write-only values (empty)
861 pub mod W {}
862 /// Read-write values (empty)
863 pub mod RW {}
864 }
865}
866
867/// Flash Bank 1 PCROP Start address register
868pub mod PCROP1SR {
869
870 /// Bank 1 PCROP area start offset
871 pub mod PCROP1_STRT {
872 /// Offset (0 bits)
873 pub const offset: u32 = 0;
874 /// Mask (16 bits: 0xffff << 0)
875 pub const mask: u32 = 0xffff << offset;
876 /// Read-only values (empty)
877 pub mod R {}
878 /// Write-only values (empty)
879 pub mod W {}
880 /// Read-write values (empty)
881 pub mod RW {}
882 }
883}
884
885/// Flash Bank 1 PCROP End address register
886pub mod PCROP1ER {
887
888 /// Bank 1 PCROP area end offset
889 pub mod PCROP1_END {
890 /// Offset (0 bits)
891 pub const offset: u32 = 0;
892 /// Mask (16 bits: 0xffff << 0)
893 pub const mask: u32 = 0xffff << offset;
894 /// Read-only values (empty)
895 pub mod R {}
896 /// Write-only values (empty)
897 pub mod W {}
898 /// Read-write values (empty)
899 pub mod RW {}
900 }
901
902 /// PCROP area preserved when RDP level decreased
903 pub mod PCROP_RDP {
904 /// Offset (31 bits)
905 pub const offset: u32 = 31;
906 /// Mask (1 bit: 1 << 31)
907 pub const mask: u32 = 1 << offset;
908 /// Read-only values (empty)
909 pub mod R {}
910 /// Write-only values (empty)
911 pub mod W {}
912 /// Read-write values (empty)
913 pub mod RW {}
914 }
915}
916
917/// Flash Bank 1 WRP area A address register
918pub mod WRP1AR {
919
920 /// Bank 1 WRP first area start offset
921 pub mod WRP1A_STRT {
922 /// Offset (0 bits)
923 pub const offset: u32 = 0;
924 /// Mask (8 bits: 0xff << 0)
925 pub const mask: u32 = 0xff << offset;
926 /// Read-only values (empty)
927 pub mod R {}
928 /// Write-only values (empty)
929 pub mod W {}
930 /// Read-write values (empty)
931 pub mod RW {}
932 }
933
934 /// Bank 1 WRP first area A end offset
935 pub mod WRP1A_END {
936 /// Offset (16 bits)
937 pub const offset: u32 = 16;
938 /// Mask (8 bits: 0xff << 16)
939 pub const mask: u32 = 0xff << offset;
940 /// Read-only values (empty)
941 pub mod R {}
942 /// Write-only values (empty)
943 pub mod W {}
944 /// Read-write values (empty)
945 pub mod RW {}
946 }
947}
948
949/// Flash Bank 1 WRP area B address register
950pub mod WRP1BR {
951
952 /// Bank 1 WRP second area B end offset
953 pub mod WRP1B_END {
954 /// Offset (16 bits)
955 pub const offset: u32 = 16;
956 /// Mask (8 bits: 0xff << 16)
957 pub const mask: u32 = 0xff << offset;
958 /// Read-only values (empty)
959 pub mod R {}
960 /// Write-only values (empty)
961 pub mod W {}
962 /// Read-write values (empty)
963 pub mod RW {}
964 }
965
966 /// Bank 1 WRP second area B start offset
967 pub mod WRP1B_STRT {
968 /// Offset (0 bits)
969 pub const offset: u32 = 0;
970 /// Mask (8 bits: 0xff << 0)
971 pub const mask: u32 = 0xff << offset;
972 /// Read-only values (empty)
973 pub mod R {}
974 /// Write-only values (empty)
975 pub mod W {}
976 /// Read-write values (empty)
977 pub mod RW {}
978 }
979}
980
981/// Flash Bank 2 PCROP Start address register
982pub mod PCROP2SR {
983
984 /// Bank 2 PCROP area start offset
985 pub mod PCROP2_STRT {
986 /// Offset (0 bits)
987 pub const offset: u32 = 0;
988 /// Mask (16 bits: 0xffff << 0)
989 pub const mask: u32 = 0xffff << offset;
990 /// Read-only values (empty)
991 pub mod R {}
992 /// Write-only values (empty)
993 pub mod W {}
994 /// Read-write values (empty)
995 pub mod RW {}
996 }
997}
998
999/// Flash Bank 2 PCROP End address register
1000pub mod PCROP2ER {
1001
1002 /// Bank 2 PCROP area end offset
1003 pub mod PCROP2_END {
1004 /// Offset (0 bits)
1005 pub const offset: u32 = 0;
1006 /// Mask (16 bits: 0xffff << 0)
1007 pub const mask: u32 = 0xffff << offset;
1008 /// Read-only values (empty)
1009 pub mod R {}
1010 /// Write-only values (empty)
1011 pub mod W {}
1012 /// Read-write values (empty)
1013 pub mod RW {}
1014 }
1015}
1016
1017/// Flash Bank 2 WRP area A address register
1018pub mod WRP2AR {
1019
1020 /// Bank 2 WRP first area A start offset
1021 pub mod WRP2A_STRT {
1022 /// Offset (0 bits)
1023 pub const offset: u32 = 0;
1024 /// Mask (8 bits: 0xff << 0)
1025 pub const mask: u32 = 0xff << offset;
1026 /// Read-only values (empty)
1027 pub mod R {}
1028 /// Write-only values (empty)
1029 pub mod W {}
1030 /// Read-write values (empty)
1031 pub mod RW {}
1032 }
1033
1034 /// Bank 2 WRP first area A end offset
1035 pub mod WRP2A_END {
1036 /// Offset (16 bits)
1037 pub const offset: u32 = 16;
1038 /// Mask (8 bits: 0xff << 16)
1039 pub const mask: u32 = 0xff << offset;
1040 /// Read-only values (empty)
1041 pub mod R {}
1042 /// Write-only values (empty)
1043 pub mod W {}
1044 /// Read-write values (empty)
1045 pub mod RW {}
1046 }
1047}
1048
1049/// Flash Bank 2 WRP area B address register
1050pub mod WRP2BR {
1051
1052 /// Bank 2 WRP second area B start offset
1053 pub mod WRP2B_STRT {
1054 /// Offset (0 bits)
1055 pub const offset: u32 = 0;
1056 /// Mask (8 bits: 0xff << 0)
1057 pub const mask: u32 = 0xff << offset;
1058 /// Read-only values (empty)
1059 pub mod R {}
1060 /// Write-only values (empty)
1061 pub mod W {}
1062 /// Read-write values (empty)
1063 pub mod RW {}
1064 }
1065
1066 /// Bank 2 WRP second area B end offset
1067 pub mod WRP2B_END {
1068 /// Offset (16 bits)
1069 pub const offset: u32 = 16;
1070 /// Mask (8 bits: 0xff << 16)
1071 pub const mask: u32 = 0xff << offset;
1072 /// Read-only values (empty)
1073 pub mod R {}
1074 /// Write-only values (empty)
1075 pub mod W {}
1076 /// Read-write values (empty)
1077 pub mod RW {}
1078 }
1079}
1080#[repr(C)]
1081pub struct RegisterBlock {
1082 /// Access control register
1083 pub ACR: RWRegister<u32>,
1084
1085 /// Power down key register
1086 pub PDKEYR: WORegister<u32>,
1087
1088 /// Flash key register
1089 pub KEYR: WORegister<u32>,
1090
1091 /// Option byte key register
1092 pub OPTKEYR: WORegister<u32>,
1093
1094 /// Status register
1095 pub SR: RWRegister<u32>,
1096
1097 /// Flash control register
1098 pub CR: RWRegister<u32>,
1099
1100 /// Flash ECC register
1101 pub ECCR: RWRegister<u32>,
1102
1103 _reserved1: [u8; 4],
1104
1105 /// Flash option register
1106 pub OPTR: RWRegister<u32>,
1107
1108 /// Flash Bank 1 PCROP Start address register
1109 pub PCROP1SR: RWRegister<u32>,
1110
1111 /// Flash Bank 1 PCROP End address register
1112 pub PCROP1ER: RWRegister<u32>,
1113
1114 /// Flash Bank 1 WRP area A address register
1115 pub WRP1AR: RWRegister<u32>,
1116
1117 /// Flash Bank 1 WRP area B address register
1118 pub WRP1BR: RWRegister<u32>,
1119
1120 _reserved2: [u8; 16],
1121
1122 /// Flash Bank 2 PCROP Start address register
1123 pub PCROP2SR: RWRegister<u32>,
1124
1125 /// Flash Bank 2 PCROP End address register
1126 pub PCROP2ER: RWRegister<u32>,
1127
1128 /// Flash Bank 2 WRP area A address register
1129 pub WRP2AR: RWRegister<u32>,
1130
1131 /// Flash Bank 2 WRP area B address register
1132 pub WRP2BR: RWRegister<u32>,
1133}
1134pub struct ResetValues {
1135 pub ACR: u32,
1136 pub PDKEYR: u32,
1137 pub KEYR: u32,
1138 pub OPTKEYR: u32,
1139 pub SR: u32,
1140 pub CR: u32,
1141 pub ECCR: u32,
1142 pub OPTR: u32,
1143 pub PCROP1SR: u32,
1144 pub PCROP1ER: u32,
1145 pub WRP1AR: u32,
1146 pub WRP1BR: u32,
1147 pub PCROP2SR: u32,
1148 pub PCROP2ER: u32,
1149 pub WRP2AR: u32,
1150 pub WRP2BR: u32,
1151}
1152#[cfg(not(feature = "nosync"))]
1153pub struct Instance {
1154 pub(crate) addr: u32,
1155 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1156}
1157#[cfg(not(feature = "nosync"))]
1158impl ::core::ops::Deref for Instance {
1159 type Target = RegisterBlock;
1160 #[inline(always)]
1161 fn deref(&self) -> &RegisterBlock {
1162 unsafe { &*(self.addr as *const _) }
1163 }
1164}
1165#[cfg(feature = "rtic")]
1166unsafe impl Send for Instance {}
1167
1168/// Access functions for the FLASH peripheral instance
1169pub mod FLASH {
1170 use super::ResetValues;
1171
1172 #[cfg(not(feature = "nosync"))]
1173 use super::Instance;
1174
1175 #[cfg(not(feature = "nosync"))]
1176 const INSTANCE: Instance = Instance {
1177 addr: 0x40022000,
1178 _marker: ::core::marker::PhantomData,
1179 };
1180
1181 /// Reset values for each field in FLASH
1182 pub const reset: ResetValues = ResetValues {
1183 ACR: 0x00000600,
1184 PDKEYR: 0x00000000,
1185 KEYR: 0x00000000,
1186 OPTKEYR: 0x00000000,
1187 SR: 0x00000000,
1188 CR: 0xC0000000,
1189 ECCR: 0x00000000,
1190 OPTR: 0xF0000000,
1191 PCROP1SR: 0xFFFF0000,
1192 PCROP1ER: 0x0FFF0000,
1193 WRP1AR: 0xFF00FF00,
1194 WRP1BR: 0xFF00FF00,
1195 PCROP2SR: 0xFFFF0000,
1196 PCROP2ER: 0xFFFF0000,
1197 WRP2AR: 0xFF00FF00,
1198 WRP2BR: 0xFF00FF00,
1199 };
1200
1201 #[cfg(not(feature = "nosync"))]
1202 #[allow(renamed_and_removed_lints)]
1203 #[allow(private_no_mangle_statics)]
1204 #[no_mangle]
1205 static mut FLASH_TAKEN: bool = false;
1206
1207 /// Safe access to FLASH
1208 ///
1209 /// This function returns `Some(Instance)` if this instance is not
1210 /// currently taken, and `None` if it is. This ensures that if you
1211 /// do get `Some(Instance)`, you are ensured unique access to
1212 /// the peripheral and there cannot be data races (unless other
1213 /// code uses `unsafe`, of course). You can then pass the
1214 /// `Instance` around to other functions as required. When you're
1215 /// done with it, you can call `release(instance)` to return it.
1216 ///
1217 /// `Instance` itself dereferences to a `RegisterBlock`, which
1218 /// provides access to the peripheral's registers.
1219 #[cfg(not(feature = "nosync"))]
1220 #[inline]
1221 pub fn take() -> Option<Instance> {
1222 external_cortex_m::interrupt::free(|_| unsafe {
1223 if FLASH_TAKEN {
1224 None
1225 } else {
1226 FLASH_TAKEN = true;
1227 Some(INSTANCE)
1228 }
1229 })
1230 }
1231
1232 /// Release exclusive access to FLASH
1233 ///
1234 /// This function allows you to return an `Instance` so that it
1235 /// is available to `take()` again. This function will panic if
1236 /// you return a different `Instance` or if this instance is not
1237 /// already taken.
1238 #[cfg(not(feature = "nosync"))]
1239 #[inline]
1240 pub fn release(inst: Instance) {
1241 external_cortex_m::interrupt::free(|_| unsafe {
1242 if FLASH_TAKEN && inst.addr == INSTANCE.addr {
1243 FLASH_TAKEN = false;
1244 } else {
1245 panic!("Released a peripheral which was not taken");
1246 }
1247 });
1248 }
1249
1250 /// Unsafely steal FLASH
1251 ///
1252 /// This function is similar to take() but forcibly takes the
1253 /// Instance, marking it as taken irregardless of its previous
1254 /// state.
1255 #[cfg(not(feature = "nosync"))]
1256 #[inline]
1257 pub unsafe fn steal() -> Instance {
1258 FLASH_TAKEN = true;
1259 INSTANCE
1260 }
1261}
1262
1263/// Raw pointer to FLASH
1264///
1265/// Dereferencing this is unsafe because you are not ensured unique
1266/// access to the peripheral, so you may encounter data races with
1267/// other users of this peripheral. It is up to you to ensure you
1268/// will not cause data races.
1269///
1270/// This constant is provided for ease of use in unsafe code: you can
1271/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
1272pub const FLASH: *const RegisterBlock = 0x40022000 as *const _;