stm32ral/stm32f0/instances/
rcc.rs

1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Reset and clock control
4//!
5//! Used by: stm32f0x1, stm32f0x8
6
7#[cfg(not(feature = "nosync"))]
8pub use crate::stm32f0::peripherals::rcc::Instance;
9pub use crate::stm32f0::peripherals::rcc::{RegisterBlock, ResetValues};
10pub use crate::stm32f0::peripherals::rcc::{
11    AHBENR, AHBRSTR, APB1ENR, APB1RSTR, APB2ENR, APB2RSTR, BDCR, CFGR, CFGR2, CFGR3, CIR, CR, CR2,
12    CSR,
13};
14
15/// Access functions for the RCC peripheral instance
16pub mod RCC {
17    use super::ResetValues;
18
19    #[cfg(not(feature = "nosync"))]
20    use super::Instance;
21
22    #[cfg(not(feature = "nosync"))]
23    const INSTANCE: Instance = Instance {
24        addr: 0x40021000,
25        _marker: ::core::marker::PhantomData,
26    };
27
28    /// Reset values for each field in RCC
29    pub const reset: ResetValues = ResetValues {
30        CR: 0x00000083,
31        CFGR: 0x00000000,
32        CIR: 0x00000000,
33        APB2RSTR: 0x00000000,
34        APB1RSTR: 0x00000000,
35        AHBENR: 0x00000014,
36        APB2ENR: 0x00000000,
37        APB1ENR: 0x00000000,
38        BDCR: 0x00000000,
39        CSR: 0x0C000000,
40        AHBRSTR: 0x00000000,
41        CFGR2: 0x00000000,
42        CFGR3: 0x00000000,
43        CR2: 0x00000080,
44    };
45
46    #[cfg(not(feature = "nosync"))]
47    #[allow(renamed_and_removed_lints)]
48    #[allow(private_no_mangle_statics)]
49    #[no_mangle]
50    static mut RCC_TAKEN: bool = false;
51
52    /// Safe access to RCC
53    ///
54    /// This function returns `Some(Instance)` if this instance is not
55    /// currently taken, and `None` if it is. This ensures that if you
56    /// do get `Some(Instance)`, you are ensured unique access to
57    /// the peripheral and there cannot be data races (unless other
58    /// code uses `unsafe`, of course). You can then pass the
59    /// `Instance` around to other functions as required. When you're
60    /// done with it, you can call `release(instance)` to return it.
61    ///
62    /// `Instance` itself dereferences to a `RegisterBlock`, which
63    /// provides access to the peripheral's registers.
64    #[cfg(not(feature = "nosync"))]
65    #[inline]
66    pub fn take() -> Option<Instance> {
67        external_cortex_m::interrupt::free(|_| unsafe {
68            if RCC_TAKEN {
69                None
70            } else {
71                RCC_TAKEN = true;
72                Some(INSTANCE)
73            }
74        })
75    }
76
77    /// Release exclusive access to RCC
78    ///
79    /// This function allows you to return an `Instance` so that it
80    /// is available to `take()` again. This function will panic if
81    /// you return a different `Instance` or if this instance is not
82    /// already taken.
83    #[cfg(not(feature = "nosync"))]
84    #[inline]
85    pub fn release(inst: Instance) {
86        external_cortex_m::interrupt::free(|_| unsafe {
87            if RCC_TAKEN && inst.addr == INSTANCE.addr {
88                RCC_TAKEN = false;
89            } else {
90                panic!("Released a peripheral which was not taken");
91            }
92        });
93    }
94
95    /// Unsafely steal RCC
96    ///
97    /// This function is similar to take() but forcibly takes the
98    /// Instance, marking it as taken irregardless of its previous
99    /// state.
100    #[cfg(not(feature = "nosync"))]
101    #[inline]
102    pub unsafe fn steal() -> Instance {
103        RCC_TAKEN = true;
104        INSTANCE
105    }
106}
107
108/// Raw pointer to RCC
109///
110/// Dereferencing this is unsafe because you are not ensured unique
111/// access to the peripheral, so you may encounter data races with
112/// other users of this peripheral. It is up to you to ensure you
113/// will not cause data races.
114///
115/// This constant is provided for ease of use in unsafe code: you can
116/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
117pub const RCC: *const RegisterBlock = 0x40021000 as *const _;
stm32ral/stm32f0/instances/rcc.rs

stm32ral/stm32f0/instances/
rcc.rs
