stm32ral/stm32f3/peripherals/tim16_v2.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General-purpose-timers
4//!
5//! Used by: stm32f302, stm32f303, stm32f3x4
6
7use crate::{RWRegister, WORegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Counter enable
15 pub mod CEN {
16 /// Offset (0 bits)
17 pub const offset: u32 = 0;
18 /// Mask (1 bit: 1 << 0)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b0: Counter disabled
28 pub const Disabled: u32 = 0b0;
29
30 /// 0b1: Counter enabled
31 pub const Enabled: u32 = 0b1;
32 }
33 }
34
35 /// Update disable
36 pub mod UDIS {
37 /// Offset (1 bits)
38 pub const offset: u32 = 1;
39 /// Mask (1 bit: 1 << 1)
40 pub const mask: u32 = 1 << offset;
41 /// Read-only values (empty)
42 pub mod R {}
43 /// Write-only values (empty)
44 pub mod W {}
45 /// Read-write values
46 pub mod RW {
47
48 /// 0b0: Update event enabled
49 pub const Enabled: u32 = 0b0;
50
51 /// 0b1: Update event disabled
52 pub const Disabled: u32 = 0b1;
53 }
54 }
55
56 /// Update request source
57 pub mod URS {
58 /// Offset (2 bits)
59 pub const offset: u32 = 2;
60 /// Mask (1 bit: 1 << 2)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values
67 pub mod RW {
68
69 /// 0b0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
70 pub const AnyEvent: u32 = 0b0;
71
72 /// 0b1: Only counter overflow/underflow generates an update interrupt or DMA request
73 pub const CounterOnly: u32 = 0b1;
74 }
75 }
76
77 /// One-pulse mode
78 pub mod OPM {
79 /// Offset (3 bits)
80 pub const offset: u32 = 3;
81 /// Mask (1 bit: 1 << 3)
82 pub const mask: u32 = 1 << offset;
83 /// Read-only values (empty)
84 pub mod R {}
85 /// Write-only values (empty)
86 pub mod W {}
87 /// Read-write values
88 pub mod RW {
89
90 /// 0b0: Counter is not stopped at update event
91 pub const Disabled: u32 = 0b0;
92
93 /// 0b1: Counter stops counting at the next update event (clearing the CEN bit)
94 pub const Enabled: u32 = 0b1;
95 }
96 }
97
98 /// Auto-reload preload enable
99 pub mod ARPE {
100 /// Offset (7 bits)
101 pub const offset: u32 = 7;
102 /// Mask (1 bit: 1 << 7)
103 pub const mask: u32 = 1 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values
109 pub mod RW {
110
111 /// 0b0: TIMx_APRR register is not buffered
112 pub const Disabled: u32 = 0b0;
113
114 /// 0b1: TIMx_APRR register is buffered
115 pub const Enabled: u32 = 0b1;
116 }
117 }
118
119 /// Clock division
120 pub mod CKD {
121 /// Offset (8 bits)
122 pub const offset: u32 = 8;
123 /// Mask (2 bits: 0b11 << 8)
124 pub const mask: u32 = 0b11 << offset;
125 /// Read-only values (empty)
126 pub mod R {}
127 /// Write-only values (empty)
128 pub mod W {}
129 /// Read-write values
130 pub mod RW {
131
132 /// 0b00: t_DTS = t_CK_INT
133 pub const Div1: u32 = 0b00;
134
135 /// 0b01: t_DTS = 2 × t_CK_INT
136 pub const Div2: u32 = 0b01;
137
138 /// 0b10: t_DTS = 4 × t_CK_INT
139 pub const Div4: u32 = 0b10;
140 }
141 }
142
143 /// UIF status bit remapping
144 pub mod UIFREMAP {
145 /// Offset (11 bits)
146 pub const offset: u32 = 11;
147 /// Mask (1 bit: 1 << 11)
148 pub const mask: u32 = 1 << offset;
149 /// Read-only values (empty)
150 pub mod R {}
151 /// Write-only values (empty)
152 pub mod W {}
153 /// Read-write values (empty)
154 pub mod RW {}
155 }
156}
157
158/// control register 2
159pub mod CR2 {
160
161 /// Output Idle state 1
162 pub mod OIS1N {
163 /// Offset (9 bits)
164 pub const offset: u32 = 9;
165 /// Mask (1 bit: 1 << 9)
166 pub const mask: u32 = 1 << offset;
167 /// Read-only values (empty)
168 pub mod R {}
169 /// Write-only values (empty)
170 pub mod W {}
171 /// Read-write values
172 pub mod RW {
173
174 /// 0b0: OC1N=0 after a dead-time when MOE=0
175 pub const Low: u32 = 0b0;
176
177 /// 0b1: OC1N=1 after a dead-time when MOE=0
178 pub const High: u32 = 0b1;
179 }
180 }
181
182 /// Output Idle state 1
183 pub mod OIS1 {
184 /// Offset (8 bits)
185 pub const offset: u32 = 8;
186 /// Mask (1 bit: 1 << 8)
187 pub const mask: u32 = 1 << offset;
188 /// Read-only values (empty)
189 pub mod R {}
190 /// Write-only values (empty)
191 pub mod W {}
192 /// Read-write values
193 pub mod RW {
194
195 /// 0b0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
196 pub const Low: u32 = 0b0;
197
198 /// 0b1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
199 pub const High: u32 = 0b1;
200 }
201 }
202
203 /// Capture/compare DMA selection
204 pub mod CCDS {
205 /// Offset (3 bits)
206 pub const offset: u32 = 3;
207 /// Mask (1 bit: 1 << 3)
208 pub const mask: u32 = 1 << offset;
209 /// Read-only values (empty)
210 pub mod R {}
211 /// Write-only values (empty)
212 pub mod W {}
213 /// Read-write values
214 pub mod RW {
215
216 /// 0b0: CCx DMA request sent when CCx event occurs
217 pub const OnCompare: u32 = 0b0;
218
219 /// 0b1: CCx DMA request sent when update event occurs
220 pub const OnUpdate: u32 = 0b1;
221 }
222 }
223
224 /// Capture/compare control update selection
225 pub mod CCUS {
226 /// Offset (2 bits)
227 pub const offset: u32 = 2;
228 /// Mask (1 bit: 1 << 2)
229 pub const mask: u32 = 1 << offset;
230 /// Read-only values (empty)
231 pub mod R {}
232 /// Write-only values (empty)
233 pub mod W {}
234 /// Read-write values
235 pub mod RW {
236
237 /// 0b0: Capture/compare are updated only by setting the COMG bit
238 pub const Default: u32 = 0b0;
239
240 /// 0b1: Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI
241 pub const WithRisingEdge: u32 = 0b1;
242 }
243 }
244
245 /// Capture/compare preloaded control
246 pub mod CCPC {
247 /// Offset (0 bits)
248 pub const offset: u32 = 0;
249 /// Mask (1 bit: 1 << 0)
250 pub const mask: u32 = 1 << offset;
251 /// Read-only values (empty)
252 pub mod R {}
253 /// Write-only values (empty)
254 pub mod W {}
255 /// Read-write values
256 pub mod RW {
257
258 /// 0b0: CCxE, CCxNE and OCxM bits are not preloaded
259 pub const NotPreloaded: u32 = 0b0;
260
261 /// 0b1: CCxE, CCxNE and OCxM bits are preloaded
262 pub const Preloaded: u32 = 0b1;
263 }
264 }
265}
266
267/// DMA/Interrupt enable register
268pub mod DIER {
269
270 /// Update interrupt enable
271 pub mod UIE {
272 /// Offset (0 bits)
273 pub const offset: u32 = 0;
274 /// Mask (1 bit: 1 << 0)
275 pub const mask: u32 = 1 << offset;
276 /// Read-only values (empty)
277 pub mod R {}
278 /// Write-only values (empty)
279 pub mod W {}
280 /// Read-write values
281 pub mod RW {
282
283 /// 0b0: Update interrupt disabled
284 pub const Disabled: u32 = 0b0;
285
286 /// 0b1: Update interrupt enabled
287 pub const Enabled: u32 = 0b1;
288 }
289 }
290
291 /// Capture/Compare 1 interrupt enable
292 pub mod CC1IE {
293 /// Offset (1 bits)
294 pub const offset: u32 = 1;
295 /// Mask (1 bit: 1 << 1)
296 pub const mask: u32 = 1 << offset;
297 /// Read-only values (empty)
298 pub mod R {}
299 /// Write-only values (empty)
300 pub mod W {}
301 /// Read-write values
302 pub mod RW {
303
304 /// 0b0: CC1 interrupt disabled
305 pub const Disabled: u32 = 0b0;
306
307 /// 0b1: CC1 interrupt enabled
308 pub const Enabled: u32 = 0b1;
309 }
310 }
311
312 /// COM interrupt enable
313 pub mod COMIE {
314 /// Offset (5 bits)
315 pub const offset: u32 = 5;
316 /// Mask (1 bit: 1 << 5)
317 pub const mask: u32 = 1 << offset;
318 /// Read-only values (empty)
319 pub mod R {}
320 /// Write-only values (empty)
321 pub mod W {}
322 /// Read-write values
323 pub mod RW {
324
325 /// 0b0: COM interrupt disabled
326 pub const Disabled: u32 = 0b0;
327
328 /// 0b1: COM interrupt enabled
329 pub const Enabled: u32 = 0b1;
330 }
331 }
332
333 /// Trigger interrupt enable
334 pub mod TIE {
335 /// Offset (6 bits)
336 pub const offset: u32 = 6;
337 /// Mask (1 bit: 1 << 6)
338 pub const mask: u32 = 1 << offset;
339 /// Read-only values (empty)
340 pub mod R {}
341 /// Write-only values (empty)
342 pub mod W {}
343 /// Read-write values (empty)
344 pub mod RW {}
345 }
346
347 /// Break interrupt enable
348 pub mod BIE {
349 /// Offset (7 bits)
350 pub const offset: u32 = 7;
351 /// Mask (1 bit: 1 << 7)
352 pub const mask: u32 = 1 << offset;
353 /// Read-only values (empty)
354 pub mod R {}
355 /// Write-only values (empty)
356 pub mod W {}
357 /// Read-write values
358 pub mod RW {
359
360 /// 0b0: Break interrupt disabled
361 pub const Disabled: u32 = 0b0;
362
363 /// 0b1: Break interrupt enabled
364 pub const Enabled: u32 = 0b1;
365 }
366 }
367
368 /// Update DMA request enable
369 pub mod UDE {
370 /// Offset (8 bits)
371 pub const offset: u32 = 8;
372 /// Mask (1 bit: 1 << 8)
373 pub const mask: u32 = 1 << offset;
374 /// Read-only values (empty)
375 pub mod R {}
376 /// Write-only values (empty)
377 pub mod W {}
378 /// Read-write values (empty)
379 pub mod RW {}
380 }
381
382 /// Capture/Compare 1 DMA request enable
383 pub mod CC1DE {
384 /// Offset (9 bits)
385 pub const offset: u32 = 9;
386 /// Mask (1 bit: 1 << 9)
387 pub const mask: u32 = 1 << offset;
388 /// Read-only values (empty)
389 pub mod R {}
390 /// Write-only values (empty)
391 pub mod W {}
392 /// Read-write values
393 pub mod RW {
394
395 /// 0b0: CC1 DMA request disabled
396 pub const Disabled: u32 = 0b0;
397
398 /// 0b1: CC1 DMA request enabled
399 pub const Enabled: u32 = 0b1;
400 }
401 }
402
403 /// COM DMA request enable
404 pub mod COMDE {
405 /// Offset (13 bits)
406 pub const offset: u32 = 13;
407 /// Mask (1 bit: 1 << 13)
408 pub const mask: u32 = 1 << offset;
409 /// Read-only values (empty)
410 pub mod R {}
411 /// Write-only values (empty)
412 pub mod W {}
413 /// Read-write values (empty)
414 pub mod RW {}
415 }
416
417 /// Trigger DMA request enable
418 pub mod TDE {
419 /// Offset (14 bits)
420 pub const offset: u32 = 14;
421 /// Mask (1 bit: 1 << 14)
422 pub const mask: u32 = 1 << offset;
423 /// Read-only values (empty)
424 pub mod R {}
425 /// Write-only values (empty)
426 pub mod W {}
427 /// Read-write values (empty)
428 pub mod RW {}
429 }
430}
431
432/// status register
433pub mod SR {
434
435 /// Capture/Compare 1 overcapture flag
436 pub mod CC1OF {
437 /// Offset (9 bits)
438 pub const offset: u32 = 9;
439 /// Mask (1 bit: 1 << 9)
440 pub const mask: u32 = 1 << offset;
441 /// Read-only values (empty)
442 pub mod R {}
443 /// Write-only values (empty)
444 pub mod W {}
445 /// Read-write values (empty)
446 pub mod RW {}
447 }
448
449 /// Break interrupt flag
450 pub mod BIF {
451 /// Offset (7 bits)
452 pub const offset: u32 = 7;
453 /// Mask (1 bit: 1 << 7)
454 pub const mask: u32 = 1 << offset;
455 /// Read-only values (empty)
456 pub mod R {}
457 /// Write-only values (empty)
458 pub mod W {}
459 /// Read-write values (empty)
460 pub mod RW {}
461 }
462
463 /// Trigger interrupt flag
464 pub mod TIF {
465 /// Offset (6 bits)
466 pub const offset: u32 = 6;
467 /// Mask (1 bit: 1 << 6)
468 pub const mask: u32 = 1 << offset;
469 /// Read-only values (empty)
470 pub mod R {}
471 /// Write-only values (empty)
472 pub mod W {}
473 /// Read-write values (empty)
474 pub mod RW {}
475 }
476
477 /// COM interrupt flag
478 pub mod COMIF {
479 /// Offset (5 bits)
480 pub const offset: u32 = 5;
481 /// Mask (1 bit: 1 << 5)
482 pub const mask: u32 = 1 << offset;
483 /// Read-only values (empty)
484 pub mod R {}
485 /// Write-only values (empty)
486 pub mod W {}
487 /// Read-write values (empty)
488 pub mod RW {}
489 }
490
491 /// Capture/compare 1 interrupt flag
492 pub mod CC1IF {
493 /// Offset (1 bits)
494 pub const offset: u32 = 1;
495 /// Mask (1 bit: 1 << 1)
496 pub const mask: u32 = 1 << offset;
497 /// Read-only values (empty)
498 pub mod R {}
499 /// Write-only values (empty)
500 pub mod W {}
501 /// Read-write values (empty)
502 pub mod RW {}
503 }
504
505 /// Update interrupt flag
506 pub mod UIF {
507 /// Offset (0 bits)
508 pub const offset: u32 = 0;
509 /// Mask (1 bit: 1 << 0)
510 pub const mask: u32 = 1 << offset;
511 /// Read-only values (empty)
512 pub mod R {}
513 /// Write-only values (empty)
514 pub mod W {}
515 /// Read-write values
516 pub mod RW {
517
518 /// 0b0: No update occurred
519 pub const Clear: u32 = 0b0;
520
521 /// 0b1: Update interrupt pending.
522 pub const UpdatePending: u32 = 0b1;
523 }
524 }
525}
526
527/// event generation register
528pub mod EGR {
529
530 /// Break generation
531 pub mod BG {
532 /// Offset (7 bits)
533 pub const offset: u32 = 7;
534 /// Mask (1 bit: 1 << 7)
535 pub const mask: u32 = 1 << offset;
536 /// Read-only values (empty)
537 pub mod R {}
538 /// Write-only values (empty)
539 pub mod W {}
540 /// Read-write values (empty)
541 pub mod RW {}
542 }
543
544 /// Trigger generation
545 pub mod TG {
546 /// Offset (6 bits)
547 pub const offset: u32 = 6;
548 /// Mask (1 bit: 1 << 6)
549 pub const mask: u32 = 1 << offset;
550 /// Read-only values (empty)
551 pub mod R {}
552 /// Write-only values (empty)
553 pub mod W {}
554 /// Read-write values (empty)
555 pub mod RW {}
556 }
557
558 /// Capture/Compare control update generation
559 pub mod COMG {
560 /// Offset (5 bits)
561 pub const offset: u32 = 5;
562 /// Mask (1 bit: 1 << 5)
563 pub const mask: u32 = 1 << offset;
564 /// Read-only values (empty)
565 pub mod R {}
566 /// Write-only values (empty)
567 pub mod W {}
568 /// Read-write values (empty)
569 pub mod RW {}
570 }
571
572 /// Capture/compare 1 generation
573 pub mod CC1G {
574 /// Offset (1 bits)
575 pub const offset: u32 = 1;
576 /// Mask (1 bit: 1 << 1)
577 pub const mask: u32 = 1 << offset;
578 /// Read-only values (empty)
579 pub mod R {}
580 /// Write-only values (empty)
581 pub mod W {}
582 /// Read-write values (empty)
583 pub mod RW {}
584 }
585
586 /// Update generation
587 pub mod UG {
588 /// Offset (0 bits)
589 pub const offset: u32 = 0;
590 /// Mask (1 bit: 1 << 0)
591 pub const mask: u32 = 1 << offset;
592 /// Read-only values (empty)
593 pub mod R {}
594 /// Write-only values
595 pub mod W {
596
597 /// 0b1: Re-initializes the timer counter and generates an update of the registers.
598 pub const Update: u32 = 0b1;
599 }
600 /// Read-write values (empty)
601 pub mod RW {}
602 }
603}
604
605/// CCMR1_Output and CCMR1_Input
606/// CCMR1_Output: capture/compare mode register (output mode)
607/// CCMR1_Input: capture/compare mode register 1 (input mode)
608pub mod CCMR1 {
609
610 /// Capture/Compare 1 selection
611 pub mod CC1S {
612 /// Offset (0 bits)
613 pub const offset: u32 = 0;
614 /// Mask (2 bits: 0b11 << 0)
615 pub const mask: u32 = 0b11 << offset;
616 /// Read-only values (empty)
617 pub mod R {}
618 /// Write-only values (empty)
619 pub mod W {}
620 /// Read-write values (empty)
621 pub mod RW {}
622 }
623
624 /// Output Compare 1 fast enable
625 pub mod OC1FE {
626 /// Offset (2 bits)
627 pub const offset: u32 = 2;
628 /// Mask (1 bit: 1 << 2)
629 pub const mask: u32 = 1 << offset;
630 /// Read-only values (empty)
631 pub mod R {}
632 /// Write-only values (empty)
633 pub mod W {}
634 /// Read-write values (empty)
635 pub mod RW {}
636 }
637
638 /// Output Compare 1 preload enable
639 pub mod OC1PE {
640 /// Offset (3 bits)
641 pub const offset: u32 = 3;
642 /// Mask (1 bit: 1 << 3)
643 pub const mask: u32 = 1 << offset;
644 /// Read-only values (empty)
645 pub mod R {}
646 /// Write-only values (empty)
647 pub mod W {}
648 /// Read-write values (empty)
649 pub mod RW {}
650 }
651
652 /// Output Compare 1 mode
653 pub mod OC1M {
654 /// Offset (4 bits)
655 pub const offset: u32 = 4;
656 /// Mask (3 bits: 0b111 << 4)
657 pub const mask: u32 = 0b111 << offset;
658 /// Read-only values (empty)
659 pub mod R {}
660 /// Write-only values (empty)
661 pub mod W {}
662 /// Read-write values
663 pub mod RW {
664
665 /// 0b000: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
666 pub const Frozen: u32 = 0b000;
667
668 /// 0b001: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
669 pub const ActiveOnMatch: u32 = 0b001;
670
671 /// 0b010: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
672 pub const InactiveOnMatch: u32 = 0b010;
673
674 /// 0b011: OCyREF toggles when TIMx_CNT=TIMx_CCRy
675 pub const Toggle: u32 = 0b011;
676
677 /// 0b100: OCyREF is forced low
678 pub const ForceInactive: u32 = 0b100;
679
680 /// 0b101: OCyREF is forced high
681 pub const ForceActive: u32 = 0b101;
682
683 /// 0b110: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
684 pub const PwmMode1: u32 = 0b110;
685
686 /// 0b111: Inversely to PwmMode1
687 pub const PwmMode2: u32 = 0b111;
688 }
689 }
690
691 /// Output Compare 1 mode
692 pub mod OC1M_3 {
693 /// Offset (16 bits)
694 pub const offset: u32 = 16;
695 /// Mask (1 bit: 1 << 16)
696 pub const mask: u32 = 1 << offset;
697 /// Read-only values (empty)
698 pub mod R {}
699 /// Write-only values (empty)
700 pub mod W {}
701 /// Read-write values (empty)
702 pub mod RW {}
703 }
704
705 /// Input capture 1 filter
706 pub mod IC1F {
707 /// Offset (4 bits)
708 pub const offset: u32 = 4;
709 /// Mask (4 bits: 0b1111 << 4)
710 pub const mask: u32 = 0b1111 << offset;
711 /// Read-only values (empty)
712 pub mod R {}
713 /// Write-only values (empty)
714 pub mod W {}
715 /// Read-write values (empty)
716 pub mod RW {}
717 }
718
719 /// Input capture 1 prescaler
720 pub mod IC1PSC {
721 /// Offset (2 bits)
722 pub const offset: u32 = 2;
723 /// Mask (2 bits: 0b11 << 2)
724 pub const mask: u32 = 0b11 << offset;
725 /// Read-only values (empty)
726 pub mod R {}
727 /// Write-only values (empty)
728 pub mod W {}
729 /// Read-write values (empty)
730 pub mod RW {}
731 }
732}
733
734/// capture/compare enable register
735pub mod CCER {
736
737 /// Capture/Compare 1 output Polarity
738 pub mod CC1NP {
739 /// Offset (3 bits)
740 pub const offset: u32 = 3;
741 /// Mask (1 bit: 1 << 3)
742 pub const mask: u32 = 1 << offset;
743 /// Read-only values (empty)
744 pub mod R {}
745 /// Write-only values (empty)
746 pub mod W {}
747 /// Read-write values (empty)
748 pub mod RW {}
749 }
750
751 /// Capture/Compare 1 complementary output enable
752 pub mod CC1NE {
753 /// Offset (2 bits)
754 pub const offset: u32 = 2;
755 /// Mask (1 bit: 1 << 2)
756 pub const mask: u32 = 1 << offset;
757 /// Read-only values (empty)
758 pub mod R {}
759 /// Write-only values (empty)
760 pub mod W {}
761 /// Read-write values (empty)
762 pub mod RW {}
763 }
764
765 /// Capture/Compare 1 output Polarity
766 pub mod CC1P {
767 /// Offset (1 bits)
768 pub const offset: u32 = 1;
769 /// Mask (1 bit: 1 << 1)
770 pub const mask: u32 = 1 << offset;
771 /// Read-only values (empty)
772 pub mod R {}
773 /// Write-only values (empty)
774 pub mod W {}
775 /// Read-write values (empty)
776 pub mod RW {}
777 }
778
779 /// Capture/Compare 1 output enable
780 pub mod CC1E {
781 /// Offset (0 bits)
782 pub const offset: u32 = 0;
783 /// Mask (1 bit: 1 << 0)
784 pub const mask: u32 = 1 << offset;
785 /// Read-only values (empty)
786 pub mod R {}
787 /// Write-only values (empty)
788 pub mod W {}
789 /// Read-write values (empty)
790 pub mod RW {}
791 }
792}
793
794/// counter
795pub mod CNT {
796
797 /// counter value
798 pub mod CNT {
799 /// Offset (0 bits)
800 pub const offset: u32 = 0;
801 /// Mask (16 bits: 0xffff << 0)
802 pub const mask: u32 = 0xffff << offset;
803 /// Read-only values (empty)
804 pub mod R {}
805 /// Write-only values (empty)
806 pub mod W {}
807 /// Read-write values (empty)
808 pub mod RW {}
809 }
810
811 /// UIF Copy
812 pub mod UIFCPY {
813 /// Offset (31 bits)
814 pub const offset: u32 = 31;
815 /// Mask (1 bit: 1 << 31)
816 pub const mask: u32 = 1 << offset;
817 /// Read-only values (empty)
818 pub mod R {}
819 /// Write-only values (empty)
820 pub mod W {}
821 /// Read-write values (empty)
822 pub mod RW {}
823 }
824}
825
826/// prescaler
827pub mod PSC {
828
829 /// Prescaler value
830 pub mod PSC {
831 /// Offset (0 bits)
832 pub const offset: u32 = 0;
833 /// Mask (16 bits: 0xffff << 0)
834 pub const mask: u32 = 0xffff << offset;
835 /// Read-only values (empty)
836 pub mod R {}
837 /// Write-only values (empty)
838 pub mod W {}
839 /// Read-write values (empty)
840 pub mod RW {}
841 }
842}
843
844/// auto-reload register
845pub mod ARR {
846
847 /// Auto-reload value
848 pub mod ARR {
849 /// Offset (0 bits)
850 pub const offset: u32 = 0;
851 /// Mask (16 bits: 0xffff << 0)
852 pub const mask: u32 = 0xffff << offset;
853 /// Read-only values (empty)
854 pub mod R {}
855 /// Write-only values (empty)
856 pub mod W {}
857 /// Read-write values (empty)
858 pub mod RW {}
859 }
860}
861
862/// repetition counter register
863pub mod RCR {
864
865 /// Repetition counter value
866 pub mod REP {
867 /// Offset (0 bits)
868 pub const offset: u32 = 0;
869 /// Mask (8 bits: 0xff << 0)
870 pub const mask: u32 = 0xff << offset;
871 /// Read-only values (empty)
872 pub mod R {}
873 /// Write-only values (empty)
874 pub mod W {}
875 /// Read-write values (empty)
876 pub mod RW {}
877 }
878}
879
880/// capture/compare register
881pub mod CCR1 {
882
883 /// Capture/Compare value
884 pub mod CCR {
885 /// Offset (0 bits)
886 pub const offset: u32 = 0;
887 /// Mask (16 bits: 0xffff << 0)
888 pub const mask: u32 = 0xffff << offset;
889 /// Read-only values (empty)
890 pub mod R {}
891 /// Write-only values (empty)
892 pub mod W {}
893 /// Read-write values (empty)
894 pub mod RW {}
895 }
896}
897
898/// break and dead-time register
899pub mod BDTR {
900
901 /// Dead-time generator setup
902 pub mod DTG {
903 /// Offset (0 bits)
904 pub const offset: u32 = 0;
905 /// Mask (8 bits: 0xff << 0)
906 pub const mask: u32 = 0xff << offset;
907 /// Read-only values (empty)
908 pub mod R {}
909 /// Write-only values (empty)
910 pub mod W {}
911 /// Read-write values (empty)
912 pub mod RW {}
913 }
914
915 /// Lock configuration
916 pub mod LOCK {
917 /// Offset (8 bits)
918 pub const offset: u32 = 8;
919 /// Mask (2 bits: 0b11 << 8)
920 pub const mask: u32 = 0b11 << offset;
921 /// Read-only values (empty)
922 pub mod R {}
923 /// Write-only values (empty)
924 pub mod W {}
925 /// Read-write values (empty)
926 pub mod RW {}
927 }
928
929 /// Off-state selection for Idle mode
930 pub mod OSSI {
931 /// Offset (10 bits)
932 pub const offset: u32 = 10;
933 /// Mask (1 bit: 1 << 10)
934 pub const mask: u32 = 1 << offset;
935 /// Read-only values (empty)
936 pub mod R {}
937 /// Write-only values (empty)
938 pub mod W {}
939 /// Read-write values (empty)
940 pub mod RW {}
941 }
942
943 /// Off-state selection for Run mode
944 pub mod OSSR {
945 /// Offset (11 bits)
946 pub const offset: u32 = 11;
947 /// Mask (1 bit: 1 << 11)
948 pub const mask: u32 = 1 << offset;
949 /// Read-only values (empty)
950 pub mod R {}
951 /// Write-only values (empty)
952 pub mod W {}
953 /// Read-write values (empty)
954 pub mod RW {}
955 }
956
957 /// Break enable
958 pub mod BKE {
959 /// Offset (12 bits)
960 pub const offset: u32 = 12;
961 /// Mask (1 bit: 1 << 12)
962 pub const mask: u32 = 1 << offset;
963 /// Read-only values (empty)
964 pub mod R {}
965 /// Write-only values (empty)
966 pub mod W {}
967 /// Read-write values (empty)
968 pub mod RW {}
969 }
970
971 /// Break polarity
972 pub mod BKP {
973 /// Offset (13 bits)
974 pub const offset: u32 = 13;
975 /// Mask (1 bit: 1 << 13)
976 pub const mask: u32 = 1 << offset;
977 /// Read-only values (empty)
978 pub mod R {}
979 /// Write-only values (empty)
980 pub mod W {}
981 /// Read-write values (empty)
982 pub mod RW {}
983 }
984
985 /// Automatic output enable
986 pub mod AOE {
987 /// Offset (14 bits)
988 pub const offset: u32 = 14;
989 /// Mask (1 bit: 1 << 14)
990 pub const mask: u32 = 1 << offset;
991 /// Read-only values (empty)
992 pub mod R {}
993 /// Write-only values (empty)
994 pub mod W {}
995 /// Read-write values (empty)
996 pub mod RW {}
997 }
998
999 /// Main output enable
1000 pub mod MOE {
1001 /// Offset (15 bits)
1002 pub const offset: u32 = 15;
1003 /// Mask (1 bit: 1 << 15)
1004 pub const mask: u32 = 1 << offset;
1005 /// Read-only values (empty)
1006 pub mod R {}
1007 /// Write-only values (empty)
1008 pub mod W {}
1009 /// Read-write values (empty)
1010 pub mod RW {}
1011 }
1012
1013 /// Break filter
1014 pub mod BKF {
1015 /// Offset (16 bits)
1016 pub const offset: u32 = 16;
1017 /// Mask (4 bits: 0b1111 << 16)
1018 pub const mask: u32 = 0b1111 << offset;
1019 /// Read-only values (empty)
1020 pub mod R {}
1021 /// Write-only values (empty)
1022 pub mod W {}
1023 /// Read-write values (empty)
1024 pub mod RW {}
1025 }
1026}
1027
1028/// DMA control register
1029pub mod DCR {
1030
1031 /// DMA burst length
1032 pub mod DBL {
1033 /// Offset (8 bits)
1034 pub const offset: u32 = 8;
1035 /// Mask (5 bits: 0b11111 << 8)
1036 pub const mask: u32 = 0b11111 << offset;
1037 /// Read-only values (empty)
1038 pub mod R {}
1039 /// Write-only values (empty)
1040 pub mod W {}
1041 /// Read-write values (empty)
1042 pub mod RW {}
1043 }
1044
1045 /// DMA base address
1046 pub mod DBA {
1047 /// Offset (0 bits)
1048 pub const offset: u32 = 0;
1049 /// Mask (5 bits: 0b11111 << 0)
1050 pub const mask: u32 = 0b11111 << offset;
1051 /// Read-only values (empty)
1052 pub mod R {}
1053 /// Write-only values (empty)
1054 pub mod W {}
1055 /// Read-write values (empty)
1056 pub mod RW {}
1057 }
1058}
1059
1060/// DMA address for full transfer
1061pub mod DMAR {
1062
1063 /// DMA register for burst accesses
1064 pub mod DMAB {
1065 /// Offset (0 bits)
1066 pub const offset: u32 = 0;
1067 /// Mask (16 bits: 0xffff << 0)
1068 pub const mask: u32 = 0xffff << offset;
1069 /// Read-only values (empty)
1070 pub mod R {}
1071 /// Write-only values (empty)
1072 pub mod W {}
1073 /// Read-write values (empty)
1074 pub mod RW {}
1075 }
1076}
1077
1078/// option register
1079pub mod OR {}
1080#[repr(C)]
1081pub struct RegisterBlock {
1082 /// control register 1
1083 pub CR1: RWRegister<u32>,
1084
1085 /// control register 2
1086 pub CR2: RWRegister<u32>,
1087
1088 _reserved1: [u8; 4],
1089
1090 /// DMA/Interrupt enable register
1091 pub DIER: RWRegister<u32>,
1092
1093 /// status register
1094 pub SR: RWRegister<u32>,
1095
1096 /// event generation register
1097 pub EGR: WORegister<u32>,
1098
1099 /// CCMR1_Output and CCMR1_Input
1100 /// CCMR1_Output: capture/compare mode register (output mode)
1101 /// CCMR1_Input: capture/compare mode register 1 (input mode)
1102 pub CCMR1: RWRegister<u32>,
1103
1104 _reserved2: [u8; 4],
1105
1106 /// capture/compare enable register
1107 pub CCER: RWRegister<u32>,
1108
1109 /// counter
1110 pub CNT: RWRegister<u32>,
1111
1112 /// prescaler
1113 pub PSC: RWRegister<u32>,
1114
1115 /// auto-reload register
1116 pub ARR: RWRegister<u32>,
1117
1118 /// repetition counter register
1119 pub RCR: RWRegister<u32>,
1120
1121 /// capture/compare register
1122 pub CCR1: RWRegister<u32>,
1123
1124 _reserved3: [u8; 12],
1125
1126 /// break and dead-time register
1127 pub BDTR: RWRegister<u32>,
1128
1129 /// DMA control register
1130 pub DCR: RWRegister<u32>,
1131
1132 /// DMA address for full transfer
1133 pub DMAR: RWRegister<u32>,
1134
1135 /// option register
1136 pub OR: RWRegister<u32>,
1137}
1138pub struct ResetValues {
1139 pub CR1: u32,
1140 pub CR2: u32,
1141 pub DIER: u32,
1142 pub SR: u32,
1143 pub EGR: u32,
1144 pub CCMR1: u32,
1145 pub CCER: u32,
1146 pub CNT: u32,
1147 pub PSC: u32,
1148 pub ARR: u32,
1149 pub RCR: u32,
1150 pub CCR1: u32,
1151 pub BDTR: u32,
1152 pub DCR: u32,
1153 pub DMAR: u32,
1154 pub OR: u32,
1155}
1156#[cfg(not(feature = "nosync"))]
1157pub struct Instance {
1158 pub(crate) addr: u32,
1159 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1160}
1161#[cfg(not(feature = "nosync"))]
1162impl ::core::ops::Deref for Instance {
1163 type Target = RegisterBlock;
1164 #[inline(always)]
1165 fn deref(&self) -> &RegisterBlock {
1166 unsafe { &*(self.addr as *const _) }
1167 }
1168}
1169#[cfg(feature = "rtic")]
1170unsafe impl Send for Instance {}