stm32ral/stm32f7/instances/
tim3.rs

1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! General purpose timers
4//!
5//! Used by: stm32f730, stm32f745, stm32f750, stm32f765, stm32f7x2, stm32f7x3, stm32f7x6, stm32f7x7, stm32f7x9
6
7#[cfg(not(feature = "nosync"))]
8pub use crate::stm32f7::peripherals::tim3::Instance;
9pub use crate::stm32f7::peripherals::tim3::{RegisterBlock, ResetValues};
10pub use crate::stm32f7::peripherals::tim3::{
11    ARR, CCER, CCMR1, CCMR2, CCR1, CCR2, CCR3, CCR4, CNT, CR1, CR2, DCR, DIER, DMAR, EGR, PSC,
12    SMCR, SR,
13};
14
15/// Access functions for the TIM3 peripheral instance
16pub mod TIM3 {
17    use super::ResetValues;
18
19    #[cfg(not(feature = "nosync"))]
20    use super::Instance;
21
22    #[cfg(not(feature = "nosync"))]
23    const INSTANCE: Instance = Instance {
24        addr: 0x40000400,
25        _marker: ::core::marker::PhantomData,
26    };
27
28    /// Reset values for each field in TIM3
29    pub const reset: ResetValues = ResetValues {
30        CR1: 0x00000000,
31        CR2: 0x00000000,
32        SMCR: 0x00000000,
33        DIER: 0x00000000,
34        SR: 0x00000000,
35        EGR: 0x00000000,
36        CCMR1: 0x00000000,
37        CCMR2: 0x00000000,
38        CCER: 0x00000000,
39        CNT: 0x00000000,
40        PSC: 0x00000000,
41        ARR: 0x00000000,
42        CCR1: 0x00000000,
43        CCR2: 0x00000000,
44        CCR3: 0x00000000,
45        CCR4: 0x00000000,
46        DCR: 0x00000000,
47        DMAR: 0x00000000,
48    };
49
50    #[cfg(not(feature = "nosync"))]
51    #[allow(renamed_and_removed_lints)]
52    #[allow(private_no_mangle_statics)]
53    #[no_mangle]
54    static mut TIM3_TAKEN: bool = false;
55
56    /// Safe access to TIM3
57    ///
58    /// This function returns `Some(Instance)` if this instance is not
59    /// currently taken, and `None` if it is. This ensures that if you
60    /// do get `Some(Instance)`, you are ensured unique access to
61    /// the peripheral and there cannot be data races (unless other
62    /// code uses `unsafe`, of course). You can then pass the
63    /// `Instance` around to other functions as required. When you're
64    /// done with it, you can call `release(instance)` to return it.
65    ///
66    /// `Instance` itself dereferences to a `RegisterBlock`, which
67    /// provides access to the peripheral's registers.
68    #[cfg(not(feature = "nosync"))]
69    #[inline]
70    pub fn take() -> Option<Instance> {
71        external_cortex_m::interrupt::free(|_| unsafe {
72            if TIM3_TAKEN {
73                None
74            } else {
75                TIM3_TAKEN = true;
76                Some(INSTANCE)
77            }
78        })
79    }
80
81    /// Release exclusive access to TIM3
82    ///
83    /// This function allows you to return an `Instance` so that it
84    /// is available to `take()` again. This function will panic if
85    /// you return a different `Instance` or if this instance is not
86    /// already taken.
87    #[cfg(not(feature = "nosync"))]
88    #[inline]
89    pub fn release(inst: Instance) {
90        external_cortex_m::interrupt::free(|_| unsafe {
91            if TIM3_TAKEN && inst.addr == INSTANCE.addr {
92                TIM3_TAKEN = false;
93            } else {
94                panic!("Released a peripheral which was not taken");
95            }
96        });
97    }
98
99    /// Unsafely steal TIM3
100    ///
101    /// This function is similar to take() but forcibly takes the
102    /// Instance, marking it as taken irregardless of its previous
103    /// state.
104    #[cfg(not(feature = "nosync"))]
105    #[inline]
106    pub unsafe fn steal() -> Instance {
107        TIM3_TAKEN = true;
108        INSTANCE
109    }
110}
111
112/// Raw pointer to TIM3
113///
114/// Dereferencing this is unsafe because you are not ensured unique
115/// access to the peripheral, so you may encounter data races with
116/// other users of this peripheral. It is up to you to ensure you
117/// will not cause data races.
118///
119/// This constant is provided for ease of use in unsafe code: you can
120/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
121pub const TIM3: *const RegisterBlock = 0x40000400 as *const _;
stm32ral/stm32f7/instances/tim3.rs

stm32ral/stm32f7/instances/
tim3.rs
