stm32ral/stm32l5/peripherals/fmc.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! FMC
4//!
5//! Used by: stm32l552, stm32l562
6
7use crate::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// FMC_BCR1
12pub mod BCR1 {
13
14 /// Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus.
15 pub mod MBKEN {
16 /// Offset (0 bits)
17 pub const offset: u32 = 0;
18 /// Mask (1 bit: 1 << 0)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:
29 pub mod MUXEN {
30 /// Offset (1 bits)
31 pub const offset: u32 = 1;
32 /// Mask (1 bit: 1 << 1)
33 pub const mask: u32 = 1 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// Memory type These bits define the type of external memory attached to the corresponding memory bank:
43 pub mod MTYP {
44 /// Offset (2 bits)
45 pub const offset: u32 = 2;
46 /// Mask (2 bits: 0b11 << 2)
47 pub const mask: u32 = 0b11 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// Memory data bus width Defines the external memory device width, valid for all type of memories.
57 pub mod MWID {
58 /// Offset (4 bits)
59 pub const offset: u32 = 4;
60 /// Mask (2 bits: 0b11 << 4)
61 pub const mask: u32 = 0b11 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// Flash access enable This bit enables NOR Flash memory access operations.
71 pub mod FACCEN {
72 /// Offset (6 bits)
73 pub const offset: u32 = 6;
74 /// Mask (1 bit: 1 << 6)
75 pub const mask: u32 = 1 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83
84 /// Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:
85 pub mod BURSTEN {
86 /// Offset (8 bits)
87 pub const offset: u32 = 8;
88 /// Mask (1 bit: 1 << 8)
89 pub const mask: u32 = 1 << offset;
90 /// Read-only values (empty)
91 pub mod R {}
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values (empty)
95 pub mod RW {}
96 }
97
98 /// Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:
99 pub mod WAITPOL {
100 /// Offset (9 bits)
101 pub const offset: u32 = 9;
102 /// Mask (1 bit: 1 << 9)
103 pub const mask: u32 = 1 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values (empty)
109 pub mod RW {}
110 }
111
112 /// Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:
113 pub mod WAITCFG {
114 /// Offset (11 bits)
115 pub const offset: u32 = 11;
116 /// Mask (1 bit: 1 << 11)
117 pub const mask: u32 = 1 << offset;
118 /// Read-only values (empty)
119 pub mod R {}
120 /// Write-only values (empty)
121 pub mod W {}
122 /// Read-write values (empty)
123 pub mod RW {}
124 }
125
126 /// Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:
127 pub mod WREN {
128 /// Offset (12 bits)
129 pub const offset: u32 = 12;
130 /// Mask (1 bit: 1 << 12)
131 pub const mask: u32 = 1 << offset;
132 /// Read-only values (empty)
133 pub mod R {}
134 /// Write-only values (empty)
135 pub mod W {}
136 /// Read-write values (empty)
137 pub mod RW {}
138 }
139
140 /// Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode.
141 pub mod WAITEN {
142 /// Offset (13 bits)
143 pub const offset: u32 = 13;
144 /// Mask (1 bit: 1 << 13)
145 pub const mask: u32 = 1 << offset;
146 /// Read-only values (empty)
147 pub mod R {}
148 /// Write-only values (empty)
149 pub mod W {}
150 /// Read-write values (empty)
151 pub mod RW {}
152 }
153
154 /// Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).
155 pub mod EXTMOD {
156 /// Offset (14 bits)
157 pub const offset: u32 = 14;
158 /// Mask (1 bit: 1 << 14)
159 pub const mask: u32 = 1 << offset;
160 /// Read-only values (empty)
161 pub mod R {}
162 /// Write-only values (empty)
163 pub mod W {}
164 /// Read-write values (empty)
165 pub mod RW {}
166 }
167
168 /// Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.
169 pub mod ASYNCWAIT {
170 /// Offset (15 bits)
171 pub const offset: u32 = 15;
172 /// Mask (1 bit: 1 << 15)
173 pub const mask: u32 = 1 << offset;
174 /// Read-only values (empty)
175 pub mod R {}
176 /// Write-only values (empty)
177 pub mod W {}
178 /// Read-write values (empty)
179 pub mod RW {}
180 }
181
182 /// CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved.
183 pub mod CPSIZE {
184 /// Offset (16 bits)
185 pub const offset: u32 = 16;
186 /// Mask (3 bits: 0b111 << 16)
187 pub const mask: u32 = 0b111 << offset;
188 /// Read-only values (empty)
189 pub mod R {}
190 /// Write-only values (empty)
191 pub mod W {}
192 /// Read-write values (empty)
193 pub mod RW {}
194 }
195
196 /// Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.
197 pub mod CBURSTRW {
198 /// Offset (19 bits)
199 pub const offset: u32 = 19;
200 /// Mask (1 bit: 1 << 19)
201 pub const mask: u32 = 1 << offset;
202 /// Read-only values (empty)
203 pub mod R {}
204 /// Write-only values (empty)
205 pub mod W {}
206 /// Read-write values (empty)
207 pub mod RW {}
208 }
209
210 /// Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)
211 pub mod CCLKEN {
212 /// Offset (20 bits)
213 pub const offset: u32 = 20;
214 /// Mask (1 bit: 1 << 20)
215 pub const mask: u32 = 1 << offset;
216 /// Read-only values (empty)
217 pub mod R {}
218 /// Write-only values (empty)
219 pub mod W {}
220 /// Read-write values (empty)
221 pub mod RW {}
222 }
223
224 /// Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register.
225 pub mod WFDIS {
226 /// Offset (21 bits)
227 pub const offset: u32 = 21;
228 /// Mask (1 bit: 1 << 21)
229 pub const mask: u32 = 1 << offset;
230 /// Read-only values (empty)
231 pub mod R {}
232 /// Write-only values (empty)
233 pub mod W {}
234 /// Read-write values (empty)
235 pub mod RW {}
236 }
237
238 /// NBLSET
239 pub mod NBLSET {
240 /// Offset (22 bits)
241 pub const offset: u32 = 22;
242 /// Mask (2 bits: 0b11 << 22)
243 pub const mask: u32 = 0b11 << offset;
244 /// Read-only values (empty)
245 pub mod R {}
246 /// Write-only values (empty)
247 pub mod W {}
248 /// Read-write values (empty)
249 pub mod RW {}
250 }
251}
252
253/// FMC_BCR2
254pub mod BCR2 {
255 pub use super::BCR1::ASYNCWAIT;
256 pub use super::BCR1::BURSTEN;
257 pub use super::BCR1::CBURSTRW;
258 pub use super::BCR1::CCLKEN;
259 pub use super::BCR1::CPSIZE;
260 pub use super::BCR1::EXTMOD;
261 pub use super::BCR1::FACCEN;
262 pub use super::BCR1::MBKEN;
263 pub use super::BCR1::MTYP;
264 pub use super::BCR1::MUXEN;
265 pub use super::BCR1::MWID;
266 pub use super::BCR1::NBLSET;
267 pub use super::BCR1::WAITCFG;
268 pub use super::BCR1::WAITEN;
269 pub use super::BCR1::WAITPOL;
270 pub use super::BCR1::WFDIS;
271 pub use super::BCR1::WREN;
272}
273
274/// >FMC_BCR3
275pub mod BCR3 {
276 pub use super::BCR1::ASYNCWAIT;
277 pub use super::BCR1::BURSTEN;
278 pub use super::BCR1::CBURSTRW;
279 pub use super::BCR1::CCLKEN;
280 pub use super::BCR1::CPSIZE;
281 pub use super::BCR1::EXTMOD;
282 pub use super::BCR1::FACCEN;
283 pub use super::BCR1::MBKEN;
284 pub use super::BCR1::MTYP;
285 pub use super::BCR1::MUXEN;
286 pub use super::BCR1::MWID;
287 pub use super::BCR1::NBLSET;
288 pub use super::BCR1::WAITCFG;
289 pub use super::BCR1::WAITEN;
290 pub use super::BCR1::WAITPOL;
291 pub use super::BCR1::WFDIS;
292 pub use super::BCR1::WREN;
293}
294
295/// >FMC_BCR4
296pub mod BCR4 {
297 pub use super::BCR1::ASYNCWAIT;
298 pub use super::BCR1::BURSTEN;
299 pub use super::BCR1::CBURSTRW;
300 pub use super::BCR1::CCLKEN;
301 pub use super::BCR1::CPSIZE;
302 pub use super::BCR1::EXTMOD;
303 pub use super::BCR1::FACCEN;
304 pub use super::BCR1::MBKEN;
305 pub use super::BCR1::MTYP;
306 pub use super::BCR1::MUXEN;
307 pub use super::BCR1::MWID;
308 pub use super::BCR1::NBLSET;
309 pub use super::BCR1::WAITCFG;
310 pub use super::BCR1::WAITEN;
311 pub use super::BCR1::WAITPOL;
312 pub use super::BCR1::WFDIS;
313 pub use super::BCR1::WREN;
314}
315
316/// This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
317pub mod BTR1 {
318
319 /// Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1.
320 pub mod ADDSET {
321 /// Offset (0 bits)
322 pub const offset: u32 = 0;
323 /// Mask (4 bits: 0b1111 << 0)
324 pub const mask: u32 = 0b1111 << offset;
325 /// Read-only values (empty)
326 pub mod R {}
327 /// Write-only values (empty)
328 pub mod W {}
329 /// Read-write values (empty)
330 pub mod RW {}
331 }
332
333 /// Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.
334 pub mod ADDHLD {
335 /// Offset (4 bits)
336 pub const offset: u32 = 4;
337 /// Mask (4 bits: 0b1111 << 4)
338 pub const mask: u32 = 0b1111 << offset;
339 /// Read-only values (empty)
340 pub mod R {}
341 /// Write-only values (empty)
342 pub mod W {}
343 /// Read-write values (empty)
344 pub mod RW {}
345 }
346
347 /// Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care.
348 pub mod DATAST {
349 /// Offset (8 bits)
350 pub const offset: u32 = 8;
351 /// Mask (8 bits: 0xff << 8)
352 pub const mask: u32 = 0xff << offset;
353 /// Read-only values (empty)
354 pub mod R {}
355 /// Write-only values (empty)
356 pub mod W {}
357 /// Read-write values (empty)
358 pub mod RW {}
359 }
360
361 /// Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ...
362 pub mod BUSTURN {
363 /// Offset (16 bits)
364 pub const offset: u32 = 16;
365 /// Mask (4 bits: 0b1111 << 16)
366 pub const mask: u32 = 0b1111 << offset;
367 /// Read-only values (empty)
368 pub mod R {}
369 /// Write-only values (empty)
370 pub mod W {}
371 /// Read-write values (empty)
372 pub mod RW {}
373 }
374
375 /// Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula)
376 pub mod CLKDIV {
377 /// Offset (20 bits)
378 pub const offset: u32 = 20;
379 /// Mask (4 bits: 0b1111 << 20)
380 pub const mask: u32 = 0b1111 << offset;
381 /// Read-only values (empty)
382 pub mod R {}
383 /// Write-only values (empty)
384 pub mod W {}
385 /// Read-write values (empty)
386 pub mod RW {}
387 }
388
389 /// Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles
390 pub mod DATLAT {
391 /// Offset (24 bits)
392 pub const offset: u32 = 24;
393 /// Mask (4 bits: 0b1111 << 24)
394 pub const mask: u32 = 0b1111 << offset;
395 /// Read-only values (empty)
396 pub mod R {}
397 /// Write-only values (empty)
398 pub mod W {}
399 /// Read-write values (empty)
400 pub mod RW {}
401 }
402
403 /// Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
404 pub mod ACCMOD {
405 /// Offset (28 bits)
406 pub const offset: u32 = 28;
407 /// Mask (2 bits: 0b11 << 28)
408 pub const mask: u32 = 0b11 << offset;
409 /// Read-only values (empty)
410 pub mod R {}
411 /// Write-only values (empty)
412 pub mod W {}
413 /// Read-write values (empty)
414 pub mod RW {}
415 }
416
417 /// DATAHLD
418 pub mod DATAHLD {
419 /// Offset (30 bits)
420 pub const offset: u32 = 30;
421 /// Mask (2 bits: 0b11 << 30)
422 pub const mask: u32 = 0b11 << offset;
423 /// Read-only values (empty)
424 pub mod R {}
425 /// Write-only values (empty)
426 pub mod W {}
427 /// Read-write values (empty)
428 pub mod RW {}
429 }
430}
431
432/// FMC_BTR2
433pub mod BTR2 {
434 pub use super::BTR1::ACCMOD;
435 pub use super::BTR1::ADDHLD;
436 pub use super::BTR1::ADDSET;
437 pub use super::BTR1::BUSTURN;
438 pub use super::BTR1::CLKDIV;
439 pub use super::BTR1::DATAHLD;
440 pub use super::BTR1::DATAST;
441 pub use super::BTR1::DATLAT;
442}
443
444/// FMC_BTR3
445pub mod BTR3 {
446 pub use super::BTR1::ACCMOD;
447 pub use super::BTR1::ADDHLD;
448 pub use super::BTR1::ADDSET;
449 pub use super::BTR1::BUSTURN;
450 pub use super::BTR1::CLKDIV;
451 pub use super::BTR1::DATAHLD;
452 pub use super::BTR1::DATAST;
453 pub use super::BTR1::DATLAT;
454}
455
456/// FMC_BTR4
457pub mod BTR4 {
458 pub use super::BTR1::ACCMOD;
459 pub use super::BTR1::ADDHLD;
460 pub use super::BTR1::ADDSET;
461 pub use super::BTR1::BUSTURN;
462 pub use super::BTR1::CLKDIV;
463 pub use super::BTR1::DATAHLD;
464 pub use super::BTR1::DATAST;
465 pub use super::BTR1::DATLAT;
466}
467
468/// NAND Flash control registers
469pub mod PCR {
470
471 /// Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:
472 pub mod PWAITEN {
473 /// Offset (1 bits)
474 pub const offset: u32 = 1;
475 /// Mask (1 bit: 1 << 1)
476 pub const mask: u32 = 1 << offset;
477 /// Read-only values (empty)
478 pub mod R {}
479 /// Write-only values (empty)
480 pub mod W {}
481 /// Read-write values (empty)
482 pub mod RW {}
483 }
484
485 /// NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus
486 pub mod PBKEN {
487 /// Offset (2 bits)
488 pub const offset: u32 = 2;
489 /// Mask (1 bit: 1 << 2)
490 pub const mask: u32 = 1 << offset;
491 /// Read-only values (empty)
492 pub mod R {}
493 /// Write-only values (empty)
494 pub mod W {}
495 /// Read-write values (empty)
496 pub mod RW {}
497 }
498
499 /// Memory type
500 pub mod PTYP {
501 /// Offset (3 bits)
502 pub const offset: u32 = 3;
503 /// Mask (1 bit: 1 << 3)
504 pub const mask: u32 = 1 << offset;
505 /// Read-only values (empty)
506 pub mod R {}
507 /// Write-only values (empty)
508 pub mod W {}
509 /// Read-write values (empty)
510 pub mod RW {}
511 }
512
513 /// Data bus width. These bits define the external memory device width.
514 pub mod PWID {
515 /// Offset (4 bits)
516 pub const offset: u32 = 4;
517 /// Mask (2 bits: 0b11 << 4)
518 pub const mask: u32 = 0b11 << offset;
519 /// Read-only values (empty)
520 pub mod R {}
521 /// Write-only values (empty)
522 pub mod W {}
523 /// Read-write values (empty)
524 pub mod RW {}
525 }
526
527 /// ECC computation logic enable bit
528 pub mod ECCEN {
529 /// Offset (6 bits)
530 pub const offset: u32 = 6;
531 /// Mask (1 bit: 1 << 6)
532 pub const mask: u32 = 1 << offset;
533 /// Read-only values (empty)
534 pub mod R {}
535 /// Write-only values (empty)
536 pub mod W {}
537 /// Read-write values (empty)
538 pub mod RW {}
539 }
540
541 /// CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space.
542 pub mod TCLR {
543 /// Offset (9 bits)
544 pub const offset: u32 = 9;
545 /// Mask (4 bits: 0b1111 << 9)
546 pub const mask: u32 = 0b1111 << offset;
547 /// Read-only values (empty)
548 pub mod R {}
549 /// Write-only values (empty)
550 pub mod W {}
551 /// Read-write values (empty)
552 pub mod RW {}
553 }
554
555 /// ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space.
556 pub mod TAR {
557 /// Offset (13 bits)
558 pub const offset: u32 = 13;
559 /// Mask (4 bits: 0b1111 << 13)
560 pub const mask: u32 = 0b1111 << offset;
561 /// Read-only values (empty)
562 pub mod R {}
563 /// Write-only values (empty)
564 pub mod W {}
565 /// Read-write values (empty)
566 pub mod RW {}
567 }
568
569 /// ECC page size. These bits define the page size for the extended ECC:
570 pub mod ECCPS {
571 /// Offset (17 bits)
572 pub const offset: u32 = 17;
573 /// Mask (3 bits: 0b111 << 17)
574 pub const mask: u32 = 0b111 << offset;
575 /// Read-only values (empty)
576 pub mod R {}
577 /// Write-only values (empty)
578 pub mod W {}
579 /// Read-write values (empty)
580 pub mod RW {}
581 }
582}
583
584/// This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.
585pub mod SR {
586
587 /// Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set.
588 pub mod IRS {
589 /// Offset (0 bits)
590 pub const offset: u32 = 0;
591 /// Mask (1 bit: 1 << 0)
592 pub const mask: u32 = 1 << offset;
593 /// Read-only values (empty)
594 pub mod R {}
595 /// Write-only values (empty)
596 pub mod W {}
597 /// Read-write values (empty)
598 pub mod RW {}
599 }
600
601 /// Interrupt high-level status The flag is set by hardware and reset by software.
602 pub mod ILS {
603 /// Offset (1 bits)
604 pub const offset: u32 = 1;
605 /// Mask (1 bit: 1 << 1)
606 pub const mask: u32 = 1 << offset;
607 /// Read-only values (empty)
608 pub mod R {}
609 /// Write-only values (empty)
610 pub mod W {}
611 /// Read-write values (empty)
612 pub mod RW {}
613 }
614
615 /// Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set.
616 pub mod IFS {
617 /// Offset (2 bits)
618 pub const offset: u32 = 2;
619 /// Mask (1 bit: 1 << 2)
620 pub const mask: u32 = 1 << offset;
621 /// Read-only values (empty)
622 pub mod R {}
623 /// Write-only values (empty)
624 pub mod W {}
625 /// Read-write values (empty)
626 pub mod RW {}
627 }
628
629 /// Interrupt rising edge detection enable bit
630 pub mod IREN {
631 /// Offset (3 bits)
632 pub const offset: u32 = 3;
633 /// Mask (1 bit: 1 << 3)
634 pub const mask: u32 = 1 << offset;
635 /// Read-only values (empty)
636 pub mod R {}
637 /// Write-only values (empty)
638 pub mod W {}
639 /// Read-write values (empty)
640 pub mod RW {}
641 }
642
643 /// Interrupt high-level detection enable bit
644 pub mod ILEN {
645 /// Offset (4 bits)
646 pub const offset: u32 = 4;
647 /// Mask (1 bit: 1 << 4)
648 pub const mask: u32 = 1 << offset;
649 /// Read-only values (empty)
650 pub mod R {}
651 /// Write-only values (empty)
652 pub mod W {}
653 /// Read-write values (empty)
654 pub mod RW {}
655 }
656
657 /// Interrupt falling edge detection enable bit
658 pub mod IFEN {
659 /// Offset (5 bits)
660 pub const offset: u32 = 5;
661 /// Mask (1 bit: 1 << 5)
662 pub const mask: u32 = 1 << offset;
663 /// Read-only values (empty)
664 pub mod R {}
665 /// Write-only values (empty)
666 pub mod W {}
667 /// Read-write values (empty)
668 pub mod RW {}
669 }
670
671 /// FIFO empty. Read-only bit that provides the status of the FIFO
672 pub mod FEMPT {
673 /// Offset (6 bits)
674 pub const offset: u32 = 6;
675 /// Mask (1 bit: 1 << 6)
676 pub const mask: u32 = 1 << offset;
677 /// Read-only values (empty)
678 pub mod R {}
679 /// Write-only values (empty)
680 pub mod W {}
681 /// Read-write values (empty)
682 pub mod RW {}
683 }
684}
685
686/// The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.
687pub mod PMEM {
688
689 /// Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space:
690 pub mod MEMSET {
691 /// Offset (0 bits)
692 pub const offset: u32 = 0;
693 /// Mask (8 bits: 0xff << 0)
694 pub const mask: u32 = 0xff << offset;
695 /// Read-only values (empty)
696 pub mod R {}
697 /// Write-only values (empty)
698 pub mod W {}
699 /// Read-write values (empty)
700 pub mod RW {}
701 }
702
703 /// Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:
704 pub mod MEMWAIT {
705 /// Offset (8 bits)
706 pub const offset: u32 = 8;
707 /// Mask (8 bits: 0xff << 8)
708 pub const mask: u32 = 0xff << offset;
709 /// Read-only values (empty)
710 pub mod R {}
711 /// Write-only values (empty)
712 pub mod W {}
713 /// Read-write values (empty)
714 pub mod RW {}
715 }
716
717 /// Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space:
718 pub mod MEMHOLD {
719 /// Offset (16 bits)
720 pub const offset: u32 = 16;
721 /// Mask (8 bits: 0xff << 16)
722 pub const mask: u32 = 0xff << offset;
723 /// Read-only values (empty)
724 pub mod R {}
725 /// Write-only values (empty)
726 pub mod W {}
727 /// Read-write values (empty)
728 pub mod RW {}
729 }
730
731 /// Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions:
732 pub mod MEMHIZ {
733 /// Offset (24 bits)
734 pub const offset: u32 = 24;
735 /// Mask (8 bits: 0xff << 24)
736 pub const mask: u32 = 0xff << offset;
737 /// Read-only values (empty)
738 pub mod R {}
739 /// Write-only values (empty)
740 pub mod W {}
741 /// Read-write values (empty)
742 pub mod RW {}
743 }
744}
745
746/// The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).
747pub mod PATT {
748
749 /// Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:
750 pub mod ATTSET {
751 /// Offset (0 bits)
752 pub const offset: u32 = 0;
753 /// Mask (8 bits: 0xff << 0)
754 pub const mask: u32 = 0xff << offset;
755 /// Read-only values (empty)
756 pub mod R {}
757 /// Write-only values (empty)
758 pub mod W {}
759 /// Read-write values (empty)
760 pub mod RW {}
761 }
762
763 /// Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:
764 pub mod ATTWAIT {
765 /// Offset (8 bits)
766 pub const offset: u32 = 8;
767 /// Mask (8 bits: 0xff << 8)
768 pub const mask: u32 = 0xff << offset;
769 /// Read-only values (empty)
770 pub mod R {}
771 /// Write-only values (empty)
772 pub mod W {}
773 /// Read-write values (empty)
774 pub mod RW {}
775 }
776
777 /// Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:
778 pub mod ATTHOLD {
779 /// Offset (16 bits)
780 pub const offset: u32 = 16;
781 /// Mask (8 bits: 0xff << 16)
782 pub const mask: u32 = 0xff << offset;
783 /// Read-only values (empty)
784 pub mod R {}
785 /// Write-only values (empty)
786 pub mod W {}
787 /// Read-write values (empty)
788 pub mod RW {}
789 }
790
791 /// Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:
792 pub mod ATTHIZ {
793 /// Offset (24 bits)
794 pub const offset: u32 = 24;
795 /// Mask (8 bits: 0xff << 24)
796 pub const mask: u32 = 0xff << offset;
797 /// Read-only values (empty)
798 pub mod R {}
799 /// Write-only values (empty)
800 pub mod W {}
801 /// Read-write values (empty)
802 pub mod RW {}
803 }
804}
805
806/// This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
807pub mod ECCR {
808
809 /// ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields.
810 pub mod ECC {
811 /// Offset (0 bits)
812 pub const offset: u32 = 0;
813 /// Mask (32 bits: 0xffffffff << 0)
814 pub const mask: u32 = 0xffffffff << offset;
815 /// Read-only values (empty)
816 pub mod R {}
817 /// Write-only values (empty)
818 pub mod W {}
819 /// Read-write values (empty)
820 pub mod RW {}
821 }
822}
823
824/// This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
825pub mod BWTR1 {
826
827 /// Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.
828 pub mod ADDSET {
829 /// Offset (0 bits)
830 pub const offset: u32 = 0;
831 /// Mask (4 bits: 0b1111 << 0)
832 pub const mask: u32 = 0b1111 << offset;
833 /// Read-only values (empty)
834 pub mod R {}
835 /// Write-only values (empty)
836 pub mod W {}
837 /// Read-write values (empty)
838 pub mod RW {}
839 }
840
841 /// Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
842 pub mod ADDHLD {
843 /// Offset (4 bits)
844 pub const offset: u32 = 4;
845 /// Mask (4 bits: 0b1111 << 4)
846 pub const mask: u32 = 0b1111 << offset;
847 /// Read-only values (empty)
848 pub mod R {}
849 /// Write-only values (empty)
850 pub mod W {}
851 /// Read-write values (empty)
852 pub mod RW {}
853 }
854
855 /// Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:
856 pub mod DATAST {
857 /// Offset (8 bits)
858 pub const offset: u32 = 8;
859 /// Mask (8 bits: 0xff << 8)
860 pub const mask: u32 = 0xff << offset;
861 /// Read-only values (empty)
862 pub mod R {}
863 /// Write-only values (empty)
864 pub mod W {}
865 /// Read-write values (empty)
866 pub mod RW {}
867 }
868
869 /// Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ...
870 pub mod BUSTURN {
871 /// Offset (16 bits)
872 pub const offset: u32 = 16;
873 /// Mask (4 bits: 0b1111 << 16)
874 pub const mask: u32 = 0b1111 << offset;
875 /// Read-only values (empty)
876 pub mod R {}
877 /// Write-only values (empty)
878 pub mod W {}
879 /// Read-write values (empty)
880 pub mod RW {}
881 }
882
883 /// Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
884 pub mod ACCMOD {
885 /// Offset (28 bits)
886 pub const offset: u32 = 28;
887 /// Mask (2 bits: 0b11 << 28)
888 pub const mask: u32 = 0b11 << offset;
889 /// Read-only values (empty)
890 pub mod R {}
891 /// Write-only values (empty)
892 pub mod W {}
893 /// Read-write values (empty)
894 pub mod RW {}
895 }
896}
897
898/// This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
899pub mod BWTR2 {
900 pub use super::BWTR1::ACCMOD;
901 pub use super::BWTR1::ADDHLD;
902 pub use super::BWTR1::ADDSET;
903 pub use super::BWTR1::BUSTURN;
904 pub use super::BWTR1::DATAST;
905}
906
907/// This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
908pub mod BWTR3 {
909 pub use super::BWTR1::ACCMOD;
910 pub use super::BWTR1::ADDHLD;
911 pub use super::BWTR1::ADDSET;
912 pub use super::BWTR1::BUSTURN;
913 pub use super::BWTR1::DATAST;
914}
915
916/// This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
917pub mod BWTR4 {
918 pub use super::BWTR1::ACCMOD;
919 pub use super::BWTR1::ADDHLD;
920 pub use super::BWTR1::ADDSET;
921 pub use super::BWTR1::BUSTURN;
922 pub use super::BWTR1::DATAST;
923}
924
925/// PCSCNTR
926pub mod PCSCNTR {
927
928 /// Chip select counter
929 pub mod CSCOUNT {
930 /// Offset (0 bits)
931 pub const offset: u32 = 0;
932 /// Mask (16 bits: 0xffff << 0)
933 pub const mask: u32 = 0xffff << offset;
934 /// Read-only values (empty)
935 pub mod R {}
936 /// Write-only values (empty)
937 pub mod W {}
938 /// Read-write values (empty)
939 pub mod RW {}
940 }
941
942 /// Counter Bank 1 enable
943 pub mod CNTB1EN {
944 /// Offset (16 bits)
945 pub const offset: u32 = 16;
946 /// Mask (1 bit: 1 << 16)
947 pub const mask: u32 = 1 << offset;
948 /// Read-only values (empty)
949 pub mod R {}
950 /// Write-only values (empty)
951 pub mod W {}
952 /// Read-write values (empty)
953 pub mod RW {}
954 }
955
956 /// Counter Bank 2 enable
957 pub mod CNTB2EN {
958 /// Offset (17 bits)
959 pub const offset: u32 = 17;
960 /// Mask (1 bit: 1 << 17)
961 pub const mask: u32 = 1 << offset;
962 /// Read-only values (empty)
963 pub mod R {}
964 /// Write-only values (empty)
965 pub mod W {}
966 /// Read-write values (empty)
967 pub mod RW {}
968 }
969
970 /// Counter Bank 3 enable
971 pub mod CNTB3EN {
972 /// Offset (18 bits)
973 pub const offset: u32 = 18;
974 /// Mask (1 bit: 1 << 18)
975 pub const mask: u32 = 1 << offset;
976 /// Read-only values (empty)
977 pub mod R {}
978 /// Write-only values (empty)
979 pub mod W {}
980 /// Read-write values (empty)
981 pub mod RW {}
982 }
983
984 /// Counter Bank 4 enable
985 pub mod CNTB4EN {
986 /// Offset (19 bits)
987 pub const offset: u32 = 19;
988 /// Mask (1 bit: 1 << 19)
989 pub const mask: u32 = 1 << offset;
990 /// Read-only values (empty)
991 pub mod R {}
992 /// Write-only values (empty)
993 pub mod W {}
994 /// Read-write values (empty)
995 pub mod RW {}
996 }
997}
998#[repr(C)]
999pub struct RegisterBlock {
1000 /// FMC_BCR1
1001 pub BCR1: RWRegister<u32>,
1002
1003 /// This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).
1004 pub BTR1: RWRegister<u32>,
1005
1006 /// FMC_BCR2
1007 pub BCR2: RWRegister<u32>,
1008
1009 /// FMC_BTR2
1010 pub BTR2: RWRegister<u32>,
1011
1012 /// >FMC_BCR3
1013 pub BCR3: RWRegister<u32>,
1014
1015 /// FMC_BTR3
1016 pub BTR3: RWRegister<u32>,
1017
1018 /// >FMC_BCR4
1019 pub BCR4: RWRegister<u32>,
1020
1021 /// FMC_BTR4
1022 pub BTR4: RWRegister<u32>,
1023
1024 /// PCSCNTR
1025 pub PCSCNTR: RWRegister<u32>,
1026
1027 _reserved1: [u8; 92],
1028
1029 /// NAND Flash control registers
1030 pub PCR: RWRegister<u32>,
1031
1032 /// This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.
1033 pub SR: RWRegister<u32>,
1034
1035 /// The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.
1036 pub PMEM: RWRegister<u32>,
1037
1038 /// The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).
1039 pub PATT: RWRegister<u32>,
1040
1041 _reserved2: [u8; 4],
1042
1043 /// This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
1044 pub ECCR: RORegister<u32>,
1045
1046 _reserved3: [u8; 108],
1047
1048 /// This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
1049 pub BWTR1: RWRegister<u32>,
1050
1051 _reserved4: [u8; 4],
1052
1053 /// This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
1054 pub BWTR2: RWRegister<u32>,
1055
1056 _reserved5: [u8; 4],
1057
1058 /// This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
1059 pub BWTR3: RWRegister<u32>,
1060
1061 _reserved6: [u8; 4],
1062
1063 /// This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
1064 pub BWTR4: RWRegister<u32>,
1065}
1066pub struct ResetValues {
1067 pub BCR1: u32,
1068 pub BTR1: u32,
1069 pub BCR2: u32,
1070 pub BTR2: u32,
1071 pub BCR3: u32,
1072 pub BTR3: u32,
1073 pub BCR4: u32,
1074 pub BTR4: u32,
1075 pub PCSCNTR: u32,
1076 pub PCR: u32,
1077 pub SR: u32,
1078 pub PMEM: u32,
1079 pub PATT: u32,
1080 pub ECCR: u32,
1081 pub BWTR1: u32,
1082 pub BWTR2: u32,
1083 pub BWTR3: u32,
1084 pub BWTR4: u32,
1085}
1086#[cfg(not(feature = "nosync"))]
1087pub struct Instance {
1088 pub(crate) addr: u32,
1089 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1090}
1091#[cfg(not(feature = "nosync"))]
1092impl ::core::ops::Deref for Instance {
1093 type Target = RegisterBlock;
1094 #[inline(always)]
1095 fn deref(&self) -> &RegisterBlock {
1096 unsafe { &*(self.addr as *const _) }
1097 }
1098}
1099#[cfg(feature = "rtic")]
1100unsafe impl Send for Instance {}