stm32ral/stm32f1/stm32f103/rcc.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Reset and clock control
4
5use crate::RWRegister;
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// Clock control register
10pub mod CR {
11
12 /// Internal High Speed clock enable
13 pub mod HSION {
14 /// Offset (0 bits)
15 pub const offset: u32 = 0;
16 /// Mask (1 bit: 1 << 0)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values
23 pub mod RW {
24
25 /// 0b0: Clock Off
26 pub const Off: u32 = 0b0;
27
28 /// 0b1: Clock On
29 pub const On: u32 = 0b1;
30 }
31 }
32
33 /// Internal High Speed clock ready flag
34 pub mod HSIRDY {
35 /// Offset (1 bits)
36 pub const offset: u32 = 1;
37 /// Mask (1 bit: 1 << 1)
38 pub const mask: u32 = 1 << offset;
39 /// Read-only values
40 pub mod R {
41
42 /// 0b0: Clock not ready
43 pub const NotReady: u32 = 0b0;
44
45 /// 0b1: Clock ready
46 pub const Ready: u32 = 0b1;
47 }
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53
54 /// Internal High Speed clock trimming
55 pub mod HSITRIM {
56 /// Offset (3 bits)
57 pub const offset: u32 = 3;
58 /// Mask (5 bits: 0b11111 << 3)
59 pub const mask: u32 = 0b11111 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// Internal High Speed clock Calibration
69 pub mod HSICAL {
70 /// Offset (8 bits)
71 pub const offset: u32 = 8;
72 /// Mask (8 bits: 0xff << 8)
73 pub const mask: u32 = 0xff << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// External High Speed clock enable
83 pub mod HSEON {
84 /// Offset (16 bits)
85 pub const offset: u32 = 16;
86 /// Mask (1 bit: 1 << 16)
87 pub const mask: u32 = 1 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 pub use super::HSION::RW;
93 }
94
95 /// External High Speed clock ready flag
96 pub mod HSERDY {
97 /// Offset (17 bits)
98 pub const offset: u32 = 17;
99 /// Mask (1 bit: 1 << 17)
100 pub const mask: u32 = 1 << offset;
101 pub use super::HSIRDY::R;
102 /// Write-only values (empty)
103 pub mod W {}
104 /// Read-write values (empty)
105 pub mod RW {}
106 }
107
108 /// External High Speed clock Bypass
109 pub mod HSEBYP {
110 /// Offset (18 bits)
111 pub const offset: u32 = 18;
112 /// Mask (1 bit: 1 << 18)
113 pub const mask: u32 = 1 << offset;
114 /// Read-only values (empty)
115 pub mod R {}
116 /// Write-only values (empty)
117 pub mod W {}
118 /// Read-write values
119 pub mod RW {
120
121 /// 0b0: HSE crystal oscillator not bypassed
122 pub const NotBypassed: u32 = 0b0;
123
124 /// 0b1: HSE crystal oscillator bypassed with external clock
125 pub const Bypassed: u32 = 0b1;
126 }
127 }
128
129 /// Clock Security System enable
130 pub mod CSSON {
131 /// Offset (19 bits)
132 pub const offset: u32 = 19;
133 /// Mask (1 bit: 1 << 19)
134 pub const mask: u32 = 1 << offset;
135 /// Read-only values (empty)
136 pub mod R {}
137 /// Write-only values (empty)
138 pub mod W {}
139 /// Read-write values
140 pub mod RW {
141
142 /// 0b0: Clock security system disabled (clock detector OFF)
143 pub const Off: u32 = 0b0;
144
145 /// 0b1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
146 pub const On: u32 = 0b1;
147 }
148 }
149
150 /// PLL enable
151 pub mod PLLON {
152 /// Offset (24 bits)
153 pub const offset: u32 = 24;
154 /// Mask (1 bit: 1 << 24)
155 pub const mask: u32 = 1 << offset;
156 /// Read-only values (empty)
157 pub mod R {}
158 /// Write-only values (empty)
159 pub mod W {}
160 pub use super::HSION::RW;
161 }
162
163 /// PLL clock ready flag
164 pub mod PLLRDY {
165 /// Offset (25 bits)
166 pub const offset: u32 = 25;
167 /// Mask (1 bit: 1 << 25)
168 pub const mask: u32 = 1 << offset;
169 pub use super::HSIRDY::R;
170 /// Write-only values (empty)
171 pub mod W {}
172 /// Read-write values (empty)
173 pub mod RW {}
174 }
175}
176
177/// Clock configuration register (RCC_CFGR)
178pub mod CFGR {
179
180 /// System clock Switch
181 pub mod SW {
182 /// Offset (0 bits)
183 pub const offset: u32 = 0;
184 /// Mask (2 bits: 0b11 << 0)
185 pub const mask: u32 = 0b11 << offset;
186 /// Read-only values (empty)
187 pub mod R {}
188 /// Write-only values (empty)
189 pub mod W {}
190 /// Read-write values
191 pub mod RW {
192
193 /// 0b00: HSI selected as system clock
194 pub const HSI: u32 = 0b00;
195
196 /// 0b01: HSE selected as system clock
197 pub const HSE: u32 = 0b01;
198
199 /// 0b10: PLL selected as system clock
200 pub const PLL: u32 = 0b10;
201 }
202 }
203
204 /// System Clock Switch Status
205 pub mod SWS {
206 /// Offset (2 bits)
207 pub const offset: u32 = 2;
208 /// Mask (2 bits: 0b11 << 2)
209 pub const mask: u32 = 0b11 << offset;
210 /// Read-only values
211 pub mod R {
212
213 /// 0b00: HSI oscillator used as system clock
214 pub const HSI: u32 = 0b00;
215
216 /// 0b01: HSE oscillator used as system clock
217 pub const HSE: u32 = 0b01;
218
219 /// 0b10: PLL used as system clock
220 pub const PLL: u32 = 0b10;
221 }
222 /// Write-only values (empty)
223 pub mod W {}
224 /// Read-write values (empty)
225 pub mod RW {}
226 }
227
228 /// AHB prescaler
229 pub mod HPRE {
230 /// Offset (4 bits)
231 pub const offset: u32 = 4;
232 /// Mask (4 bits: 0b1111 << 4)
233 pub const mask: u32 = 0b1111 << offset;
234 /// Read-only values (empty)
235 pub mod R {}
236 /// Write-only values (empty)
237 pub mod W {}
238 /// Read-write values
239 pub mod RW {
240
241 /// 0b0000: SYSCLK not divided
242 pub const Div1: u32 = 0b0000;
243
244 /// 0b1000: SYSCLK divided by 2
245 pub const Div2: u32 = 0b1000;
246
247 /// 0b1001: SYSCLK divided by 4
248 pub const Div4: u32 = 0b1001;
249
250 /// 0b1010: SYSCLK divided by 8
251 pub const Div8: u32 = 0b1010;
252
253 /// 0b1011: SYSCLK divided by 16
254 pub const Div16: u32 = 0b1011;
255
256 /// 0b1100: SYSCLK divided by 64
257 pub const Div64: u32 = 0b1100;
258
259 /// 0b1101: SYSCLK divided by 128
260 pub const Div128: u32 = 0b1101;
261
262 /// 0b1110: SYSCLK divided by 256
263 pub const Div256: u32 = 0b1110;
264
265 /// 0b1111: SYSCLK divided by 512
266 pub const Div512: u32 = 0b1111;
267 }
268 }
269
270 /// APB Low speed prescaler (APB1)
271 pub mod PPRE1 {
272 /// Offset (8 bits)
273 pub const offset: u32 = 8;
274 /// Mask (3 bits: 0b111 << 8)
275 pub const mask: u32 = 0b111 << offset;
276 /// Read-only values (empty)
277 pub mod R {}
278 /// Write-only values (empty)
279 pub mod W {}
280 /// Read-write values
281 pub mod RW {
282
283 /// 0b000: HCLK not divided
284 pub const Div1: u32 = 0b000;
285
286 /// 0b100: HCLK divided by 2
287 pub const Div2: u32 = 0b100;
288
289 /// 0b101: HCLK divided by 4
290 pub const Div4: u32 = 0b101;
291
292 /// 0b110: HCLK divided by 8
293 pub const Div8: u32 = 0b110;
294
295 /// 0b111: HCLK divided by 16
296 pub const Div16: u32 = 0b111;
297 }
298 }
299
300 /// APB High speed prescaler (APB2)
301 pub mod PPRE2 {
302 /// Offset (11 bits)
303 pub const offset: u32 = 11;
304 /// Mask (3 bits: 0b111 << 11)
305 pub const mask: u32 = 0b111 << offset;
306 /// Read-only values (empty)
307 pub mod R {}
308 /// Write-only values (empty)
309 pub mod W {}
310 pub use super::PPRE1::RW;
311 }
312
313 /// ADC prescaler
314 pub mod ADCPRE {
315 /// Offset (14 bits)
316 pub const offset: u32 = 14;
317 /// Mask (2 bits: 0b11 << 14)
318 pub const mask: u32 = 0b11 << offset;
319 /// Read-only values (empty)
320 pub mod R {}
321 /// Write-only values (empty)
322 pub mod W {}
323 /// Read-write values
324 pub mod RW {
325
326 /// 0b00: PCLK2 divided by 2
327 pub const Div2: u32 = 0b00;
328
329 /// 0b01: PCLK2 divided by 4
330 pub const Div4: u32 = 0b01;
331
332 /// 0b10: PCLK2 divided by 8
333 pub const Div6: u32 = 0b10;
334
335 /// 0b11: PCLK2 divided by 16
336 pub const Div8: u32 = 0b11;
337 }
338 }
339
340 /// PLL entry clock source
341 pub mod PLLSRC {
342 /// Offset (16 bits)
343 pub const offset: u32 = 16;
344 /// Mask (1 bit: 1 << 16)
345 pub const mask: u32 = 1 << offset;
346 /// Read-only values (empty)
347 pub mod R {}
348 /// Write-only values (empty)
349 pub mod W {}
350 /// Read-write values
351 pub mod RW {
352
353 /// 0b0: HSI divided by 2 selected as PLL input clock
354 pub const HSI_Div2: u32 = 0b0;
355
356 /// 0b1: HSE divided by PREDIV selected as PLL input clock
357 pub const HSE_Div_PREDIV: u32 = 0b1;
358 }
359 }
360
361 /// HSE divider for PLL entry
362 pub mod PLLXTPRE {
363 /// Offset (17 bits)
364 pub const offset: u32 = 17;
365 /// Mask (1 bit: 1 << 17)
366 pub const mask: u32 = 1 << offset;
367 /// Read-only values (empty)
368 pub mod R {}
369 /// Write-only values (empty)
370 pub mod W {}
371 /// Read-write values
372 pub mod RW {
373
374 /// 0b0: HSE clock not divided
375 pub const Div1: u32 = 0b0;
376
377 /// 0b1: HSE clock divided by 2
378 pub const Div2: u32 = 0b1;
379 }
380 }
381
382 /// PLL Multiplication Factor
383 pub mod PLLMUL {
384 /// Offset (18 bits)
385 pub const offset: u32 = 18;
386 /// Mask (4 bits: 0b1111 << 18)
387 pub const mask: u32 = 0b1111 << offset;
388 /// Read-only values (empty)
389 pub mod R {}
390 /// Write-only values (empty)
391 pub mod W {}
392 /// Read-write values
393 pub mod RW {
394
395 /// 0b0000: PLL input clock x2
396 pub const Mul2: u32 = 0b0000;
397
398 /// 0b0001: PLL input clock x3
399 pub const Mul3: u32 = 0b0001;
400
401 /// 0b0010: PLL input clock x4
402 pub const Mul4: u32 = 0b0010;
403
404 /// 0b0011: PLL input clock x5
405 pub const Mul5: u32 = 0b0011;
406
407 /// 0b0100: PLL input clock x6
408 pub const Mul6: u32 = 0b0100;
409
410 /// 0b0101: PLL input clock x7
411 pub const Mul7: u32 = 0b0101;
412
413 /// 0b0110: PLL input clock x8
414 pub const Mul8: u32 = 0b0110;
415
416 /// 0b0111: PLL input clock x9
417 pub const Mul9: u32 = 0b0111;
418
419 /// 0b1000: PLL input clock x10
420 pub const Mul10: u32 = 0b1000;
421
422 /// 0b1001: PLL input clock x11
423 pub const Mul11: u32 = 0b1001;
424
425 /// 0b1010: PLL input clock x12
426 pub const Mul12: u32 = 0b1010;
427
428 /// 0b1011: PLL input clock x13
429 pub const Mul13: u32 = 0b1011;
430
431 /// 0b1100: PLL input clock x14
432 pub const Mul14: u32 = 0b1100;
433
434 /// 0b1101: PLL input clock x15
435 pub const Mul15: u32 = 0b1101;
436
437 /// 0b1110: PLL input clock x16
438 pub const Mul16: u32 = 0b1110;
439
440 /// 0b1111: PLL input clock x16
441 pub const Mul16x: u32 = 0b1111;
442 }
443 }
444
445 /// USB prescaler
446 pub mod USBPRE {
447 /// Offset (22 bits)
448 pub const offset: u32 = 22;
449 /// Mask (1 bit: 1 << 22)
450 pub const mask: u32 = 1 << offset;
451 /// Read-only values (empty)
452 pub mod R {}
453 /// Write-only values (empty)
454 pub mod W {}
455 /// Read-write values
456 pub mod RW {
457
458 /// 0b0: PLL clock is divided by 1.5
459 pub const DIV1_5: u32 = 0b0;
460
461 /// 0b1: PLL clock is not divided
462 pub const DIV1: u32 = 0b1;
463 }
464 }
465
466 /// Microcontroller clock output
467 pub mod MCO {
468 /// Offset (24 bits)
469 pub const offset: u32 = 24;
470 /// Mask (3 bits: 0b111 << 24)
471 pub const mask: u32 = 0b111 << offset;
472 /// Read-only values (empty)
473 pub mod R {}
474 /// Write-only values (empty)
475 pub mod W {}
476 /// Read-write values
477 pub mod RW {
478
479 /// 0b000: MCO output disabled, no clock on MCO
480 pub const NoMCO: u32 = 0b000;
481
482 /// 0b100: System clock selected
483 pub const SYSCLK: u32 = 0b100;
484
485 /// 0b101: HSI oscillator clock selected
486 pub const HSI: u32 = 0b101;
487
488 /// 0b110: HSE oscillator clock selected
489 pub const HSE: u32 = 0b110;
490
491 /// 0b111: PLL clock selected (divided by 1 or 2, depending en PLLNODIV)
492 pub const PLL: u32 = 0b111;
493 }
494 }
495}
496
497/// Clock interrupt register (RCC_CIR)
498pub mod CIR {
499
500 /// LSI Ready Interrupt flag
501 pub mod LSIRDYF {
502 /// Offset (0 bits)
503 pub const offset: u32 = 0;
504 /// Mask (1 bit: 1 << 0)
505 pub const mask: u32 = 1 << offset;
506 /// Read-only values
507 pub mod R {
508
509 /// 0b0: No clock ready interrupt
510 pub const NotInterrupted: u32 = 0b0;
511
512 /// 0b1: Clock ready interrupt
513 pub const Interrupted: u32 = 0b1;
514 }
515 /// Write-only values (empty)
516 pub mod W {}
517 /// Read-write values (empty)
518 pub mod RW {}
519 }
520
521 /// LSE Ready Interrupt flag
522 pub mod LSERDYF {
523 /// Offset (1 bits)
524 pub const offset: u32 = 1;
525 /// Mask (1 bit: 1 << 1)
526 pub const mask: u32 = 1 << offset;
527 pub use super::LSIRDYF::R;
528 /// Write-only values (empty)
529 pub mod W {}
530 /// Read-write values (empty)
531 pub mod RW {}
532 }
533
534 /// HSI Ready Interrupt flag
535 pub mod HSIRDYF {
536 /// Offset (2 bits)
537 pub const offset: u32 = 2;
538 /// Mask (1 bit: 1 << 2)
539 pub const mask: u32 = 1 << offset;
540 pub use super::LSIRDYF::R;
541 /// Write-only values (empty)
542 pub mod W {}
543 /// Read-write values (empty)
544 pub mod RW {}
545 }
546
547 /// HSE Ready Interrupt flag
548 pub mod HSERDYF {
549 /// Offset (3 bits)
550 pub const offset: u32 = 3;
551 /// Mask (1 bit: 1 << 3)
552 pub const mask: u32 = 1 << offset;
553 pub use super::LSIRDYF::R;
554 /// Write-only values (empty)
555 pub mod W {}
556 /// Read-write values (empty)
557 pub mod RW {}
558 }
559
560 /// PLL Ready Interrupt flag
561 pub mod PLLRDYF {
562 /// Offset (4 bits)
563 pub const offset: u32 = 4;
564 /// Mask (1 bit: 1 << 4)
565 pub const mask: u32 = 1 << offset;
566 pub use super::LSIRDYF::R;
567 /// Write-only values (empty)
568 pub mod W {}
569 /// Read-write values (empty)
570 pub mod RW {}
571 }
572
573 /// Clock Security System Interrupt flag
574 pub mod CSSF {
575 /// Offset (7 bits)
576 pub const offset: u32 = 7;
577 /// Mask (1 bit: 1 << 7)
578 pub const mask: u32 = 1 << offset;
579 /// Read-only values
580 pub mod R {
581
582 /// 0b0: No clock security interrupt caused by HSE clock failure
583 pub const NotInterrupted: u32 = 0b0;
584
585 /// 0b1: Clock security interrupt caused by HSE clock failure
586 pub const Interrupted: u32 = 0b1;
587 }
588 /// Write-only values (empty)
589 pub mod W {}
590 /// Read-write values (empty)
591 pub mod RW {}
592 }
593
594 /// LSI Ready Interrupt Enable
595 pub mod LSIRDYIE {
596 /// Offset (8 bits)
597 pub const offset: u32 = 8;
598 /// Mask (1 bit: 1 << 8)
599 pub const mask: u32 = 1 << offset;
600 /// Read-only values (empty)
601 pub mod R {}
602 /// Write-only values (empty)
603 pub mod W {}
604 /// Read-write values
605 pub mod RW {
606
607 /// 0b0: Interrupt disabled
608 pub const Disabled: u32 = 0b0;
609
610 /// 0b1: Interrupt enabled
611 pub const Enabled: u32 = 0b1;
612 }
613 }
614
615 /// LSE Ready Interrupt Enable
616 pub mod LSERDYIE {
617 /// Offset (9 bits)
618 pub const offset: u32 = 9;
619 /// Mask (1 bit: 1 << 9)
620 pub const mask: u32 = 1 << offset;
621 /// Read-only values (empty)
622 pub mod R {}
623 /// Write-only values (empty)
624 pub mod W {}
625 pub use super::LSIRDYIE::RW;
626 }
627
628 /// HSI Ready Interrupt Enable
629 pub mod HSIRDYIE {
630 /// Offset (10 bits)
631 pub const offset: u32 = 10;
632 /// Mask (1 bit: 1 << 10)
633 pub const mask: u32 = 1 << offset;
634 /// Read-only values (empty)
635 pub mod R {}
636 /// Write-only values (empty)
637 pub mod W {}
638 pub use super::LSIRDYIE::RW;
639 }
640
641 /// HSE Ready Interrupt Enable
642 pub mod HSERDYIE {
643 /// Offset (11 bits)
644 pub const offset: u32 = 11;
645 /// Mask (1 bit: 1 << 11)
646 pub const mask: u32 = 1 << offset;
647 /// Read-only values (empty)
648 pub mod R {}
649 /// Write-only values (empty)
650 pub mod W {}
651 pub use super::LSIRDYIE::RW;
652 }
653
654 /// PLL Ready Interrupt Enable
655 pub mod PLLRDYIE {
656 /// Offset (12 bits)
657 pub const offset: u32 = 12;
658 /// Mask (1 bit: 1 << 12)
659 pub const mask: u32 = 1 << offset;
660 /// Read-only values (empty)
661 pub mod R {}
662 /// Write-only values (empty)
663 pub mod W {}
664 pub use super::LSIRDYIE::RW;
665 }
666
667 /// LSI Ready Interrupt Clear
668 pub mod LSIRDYC {
669 /// Offset (16 bits)
670 pub const offset: u32 = 16;
671 /// Mask (1 bit: 1 << 16)
672 pub const mask: u32 = 1 << offset;
673 /// Read-only values (empty)
674 pub mod R {}
675 /// Write-only values
676 pub mod W {
677
678 /// 0b1: Clear interrupt flag
679 pub const Clear: u32 = 0b1;
680 }
681 /// Read-write values (empty)
682 pub mod RW {}
683 }
684
685 /// LSE Ready Interrupt Clear
686 pub mod LSERDYC {
687 /// Offset (17 bits)
688 pub const offset: u32 = 17;
689 /// Mask (1 bit: 1 << 17)
690 pub const mask: u32 = 1 << offset;
691 /// Read-only values (empty)
692 pub mod R {}
693 pub use super::LSIRDYC::W;
694 /// Read-write values (empty)
695 pub mod RW {}
696 }
697
698 /// HSI Ready Interrupt Clear
699 pub mod HSIRDYC {
700 /// Offset (18 bits)
701 pub const offset: u32 = 18;
702 /// Mask (1 bit: 1 << 18)
703 pub const mask: u32 = 1 << offset;
704 /// Read-only values (empty)
705 pub mod R {}
706 pub use super::LSIRDYC::W;
707 /// Read-write values (empty)
708 pub mod RW {}
709 }
710
711 /// HSE Ready Interrupt Clear
712 pub mod HSERDYC {
713 /// Offset (19 bits)
714 pub const offset: u32 = 19;
715 /// Mask (1 bit: 1 << 19)
716 pub const mask: u32 = 1 << offset;
717 /// Read-only values (empty)
718 pub mod R {}
719 pub use super::LSIRDYC::W;
720 /// Read-write values (empty)
721 pub mod RW {}
722 }
723
724 /// PLL Ready Interrupt Clear
725 pub mod PLLRDYC {
726 /// Offset (20 bits)
727 pub const offset: u32 = 20;
728 /// Mask (1 bit: 1 << 20)
729 pub const mask: u32 = 1 << offset;
730 /// Read-only values (empty)
731 pub mod R {}
732 pub use super::LSIRDYC::W;
733 /// Read-write values (empty)
734 pub mod RW {}
735 }
736
737 /// Clock security system interrupt clear
738 pub mod CSSC {
739 /// Offset (23 bits)
740 pub const offset: u32 = 23;
741 /// Mask (1 bit: 1 << 23)
742 pub const mask: u32 = 1 << offset;
743 /// Read-only values (empty)
744 pub mod R {}
745 /// Write-only values
746 pub mod W {
747
748 /// 0b1: Clear CSSF flag
749 pub const Clear: u32 = 0b1;
750 }
751 /// Read-write values (empty)
752 pub mod RW {}
753 }
754}
755
756/// APB2 peripheral reset register (RCC_APB2RSTR)
757pub mod APB2RSTR {
758
759 /// Alternate function I/O reset
760 pub mod AFIORST {
761 /// Offset (0 bits)
762 pub const offset: u32 = 0;
763 /// Mask (1 bit: 1 << 0)
764 pub const mask: u32 = 1 << offset;
765 /// Read-only values (empty)
766 pub mod R {}
767 /// Write-only values (empty)
768 pub mod W {}
769 /// Read-write values
770 pub mod RW {
771
772 /// 0b1: Reset the selected module
773 pub const Reset: u32 = 0b1;
774 }
775 }
776
777 /// IO port A reset
778 pub mod IOPARST {
779 /// Offset (2 bits)
780 pub const offset: u32 = 2;
781 /// Mask (1 bit: 1 << 2)
782 pub const mask: u32 = 1 << offset;
783 /// Read-only values (empty)
784 pub mod R {}
785 /// Write-only values (empty)
786 pub mod W {}
787 pub use super::AFIORST::RW;
788 }
789
790 /// IO port B reset
791 pub mod IOPBRST {
792 /// Offset (3 bits)
793 pub const offset: u32 = 3;
794 /// Mask (1 bit: 1 << 3)
795 pub const mask: u32 = 1 << offset;
796 /// Read-only values (empty)
797 pub mod R {}
798 /// Write-only values (empty)
799 pub mod W {}
800 pub use super::AFIORST::RW;
801 }
802
803 /// IO port C reset
804 pub mod IOPCRST {
805 /// Offset (4 bits)
806 pub const offset: u32 = 4;
807 /// Mask (1 bit: 1 << 4)
808 pub const mask: u32 = 1 << offset;
809 /// Read-only values (empty)
810 pub mod R {}
811 /// Write-only values (empty)
812 pub mod W {}
813 pub use super::AFIORST::RW;
814 }
815
816 /// IO port D reset
817 pub mod IOPDRST {
818 /// Offset (5 bits)
819 pub const offset: u32 = 5;
820 /// Mask (1 bit: 1 << 5)
821 pub const mask: u32 = 1 << offset;
822 /// Read-only values (empty)
823 pub mod R {}
824 /// Write-only values (empty)
825 pub mod W {}
826 pub use super::AFIORST::RW;
827 }
828
829 /// IO port E reset
830 pub mod IOPERST {
831 /// Offset (6 bits)
832 pub const offset: u32 = 6;
833 /// Mask (1 bit: 1 << 6)
834 pub const mask: u32 = 1 << offset;
835 /// Read-only values (empty)
836 pub mod R {}
837 /// Write-only values (empty)
838 pub mod W {}
839 pub use super::AFIORST::RW;
840 }
841
842 /// IO port F reset
843 pub mod IOPFRST {
844 /// Offset (7 bits)
845 pub const offset: u32 = 7;
846 /// Mask (1 bit: 1 << 7)
847 pub const mask: u32 = 1 << offset;
848 /// Read-only values (empty)
849 pub mod R {}
850 /// Write-only values (empty)
851 pub mod W {}
852 pub use super::AFIORST::RW;
853 }
854
855 /// IO port G reset
856 pub mod IOPGRST {
857 /// Offset (8 bits)
858 pub const offset: u32 = 8;
859 /// Mask (1 bit: 1 << 8)
860 pub const mask: u32 = 1 << offset;
861 /// Read-only values (empty)
862 pub mod R {}
863 /// Write-only values (empty)
864 pub mod W {}
865 pub use super::AFIORST::RW;
866 }
867
868 /// ADC 1 interface reset
869 pub mod ADC1RST {
870 /// Offset (9 bits)
871 pub const offset: u32 = 9;
872 /// Mask (1 bit: 1 << 9)
873 pub const mask: u32 = 1 << offset;
874 /// Read-only values (empty)
875 pub mod R {}
876 /// Write-only values (empty)
877 pub mod W {}
878 pub use super::AFIORST::RW;
879 }
880
881 /// ADC 2 interface reset
882 pub mod ADC2RST {
883 /// Offset (10 bits)
884 pub const offset: u32 = 10;
885 /// Mask (1 bit: 1 << 10)
886 pub const mask: u32 = 1 << offset;
887 /// Read-only values (empty)
888 pub mod R {}
889 /// Write-only values (empty)
890 pub mod W {}
891 pub use super::AFIORST::RW;
892 }
893
894 /// TIM1 timer reset
895 pub mod TIM1RST {
896 /// Offset (11 bits)
897 pub const offset: u32 = 11;
898 /// Mask (1 bit: 1 << 11)
899 pub const mask: u32 = 1 << offset;
900 /// Read-only values (empty)
901 pub mod R {}
902 /// Write-only values (empty)
903 pub mod W {}
904 pub use super::AFIORST::RW;
905 }
906
907 /// SPI 1 reset
908 pub mod SPI1RST {
909 /// Offset (12 bits)
910 pub const offset: u32 = 12;
911 /// Mask (1 bit: 1 << 12)
912 pub const mask: u32 = 1 << offset;
913 /// Read-only values (empty)
914 pub mod R {}
915 /// Write-only values (empty)
916 pub mod W {}
917 pub use super::AFIORST::RW;
918 }
919
920 /// TIM8 timer reset
921 pub mod TIM8RST {
922 /// Offset (13 bits)
923 pub const offset: u32 = 13;
924 /// Mask (1 bit: 1 << 13)
925 pub const mask: u32 = 1 << offset;
926 /// Read-only values (empty)
927 pub mod R {}
928 /// Write-only values (empty)
929 pub mod W {}
930 pub use super::AFIORST::RW;
931 }
932
933 /// USART1 reset
934 pub mod USART1RST {
935 /// Offset (14 bits)
936 pub const offset: u32 = 14;
937 /// Mask (1 bit: 1 << 14)
938 pub const mask: u32 = 1 << offset;
939 /// Read-only values (empty)
940 pub mod R {}
941 /// Write-only values (empty)
942 pub mod W {}
943 pub use super::AFIORST::RW;
944 }
945
946 /// ADC 3 interface reset
947 pub mod ADC3RST {
948 /// Offset (15 bits)
949 pub const offset: u32 = 15;
950 /// Mask (1 bit: 1 << 15)
951 pub const mask: u32 = 1 << offset;
952 /// Read-only values (empty)
953 pub mod R {}
954 /// Write-only values (empty)
955 pub mod W {}
956 pub use super::AFIORST::RW;
957 }
958
959 /// TIM9 timer reset
960 pub mod TIM9RST {
961 /// Offset (19 bits)
962 pub const offset: u32 = 19;
963 /// Mask (1 bit: 1 << 19)
964 pub const mask: u32 = 1 << offset;
965 /// Read-only values (empty)
966 pub mod R {}
967 /// Write-only values (empty)
968 pub mod W {}
969 pub use super::AFIORST::RW;
970 }
971
972 /// TIM10 timer reset
973 pub mod TIM10RST {
974 /// Offset (20 bits)
975 pub const offset: u32 = 20;
976 /// Mask (1 bit: 1 << 20)
977 pub const mask: u32 = 1 << offset;
978 /// Read-only values (empty)
979 pub mod R {}
980 /// Write-only values (empty)
981 pub mod W {}
982 pub use super::AFIORST::RW;
983 }
984
985 /// TIM11 timer reset
986 pub mod TIM11RST {
987 /// Offset (21 bits)
988 pub const offset: u32 = 21;
989 /// Mask (1 bit: 1 << 21)
990 pub const mask: u32 = 1 << offset;
991 /// Read-only values (empty)
992 pub mod R {}
993 /// Write-only values (empty)
994 pub mod W {}
995 pub use super::AFIORST::RW;
996 }
997}
998
999/// APB1 peripheral reset register (RCC_APB1RSTR)
1000pub mod APB1RSTR {
1001
1002 /// Timer 2 reset
1003 pub mod TIM2RST {
1004 /// Offset (0 bits)
1005 pub const offset: u32 = 0;
1006 /// Mask (1 bit: 1 << 0)
1007 pub const mask: u32 = 1 << offset;
1008 /// Read-only values (empty)
1009 pub mod R {}
1010 /// Write-only values (empty)
1011 pub mod W {}
1012 /// Read-write values
1013 pub mod RW {
1014
1015 /// 0b1: Reset the selected module
1016 pub const Reset: u32 = 0b1;
1017 }
1018 }
1019
1020 /// Timer 3 reset
1021 pub mod TIM3RST {
1022 /// Offset (1 bits)
1023 pub const offset: u32 = 1;
1024 /// Mask (1 bit: 1 << 1)
1025 pub const mask: u32 = 1 << offset;
1026 /// Read-only values (empty)
1027 pub mod R {}
1028 /// Write-only values (empty)
1029 pub mod W {}
1030 pub use super::TIM2RST::RW;
1031 }
1032
1033 /// Timer 4 reset
1034 pub mod TIM4RST {
1035 /// Offset (2 bits)
1036 pub const offset: u32 = 2;
1037 /// Mask (1 bit: 1 << 2)
1038 pub const mask: u32 = 1 << offset;
1039 /// Read-only values (empty)
1040 pub mod R {}
1041 /// Write-only values (empty)
1042 pub mod W {}
1043 pub use super::TIM2RST::RW;
1044 }
1045
1046 /// Timer 5 reset
1047 pub mod TIM5RST {
1048 /// Offset (3 bits)
1049 pub const offset: u32 = 3;
1050 /// Mask (1 bit: 1 << 3)
1051 pub const mask: u32 = 1 << offset;
1052 /// Read-only values (empty)
1053 pub mod R {}
1054 /// Write-only values (empty)
1055 pub mod W {}
1056 pub use super::TIM2RST::RW;
1057 }
1058
1059 /// Timer 6 reset
1060 pub mod TIM6RST {
1061 /// Offset (4 bits)
1062 pub const offset: u32 = 4;
1063 /// Mask (1 bit: 1 << 4)
1064 pub const mask: u32 = 1 << offset;
1065 /// Read-only values (empty)
1066 pub mod R {}
1067 /// Write-only values (empty)
1068 pub mod W {}
1069 pub use super::TIM2RST::RW;
1070 }
1071
1072 /// Timer 7 reset
1073 pub mod TIM7RST {
1074 /// Offset (5 bits)
1075 pub const offset: u32 = 5;
1076 /// Mask (1 bit: 1 << 5)
1077 pub const mask: u32 = 1 << offset;
1078 /// Read-only values (empty)
1079 pub mod R {}
1080 /// Write-only values (empty)
1081 pub mod W {}
1082 pub use super::TIM2RST::RW;
1083 }
1084
1085 /// Timer 12 reset
1086 pub mod TIM12RST {
1087 /// Offset (6 bits)
1088 pub const offset: u32 = 6;
1089 /// Mask (1 bit: 1 << 6)
1090 pub const mask: u32 = 1 << offset;
1091 /// Read-only values (empty)
1092 pub mod R {}
1093 /// Write-only values (empty)
1094 pub mod W {}
1095 pub use super::TIM2RST::RW;
1096 }
1097
1098 /// Timer 13 reset
1099 pub mod TIM13RST {
1100 /// Offset (7 bits)
1101 pub const offset: u32 = 7;
1102 /// Mask (1 bit: 1 << 7)
1103 pub const mask: u32 = 1 << offset;
1104 /// Read-only values (empty)
1105 pub mod R {}
1106 /// Write-only values (empty)
1107 pub mod W {}
1108 pub use super::TIM2RST::RW;
1109 }
1110
1111 /// Timer 14 reset
1112 pub mod TIM14RST {
1113 /// Offset (8 bits)
1114 pub const offset: u32 = 8;
1115 /// Mask (1 bit: 1 << 8)
1116 pub const mask: u32 = 1 << offset;
1117 /// Read-only values (empty)
1118 pub mod R {}
1119 /// Write-only values (empty)
1120 pub mod W {}
1121 pub use super::TIM2RST::RW;
1122 }
1123
1124 /// Window watchdog reset
1125 pub mod WWDGRST {
1126 /// Offset (11 bits)
1127 pub const offset: u32 = 11;
1128 /// Mask (1 bit: 1 << 11)
1129 pub const mask: u32 = 1 << offset;
1130 /// Read-only values (empty)
1131 pub mod R {}
1132 /// Write-only values (empty)
1133 pub mod W {}
1134 pub use super::TIM2RST::RW;
1135 }
1136
1137 /// SPI2 reset
1138 pub mod SPI2RST {
1139 /// Offset (14 bits)
1140 pub const offset: u32 = 14;
1141 /// Mask (1 bit: 1 << 14)
1142 pub const mask: u32 = 1 << offset;
1143 /// Read-only values (empty)
1144 pub mod R {}
1145 /// Write-only values (empty)
1146 pub mod W {}
1147 pub use super::TIM2RST::RW;
1148 }
1149
1150 /// SPI3 reset
1151 pub mod SPI3RST {
1152 /// Offset (15 bits)
1153 pub const offset: u32 = 15;
1154 /// Mask (1 bit: 1 << 15)
1155 pub const mask: u32 = 1 << offset;
1156 /// Read-only values (empty)
1157 pub mod R {}
1158 /// Write-only values (empty)
1159 pub mod W {}
1160 pub use super::TIM2RST::RW;
1161 }
1162
1163 /// USART 2 reset
1164 pub mod USART2RST {
1165 /// Offset (17 bits)
1166 pub const offset: u32 = 17;
1167 /// Mask (1 bit: 1 << 17)
1168 pub const mask: u32 = 1 << offset;
1169 /// Read-only values (empty)
1170 pub mod R {}
1171 /// Write-only values (empty)
1172 pub mod W {}
1173 pub use super::TIM2RST::RW;
1174 }
1175
1176 /// USART 3 reset
1177 pub mod USART3RST {
1178 /// Offset (18 bits)
1179 pub const offset: u32 = 18;
1180 /// Mask (1 bit: 1 << 18)
1181 pub const mask: u32 = 1 << offset;
1182 /// Read-only values (empty)
1183 pub mod R {}
1184 /// Write-only values (empty)
1185 pub mod W {}
1186 pub use super::TIM2RST::RW;
1187 }
1188
1189 /// UART 4 reset
1190 pub mod UART4RST {
1191 /// Offset (19 bits)
1192 pub const offset: u32 = 19;
1193 /// Mask (1 bit: 1 << 19)
1194 pub const mask: u32 = 1 << offset;
1195 /// Read-only values (empty)
1196 pub mod R {}
1197 /// Write-only values (empty)
1198 pub mod W {}
1199 pub use super::TIM2RST::RW;
1200 }
1201
1202 /// UART 5 reset
1203 pub mod UART5RST {
1204 /// Offset (20 bits)
1205 pub const offset: u32 = 20;
1206 /// Mask (1 bit: 1 << 20)
1207 pub const mask: u32 = 1 << offset;
1208 /// Read-only values (empty)
1209 pub mod R {}
1210 /// Write-only values (empty)
1211 pub mod W {}
1212 pub use super::TIM2RST::RW;
1213 }
1214
1215 /// I2C1 reset
1216 pub mod I2C1RST {
1217 /// Offset (21 bits)
1218 pub const offset: u32 = 21;
1219 /// Mask (1 bit: 1 << 21)
1220 pub const mask: u32 = 1 << offset;
1221 /// Read-only values (empty)
1222 pub mod R {}
1223 /// Write-only values (empty)
1224 pub mod W {}
1225 pub use super::TIM2RST::RW;
1226 }
1227
1228 /// I2C2 reset
1229 pub mod I2C2RST {
1230 /// Offset (22 bits)
1231 pub const offset: u32 = 22;
1232 /// Mask (1 bit: 1 << 22)
1233 pub const mask: u32 = 1 << offset;
1234 /// Read-only values (empty)
1235 pub mod R {}
1236 /// Write-only values (empty)
1237 pub mod W {}
1238 pub use super::TIM2RST::RW;
1239 }
1240
1241 /// USB reset
1242 pub mod USBRST {
1243 /// Offset (23 bits)
1244 pub const offset: u32 = 23;
1245 /// Mask (1 bit: 1 << 23)
1246 pub const mask: u32 = 1 << offset;
1247 /// Read-only values (empty)
1248 pub mod R {}
1249 /// Write-only values (empty)
1250 pub mod W {}
1251 pub use super::TIM2RST::RW;
1252 }
1253
1254 /// CAN reset
1255 pub mod CANRST {
1256 /// Offset (25 bits)
1257 pub const offset: u32 = 25;
1258 /// Mask (1 bit: 1 << 25)
1259 pub const mask: u32 = 1 << offset;
1260 /// Read-only values (empty)
1261 pub mod R {}
1262 /// Write-only values (empty)
1263 pub mod W {}
1264 pub use super::TIM2RST::RW;
1265 }
1266
1267 /// Backup interface reset
1268 pub mod BKPRST {
1269 /// Offset (27 bits)
1270 pub const offset: u32 = 27;
1271 /// Mask (1 bit: 1 << 27)
1272 pub const mask: u32 = 1 << offset;
1273 /// Read-only values (empty)
1274 pub mod R {}
1275 /// Write-only values (empty)
1276 pub mod W {}
1277 pub use super::TIM2RST::RW;
1278 }
1279
1280 /// Power interface reset
1281 pub mod PWRRST {
1282 /// Offset (28 bits)
1283 pub const offset: u32 = 28;
1284 /// Mask (1 bit: 1 << 28)
1285 pub const mask: u32 = 1 << offset;
1286 /// Read-only values (empty)
1287 pub mod R {}
1288 /// Write-only values (empty)
1289 pub mod W {}
1290 pub use super::TIM2RST::RW;
1291 }
1292
1293 /// DAC interface reset
1294 pub mod DACRST {
1295 /// Offset (29 bits)
1296 pub const offset: u32 = 29;
1297 /// Mask (1 bit: 1 << 29)
1298 pub const mask: u32 = 1 << offset;
1299 /// Read-only values (empty)
1300 pub mod R {}
1301 /// Write-only values (empty)
1302 pub mod W {}
1303 pub use super::TIM2RST::RW;
1304 }
1305}
1306
1307/// AHB Peripheral Clock enable register (RCC_AHBENR)
1308pub mod AHBENR {
1309
1310 /// DMA1 clock enable
1311 pub mod DMA1EN {
1312 /// Offset (0 bits)
1313 pub const offset: u32 = 0;
1314 /// Mask (1 bit: 1 << 0)
1315 pub const mask: u32 = 1 << offset;
1316 /// Read-only values (empty)
1317 pub mod R {}
1318 /// Write-only values (empty)
1319 pub mod W {}
1320 /// Read-write values
1321 pub mod RW {
1322
1323 /// 0b0: The selected clock is disabled
1324 pub const Disabled: u32 = 0b0;
1325
1326 /// 0b1: The selected clock is enabled
1327 pub const Enabled: u32 = 0b1;
1328 }
1329 }
1330
1331 /// DMA2 clock enable
1332 pub mod DMA2EN {
1333 /// Offset (1 bits)
1334 pub const offset: u32 = 1;
1335 /// Mask (1 bit: 1 << 1)
1336 pub const mask: u32 = 1 << offset;
1337 /// Read-only values (empty)
1338 pub mod R {}
1339 /// Write-only values (empty)
1340 pub mod W {}
1341 pub use super::DMA1EN::RW;
1342 }
1343
1344 /// SRAM interface clock enable
1345 pub mod SRAMEN {
1346 /// Offset (2 bits)
1347 pub const offset: u32 = 2;
1348 /// Mask (1 bit: 1 << 2)
1349 pub const mask: u32 = 1 << offset;
1350 /// Read-only values (empty)
1351 pub mod R {}
1352 /// Write-only values (empty)
1353 pub mod W {}
1354 pub use super::DMA1EN::RW;
1355 }
1356
1357 /// FLITF clock enable
1358 pub mod FLITFEN {
1359 /// Offset (4 bits)
1360 pub const offset: u32 = 4;
1361 /// Mask (1 bit: 1 << 4)
1362 pub const mask: u32 = 1 << offset;
1363 /// Read-only values (empty)
1364 pub mod R {}
1365 /// Write-only values (empty)
1366 pub mod W {}
1367 pub use super::DMA1EN::RW;
1368 }
1369
1370 /// CRC clock enable
1371 pub mod CRCEN {
1372 /// Offset (6 bits)
1373 pub const offset: u32 = 6;
1374 /// Mask (1 bit: 1 << 6)
1375 pub const mask: u32 = 1 << offset;
1376 /// Read-only values (empty)
1377 pub mod R {}
1378 /// Write-only values (empty)
1379 pub mod W {}
1380 pub use super::DMA1EN::RW;
1381 }
1382
1383 /// FSMC clock enable
1384 pub mod FSMCEN {
1385 /// Offset (8 bits)
1386 pub const offset: u32 = 8;
1387 /// Mask (1 bit: 1 << 8)
1388 pub const mask: u32 = 1 << offset;
1389 /// Read-only values (empty)
1390 pub mod R {}
1391 /// Write-only values (empty)
1392 pub mod W {}
1393 pub use super::DMA1EN::RW;
1394 }
1395
1396 /// SDIO clock enable
1397 pub mod SDIOEN {
1398 /// Offset (10 bits)
1399 pub const offset: u32 = 10;
1400 /// Mask (1 bit: 1 << 10)
1401 pub const mask: u32 = 1 << offset;
1402 /// Read-only values (empty)
1403 pub mod R {}
1404 /// Write-only values (empty)
1405 pub mod W {}
1406 pub use super::DMA1EN::RW;
1407 }
1408}
1409
1410/// APB2 peripheral clock enable register (RCC_APB2ENR)
1411pub mod APB2ENR {
1412
1413 /// Alternate function I/O clock enable
1414 pub mod AFIOEN {
1415 /// Offset (0 bits)
1416 pub const offset: u32 = 0;
1417 /// Mask (1 bit: 1 << 0)
1418 pub const mask: u32 = 1 << offset;
1419 /// Read-only values (empty)
1420 pub mod R {}
1421 /// Write-only values (empty)
1422 pub mod W {}
1423 /// Read-write values
1424 pub mod RW {
1425
1426 /// 0b0: The selected clock is disabled
1427 pub const Disabled: u32 = 0b0;
1428
1429 /// 0b1: The selected clock is enabled
1430 pub const Enabled: u32 = 0b1;
1431 }
1432 }
1433
1434 /// I/O port A clock enable
1435 pub mod IOPAEN {
1436 /// Offset (2 bits)
1437 pub const offset: u32 = 2;
1438 /// Mask (1 bit: 1 << 2)
1439 pub const mask: u32 = 1 << offset;
1440 /// Read-only values (empty)
1441 pub mod R {}
1442 /// Write-only values (empty)
1443 pub mod W {}
1444 pub use super::AFIOEN::RW;
1445 }
1446
1447 /// I/O port B clock enable
1448 pub mod IOPBEN {
1449 /// Offset (3 bits)
1450 pub const offset: u32 = 3;
1451 /// Mask (1 bit: 1 << 3)
1452 pub const mask: u32 = 1 << offset;
1453 /// Read-only values (empty)
1454 pub mod R {}
1455 /// Write-only values (empty)
1456 pub mod W {}
1457 pub use super::AFIOEN::RW;
1458 }
1459
1460 /// I/O port C clock enable
1461 pub mod IOPCEN {
1462 /// Offset (4 bits)
1463 pub const offset: u32 = 4;
1464 /// Mask (1 bit: 1 << 4)
1465 pub const mask: u32 = 1 << offset;
1466 /// Read-only values (empty)
1467 pub mod R {}
1468 /// Write-only values (empty)
1469 pub mod W {}
1470 pub use super::AFIOEN::RW;
1471 }
1472
1473 /// I/O port D clock enable
1474 pub mod IOPDEN {
1475 /// Offset (5 bits)
1476 pub const offset: u32 = 5;
1477 /// Mask (1 bit: 1 << 5)
1478 pub const mask: u32 = 1 << offset;
1479 /// Read-only values (empty)
1480 pub mod R {}
1481 /// Write-only values (empty)
1482 pub mod W {}
1483 pub use super::AFIOEN::RW;
1484 }
1485
1486 /// I/O port E clock enable
1487 pub mod IOPEEN {
1488 /// Offset (6 bits)
1489 pub const offset: u32 = 6;
1490 /// Mask (1 bit: 1 << 6)
1491 pub const mask: u32 = 1 << offset;
1492 /// Read-only values (empty)
1493 pub mod R {}
1494 /// Write-only values (empty)
1495 pub mod W {}
1496 pub use super::AFIOEN::RW;
1497 }
1498
1499 /// I/O port F clock enable
1500 pub mod IOPFEN {
1501 /// Offset (7 bits)
1502 pub const offset: u32 = 7;
1503 /// Mask (1 bit: 1 << 7)
1504 pub const mask: u32 = 1 << offset;
1505 /// Read-only values (empty)
1506 pub mod R {}
1507 /// Write-only values (empty)
1508 pub mod W {}
1509 pub use super::AFIOEN::RW;
1510 }
1511
1512 /// I/O port G clock enable
1513 pub mod IOPGEN {
1514 /// Offset (8 bits)
1515 pub const offset: u32 = 8;
1516 /// Mask (1 bit: 1 << 8)
1517 pub const mask: u32 = 1 << offset;
1518 /// Read-only values (empty)
1519 pub mod R {}
1520 /// Write-only values (empty)
1521 pub mod W {}
1522 pub use super::AFIOEN::RW;
1523 }
1524
1525 /// ADC 1 interface clock enable
1526 pub mod ADC1EN {
1527 /// Offset (9 bits)
1528 pub const offset: u32 = 9;
1529 /// Mask (1 bit: 1 << 9)
1530 pub const mask: u32 = 1 << offset;
1531 /// Read-only values (empty)
1532 pub mod R {}
1533 /// Write-only values (empty)
1534 pub mod W {}
1535 pub use super::AFIOEN::RW;
1536 }
1537
1538 /// ADC 2 interface clock enable
1539 pub mod ADC2EN {
1540 /// Offset (10 bits)
1541 pub const offset: u32 = 10;
1542 /// Mask (1 bit: 1 << 10)
1543 pub const mask: u32 = 1 << offset;
1544 /// Read-only values (empty)
1545 pub mod R {}
1546 /// Write-only values (empty)
1547 pub mod W {}
1548 pub use super::AFIOEN::RW;
1549 }
1550
1551 /// TIM1 Timer clock enable
1552 pub mod TIM1EN {
1553 /// Offset (11 bits)
1554 pub const offset: u32 = 11;
1555 /// Mask (1 bit: 1 << 11)
1556 pub const mask: u32 = 1 << offset;
1557 /// Read-only values (empty)
1558 pub mod R {}
1559 /// Write-only values (empty)
1560 pub mod W {}
1561 pub use super::AFIOEN::RW;
1562 }
1563
1564 /// SPI 1 clock enable
1565 pub mod SPI1EN {
1566 /// Offset (12 bits)
1567 pub const offset: u32 = 12;
1568 /// Mask (1 bit: 1 << 12)
1569 pub const mask: u32 = 1 << offset;
1570 /// Read-only values (empty)
1571 pub mod R {}
1572 /// Write-only values (empty)
1573 pub mod W {}
1574 pub use super::AFIOEN::RW;
1575 }
1576
1577 /// TIM8 Timer clock enable
1578 pub mod TIM8EN {
1579 /// Offset (13 bits)
1580 pub const offset: u32 = 13;
1581 /// Mask (1 bit: 1 << 13)
1582 pub const mask: u32 = 1 << offset;
1583 /// Read-only values (empty)
1584 pub mod R {}
1585 /// Write-only values (empty)
1586 pub mod W {}
1587 pub use super::AFIOEN::RW;
1588 }
1589
1590 /// USART1 clock enable
1591 pub mod USART1EN {
1592 /// Offset (14 bits)
1593 pub const offset: u32 = 14;
1594 /// Mask (1 bit: 1 << 14)
1595 pub const mask: u32 = 1 << offset;
1596 /// Read-only values (empty)
1597 pub mod R {}
1598 /// Write-only values (empty)
1599 pub mod W {}
1600 pub use super::AFIOEN::RW;
1601 }
1602
1603 /// ADC3 interface clock enable
1604 pub mod ADC3EN {
1605 /// Offset (15 bits)
1606 pub const offset: u32 = 15;
1607 /// Mask (1 bit: 1 << 15)
1608 pub const mask: u32 = 1 << offset;
1609 /// Read-only values (empty)
1610 pub mod R {}
1611 /// Write-only values (empty)
1612 pub mod W {}
1613 pub use super::AFIOEN::RW;
1614 }
1615
1616 /// TIM9 Timer clock enable
1617 pub mod TIM9EN {
1618 /// Offset (19 bits)
1619 pub const offset: u32 = 19;
1620 /// Mask (1 bit: 1 << 19)
1621 pub const mask: u32 = 1 << offset;
1622 /// Read-only values (empty)
1623 pub mod R {}
1624 /// Write-only values (empty)
1625 pub mod W {}
1626 pub use super::AFIOEN::RW;
1627 }
1628
1629 /// TIM10 Timer clock enable
1630 pub mod TIM10EN {
1631 /// Offset (20 bits)
1632 pub const offset: u32 = 20;
1633 /// Mask (1 bit: 1 << 20)
1634 pub const mask: u32 = 1 << offset;
1635 /// Read-only values (empty)
1636 pub mod R {}
1637 /// Write-only values (empty)
1638 pub mod W {}
1639 pub use super::AFIOEN::RW;
1640 }
1641
1642 /// TIM11 Timer clock enable
1643 pub mod TIM11EN {
1644 /// Offset (21 bits)
1645 pub const offset: u32 = 21;
1646 /// Mask (1 bit: 1 << 21)
1647 pub const mask: u32 = 1 << offset;
1648 /// Read-only values (empty)
1649 pub mod R {}
1650 /// Write-only values (empty)
1651 pub mod W {}
1652 pub use super::AFIOEN::RW;
1653 }
1654}
1655
1656/// APB1 peripheral clock enable register (RCC_APB1ENR)
1657pub mod APB1ENR {
1658
1659 /// Timer 2 clock enable
1660 pub mod TIM2EN {
1661 /// Offset (0 bits)
1662 pub const offset: u32 = 0;
1663 /// Mask (1 bit: 1 << 0)
1664 pub const mask: u32 = 1 << offset;
1665 /// Read-only values (empty)
1666 pub mod R {}
1667 /// Write-only values (empty)
1668 pub mod W {}
1669 /// Read-write values
1670 pub mod RW {
1671
1672 /// 0b0: The selected clock is disabled
1673 pub const Disabled: u32 = 0b0;
1674
1675 /// 0b1: The selected clock is enabled
1676 pub const Enabled: u32 = 0b1;
1677 }
1678 }
1679
1680 /// Timer 3 clock enable
1681 pub mod TIM3EN {
1682 /// Offset (1 bits)
1683 pub const offset: u32 = 1;
1684 /// Mask (1 bit: 1 << 1)
1685 pub const mask: u32 = 1 << offset;
1686 /// Read-only values (empty)
1687 pub mod R {}
1688 /// Write-only values (empty)
1689 pub mod W {}
1690 pub use super::TIM2EN::RW;
1691 }
1692
1693 /// Timer 4 clock enable
1694 pub mod TIM4EN {
1695 /// Offset (2 bits)
1696 pub const offset: u32 = 2;
1697 /// Mask (1 bit: 1 << 2)
1698 pub const mask: u32 = 1 << offset;
1699 /// Read-only values (empty)
1700 pub mod R {}
1701 /// Write-only values (empty)
1702 pub mod W {}
1703 pub use super::TIM2EN::RW;
1704 }
1705
1706 /// Timer 5 clock enable
1707 pub mod TIM5EN {
1708 /// Offset (3 bits)
1709 pub const offset: u32 = 3;
1710 /// Mask (1 bit: 1 << 3)
1711 pub const mask: u32 = 1 << offset;
1712 /// Read-only values (empty)
1713 pub mod R {}
1714 /// Write-only values (empty)
1715 pub mod W {}
1716 pub use super::TIM2EN::RW;
1717 }
1718
1719 /// Timer 6 clock enable
1720 pub mod TIM6EN {
1721 /// Offset (4 bits)
1722 pub const offset: u32 = 4;
1723 /// Mask (1 bit: 1 << 4)
1724 pub const mask: u32 = 1 << offset;
1725 /// Read-only values (empty)
1726 pub mod R {}
1727 /// Write-only values (empty)
1728 pub mod W {}
1729 pub use super::TIM2EN::RW;
1730 }
1731
1732 /// Timer 7 clock enable
1733 pub mod TIM7EN {
1734 /// Offset (5 bits)
1735 pub const offset: u32 = 5;
1736 /// Mask (1 bit: 1 << 5)
1737 pub const mask: u32 = 1 << offset;
1738 /// Read-only values (empty)
1739 pub mod R {}
1740 /// Write-only values (empty)
1741 pub mod W {}
1742 pub use super::TIM2EN::RW;
1743 }
1744
1745 /// Timer 12 clock enable
1746 pub mod TIM12EN {
1747 /// Offset (6 bits)
1748 pub const offset: u32 = 6;
1749 /// Mask (1 bit: 1 << 6)
1750 pub const mask: u32 = 1 << offset;
1751 /// Read-only values (empty)
1752 pub mod R {}
1753 /// Write-only values (empty)
1754 pub mod W {}
1755 pub use super::TIM2EN::RW;
1756 }
1757
1758 /// Timer 13 clock enable
1759 pub mod TIM13EN {
1760 /// Offset (7 bits)
1761 pub const offset: u32 = 7;
1762 /// Mask (1 bit: 1 << 7)
1763 pub const mask: u32 = 1 << offset;
1764 /// Read-only values (empty)
1765 pub mod R {}
1766 /// Write-only values (empty)
1767 pub mod W {}
1768 pub use super::TIM2EN::RW;
1769 }
1770
1771 /// Timer 14 clock enable
1772 pub mod TIM14EN {
1773 /// Offset (8 bits)
1774 pub const offset: u32 = 8;
1775 /// Mask (1 bit: 1 << 8)
1776 pub const mask: u32 = 1 << offset;
1777 /// Read-only values (empty)
1778 pub mod R {}
1779 /// Write-only values (empty)
1780 pub mod W {}
1781 pub use super::TIM2EN::RW;
1782 }
1783
1784 /// Window watchdog clock enable
1785 pub mod WWDGEN {
1786 /// Offset (11 bits)
1787 pub const offset: u32 = 11;
1788 /// Mask (1 bit: 1 << 11)
1789 pub const mask: u32 = 1 << offset;
1790 /// Read-only values (empty)
1791 pub mod R {}
1792 /// Write-only values (empty)
1793 pub mod W {}
1794 pub use super::TIM2EN::RW;
1795 }
1796
1797 /// SPI 2 clock enable
1798 pub mod SPI2EN {
1799 /// Offset (14 bits)
1800 pub const offset: u32 = 14;
1801 /// Mask (1 bit: 1 << 14)
1802 pub const mask: u32 = 1 << offset;
1803 /// Read-only values (empty)
1804 pub mod R {}
1805 /// Write-only values (empty)
1806 pub mod W {}
1807 pub use super::TIM2EN::RW;
1808 }
1809
1810 /// SPI 3 clock enable
1811 pub mod SPI3EN {
1812 /// Offset (15 bits)
1813 pub const offset: u32 = 15;
1814 /// Mask (1 bit: 1 << 15)
1815 pub const mask: u32 = 1 << offset;
1816 /// Read-only values (empty)
1817 pub mod R {}
1818 /// Write-only values (empty)
1819 pub mod W {}
1820 pub use super::TIM2EN::RW;
1821 }
1822
1823 /// USART 2 clock enable
1824 pub mod USART2EN {
1825 /// Offset (17 bits)
1826 pub const offset: u32 = 17;
1827 /// Mask (1 bit: 1 << 17)
1828 pub const mask: u32 = 1 << offset;
1829 /// Read-only values (empty)
1830 pub mod R {}
1831 /// Write-only values (empty)
1832 pub mod W {}
1833 pub use super::TIM2EN::RW;
1834 }
1835
1836 /// USART 3 clock enable
1837 pub mod USART3EN {
1838 /// Offset (18 bits)
1839 pub const offset: u32 = 18;
1840 /// Mask (1 bit: 1 << 18)
1841 pub const mask: u32 = 1 << offset;
1842 /// Read-only values (empty)
1843 pub mod R {}
1844 /// Write-only values (empty)
1845 pub mod W {}
1846 pub use super::TIM2EN::RW;
1847 }
1848
1849 /// UART 4 clock enable
1850 pub mod UART4EN {
1851 /// Offset (19 bits)
1852 pub const offset: u32 = 19;
1853 /// Mask (1 bit: 1 << 19)
1854 pub const mask: u32 = 1 << offset;
1855 /// Read-only values (empty)
1856 pub mod R {}
1857 /// Write-only values (empty)
1858 pub mod W {}
1859 pub use super::TIM2EN::RW;
1860 }
1861
1862 /// UART 5 clock enable
1863 pub mod UART5EN {
1864 /// Offset (20 bits)
1865 pub const offset: u32 = 20;
1866 /// Mask (1 bit: 1 << 20)
1867 pub const mask: u32 = 1 << offset;
1868 /// Read-only values (empty)
1869 pub mod R {}
1870 /// Write-only values (empty)
1871 pub mod W {}
1872 pub use super::TIM2EN::RW;
1873 }
1874
1875 /// I2C 1 clock enable
1876 pub mod I2C1EN {
1877 /// Offset (21 bits)
1878 pub const offset: u32 = 21;
1879 /// Mask (1 bit: 1 << 21)
1880 pub const mask: u32 = 1 << offset;
1881 /// Read-only values (empty)
1882 pub mod R {}
1883 /// Write-only values (empty)
1884 pub mod W {}
1885 pub use super::TIM2EN::RW;
1886 }
1887
1888 /// I2C 2 clock enable
1889 pub mod I2C2EN {
1890 /// Offset (22 bits)
1891 pub const offset: u32 = 22;
1892 /// Mask (1 bit: 1 << 22)
1893 pub const mask: u32 = 1 << offset;
1894 /// Read-only values (empty)
1895 pub mod R {}
1896 /// Write-only values (empty)
1897 pub mod W {}
1898 pub use super::TIM2EN::RW;
1899 }
1900
1901 /// USB clock enable
1902 pub mod USBEN {
1903 /// Offset (23 bits)
1904 pub const offset: u32 = 23;
1905 /// Mask (1 bit: 1 << 23)
1906 pub const mask: u32 = 1 << offset;
1907 /// Read-only values (empty)
1908 pub mod R {}
1909 /// Write-only values (empty)
1910 pub mod W {}
1911 pub use super::TIM2EN::RW;
1912 }
1913
1914 /// CAN clock enable
1915 pub mod CANEN {
1916 /// Offset (25 bits)
1917 pub const offset: u32 = 25;
1918 /// Mask (1 bit: 1 << 25)
1919 pub const mask: u32 = 1 << offset;
1920 /// Read-only values (empty)
1921 pub mod R {}
1922 /// Write-only values (empty)
1923 pub mod W {}
1924 pub use super::TIM2EN::RW;
1925 }
1926
1927 /// Backup interface clock enable
1928 pub mod BKPEN {
1929 /// Offset (27 bits)
1930 pub const offset: u32 = 27;
1931 /// Mask (1 bit: 1 << 27)
1932 pub const mask: u32 = 1 << offset;
1933 /// Read-only values (empty)
1934 pub mod R {}
1935 /// Write-only values (empty)
1936 pub mod W {}
1937 pub use super::TIM2EN::RW;
1938 }
1939
1940 /// Power interface clock enable
1941 pub mod PWREN {
1942 /// Offset (28 bits)
1943 pub const offset: u32 = 28;
1944 /// Mask (1 bit: 1 << 28)
1945 pub const mask: u32 = 1 << offset;
1946 /// Read-only values (empty)
1947 pub mod R {}
1948 /// Write-only values (empty)
1949 pub mod W {}
1950 pub use super::TIM2EN::RW;
1951 }
1952
1953 /// DAC interface clock enable
1954 pub mod DACEN {
1955 /// Offset (29 bits)
1956 pub const offset: u32 = 29;
1957 /// Mask (1 bit: 1 << 29)
1958 pub const mask: u32 = 1 << offset;
1959 /// Read-only values (empty)
1960 pub mod R {}
1961 /// Write-only values (empty)
1962 pub mod W {}
1963 pub use super::TIM2EN::RW;
1964 }
1965}
1966
1967/// Backup domain control register (RCC_BDCR)
1968pub mod BDCR {
1969
1970 /// External Low Speed oscillator enable
1971 pub mod LSEON {
1972 /// Offset (0 bits)
1973 pub const offset: u32 = 0;
1974 /// Mask (1 bit: 1 << 0)
1975 pub const mask: u32 = 1 << offset;
1976 /// Read-only values (empty)
1977 pub mod R {}
1978 /// Write-only values (empty)
1979 pub mod W {}
1980 /// Read-write values
1981 pub mod RW {
1982
1983 /// 0b0: LSE oscillator Off
1984 pub const Off: u32 = 0b0;
1985
1986 /// 0b1: LSE oscillator On
1987 pub const On: u32 = 0b1;
1988 }
1989 }
1990
1991 /// External Low Speed oscillator ready
1992 pub mod LSERDY {
1993 /// Offset (1 bits)
1994 pub const offset: u32 = 1;
1995 /// Mask (1 bit: 1 << 1)
1996 pub const mask: u32 = 1 << offset;
1997 /// Read-only values
1998 pub mod R {
1999
2000 /// 0b0: LSE oscillator not ready
2001 pub const NotReady: u32 = 0b0;
2002
2003 /// 0b1: LSE oscillator ready
2004 pub const Ready: u32 = 0b1;
2005 }
2006 /// Write-only values (empty)
2007 pub mod W {}
2008 /// Read-write values (empty)
2009 pub mod RW {}
2010 }
2011
2012 /// External Low Speed oscillator bypass
2013 pub mod LSEBYP {
2014 /// Offset (2 bits)
2015 pub const offset: u32 = 2;
2016 /// Mask (1 bit: 1 << 2)
2017 pub const mask: u32 = 1 << offset;
2018 /// Read-only values (empty)
2019 pub mod R {}
2020 /// Write-only values (empty)
2021 pub mod W {}
2022 /// Read-write values
2023 pub mod RW {
2024
2025 /// 0b0: LSE crystal oscillator not bypassed
2026 pub const NotBypassed: u32 = 0b0;
2027
2028 /// 0b1: LSE crystal oscillator bypassed with external clock
2029 pub const Bypassed: u32 = 0b1;
2030 }
2031 }
2032
2033 /// RTC clock source selection
2034 pub mod RTCSEL {
2035 /// Offset (8 bits)
2036 pub const offset: u32 = 8;
2037 /// Mask (2 bits: 0b11 << 8)
2038 pub const mask: u32 = 0b11 << offset;
2039 /// Read-only values (empty)
2040 pub mod R {}
2041 /// Write-only values (empty)
2042 pub mod W {}
2043 /// Read-write values
2044 pub mod RW {
2045
2046 /// 0b00: No clock
2047 pub const NoClock: u32 = 0b00;
2048
2049 /// 0b01: LSE oscillator clock used as RTC clock
2050 pub const LSE: u32 = 0b01;
2051
2052 /// 0b10: LSI oscillator clock used as RTC clock
2053 pub const LSI: u32 = 0b10;
2054
2055 /// 0b11: HSE oscillator clock divided by a prescaler used as RTC clock
2056 pub const HSE: u32 = 0b11;
2057 }
2058 }
2059
2060 /// RTC clock enable
2061 pub mod RTCEN {
2062 /// Offset (15 bits)
2063 pub const offset: u32 = 15;
2064 /// Mask (1 bit: 1 << 15)
2065 pub const mask: u32 = 1 << offset;
2066 /// Read-only values (empty)
2067 pub mod R {}
2068 /// Write-only values (empty)
2069 pub mod W {}
2070 /// Read-write values
2071 pub mod RW {
2072
2073 /// 0b0: RTC clock disabled
2074 pub const Disabled: u32 = 0b0;
2075
2076 /// 0b1: RTC clock enabled
2077 pub const Enabled: u32 = 0b1;
2078 }
2079 }
2080
2081 /// Backup domain software reset
2082 pub mod BDRST {
2083 /// Offset (16 bits)
2084 pub const offset: u32 = 16;
2085 /// Mask (1 bit: 1 << 16)
2086 pub const mask: u32 = 1 << offset;
2087 /// Read-only values (empty)
2088 pub mod R {}
2089 /// Write-only values (empty)
2090 pub mod W {}
2091 /// Read-write values
2092 pub mod RW {
2093
2094 /// 0b0: Reset not activated
2095 pub const Disabled: u32 = 0b0;
2096
2097 /// 0b1: Reset the entire RTC domain
2098 pub const Enabled: u32 = 0b1;
2099 }
2100 }
2101}
2102
2103/// Control/status register (RCC_CSR)
2104pub mod CSR {
2105
2106 /// Internal low speed oscillator enable
2107 pub mod LSION {
2108 /// Offset (0 bits)
2109 pub const offset: u32 = 0;
2110 /// Mask (1 bit: 1 << 0)
2111 pub const mask: u32 = 1 << offset;
2112 /// Read-only values (empty)
2113 pub mod R {}
2114 /// Write-only values (empty)
2115 pub mod W {}
2116 /// Read-write values
2117 pub mod RW {
2118
2119 /// 0b0: LSI oscillator Off
2120 pub const Off: u32 = 0b0;
2121
2122 /// 0b1: LSI oscillator On
2123 pub const On: u32 = 0b1;
2124 }
2125 }
2126
2127 /// Internal low speed oscillator ready
2128 pub mod LSIRDY {
2129 /// Offset (1 bits)
2130 pub const offset: u32 = 1;
2131 /// Mask (1 bit: 1 << 1)
2132 pub const mask: u32 = 1 << offset;
2133 /// Read-only values
2134 pub mod R {
2135
2136 /// 0b0: LSI oscillator not ready
2137 pub const NotReady: u32 = 0b0;
2138
2139 /// 0b1: LSI oscillator ready
2140 pub const Ready: u32 = 0b1;
2141 }
2142 /// Write-only values (empty)
2143 pub mod W {}
2144 /// Read-write values (empty)
2145 pub mod RW {}
2146 }
2147
2148 /// Remove reset flag
2149 pub mod RMVF {
2150 /// Offset (24 bits)
2151 pub const offset: u32 = 24;
2152 /// Mask (1 bit: 1 << 24)
2153 pub const mask: u32 = 1 << offset;
2154 /// Read-only values (empty)
2155 pub mod R {}
2156 /// Write-only values
2157 pub mod W {
2158
2159 /// 0b1: Clears the reset flag
2160 pub const Clear: u32 = 0b1;
2161 }
2162 /// Read-write values (empty)
2163 pub mod RW {}
2164 }
2165
2166 /// PIN reset flag
2167 pub mod PINRSTF {
2168 /// Offset (26 bits)
2169 pub const offset: u32 = 26;
2170 /// Mask (1 bit: 1 << 26)
2171 pub const mask: u32 = 1 << offset;
2172 /// Read-only values
2173 pub mod R {
2174
2175 /// 0b0: No reset has occured
2176 pub const NoReset: u32 = 0b0;
2177
2178 /// 0b1: A reset has occured
2179 pub const Reset: u32 = 0b1;
2180 }
2181 /// Write-only values (empty)
2182 pub mod W {}
2183 /// Read-write values (empty)
2184 pub mod RW {}
2185 }
2186
2187 /// POR/PDR reset flag
2188 pub mod PORRSTF {
2189 /// Offset (27 bits)
2190 pub const offset: u32 = 27;
2191 /// Mask (1 bit: 1 << 27)
2192 pub const mask: u32 = 1 << offset;
2193 pub use super::PINRSTF::R;
2194 /// Write-only values (empty)
2195 pub mod W {}
2196 /// Read-write values (empty)
2197 pub mod RW {}
2198 }
2199
2200 /// Software reset flag
2201 pub mod SFTRSTF {
2202 /// Offset (28 bits)
2203 pub const offset: u32 = 28;
2204 /// Mask (1 bit: 1 << 28)
2205 pub const mask: u32 = 1 << offset;
2206 pub use super::PINRSTF::R;
2207 /// Write-only values (empty)
2208 pub mod W {}
2209 /// Read-write values (empty)
2210 pub mod RW {}
2211 }
2212
2213 /// Independent watchdog reset flag
2214 pub mod IWDGRSTF {
2215 /// Offset (29 bits)
2216 pub const offset: u32 = 29;
2217 /// Mask (1 bit: 1 << 29)
2218 pub const mask: u32 = 1 << offset;
2219 pub use super::PINRSTF::R;
2220 /// Write-only values (empty)
2221 pub mod W {}
2222 /// Read-write values (empty)
2223 pub mod RW {}
2224 }
2225
2226 /// Window watchdog reset flag
2227 pub mod WWDGRSTF {
2228 /// Offset (30 bits)
2229 pub const offset: u32 = 30;
2230 /// Mask (1 bit: 1 << 30)
2231 pub const mask: u32 = 1 << offset;
2232 pub use super::PINRSTF::R;
2233 /// Write-only values (empty)
2234 pub mod W {}
2235 /// Read-write values (empty)
2236 pub mod RW {}
2237 }
2238
2239 /// Low-power reset flag
2240 pub mod LPWRRSTF {
2241 /// Offset (31 bits)
2242 pub const offset: u32 = 31;
2243 /// Mask (1 bit: 1 << 31)
2244 pub const mask: u32 = 1 << offset;
2245 pub use super::PINRSTF::R;
2246 /// Write-only values (empty)
2247 pub mod W {}
2248 /// Read-write values (empty)
2249 pub mod RW {}
2250 }
2251}
2252#[repr(C)]
2253pub struct RegisterBlock {
2254 /// Clock control register
2255 pub CR: RWRegister<u32>,
2256
2257 /// Clock configuration register (RCC_CFGR)
2258 pub CFGR: RWRegister<u32>,
2259
2260 /// Clock interrupt register (RCC_CIR)
2261 pub CIR: RWRegister<u32>,
2262
2263 /// APB2 peripheral reset register (RCC_APB2RSTR)
2264 pub APB2RSTR: RWRegister<u32>,
2265
2266 /// APB1 peripheral reset register (RCC_APB1RSTR)
2267 pub APB1RSTR: RWRegister<u32>,
2268
2269 /// AHB Peripheral Clock enable register (RCC_AHBENR)
2270 pub AHBENR: RWRegister<u32>,
2271
2272 /// APB2 peripheral clock enable register (RCC_APB2ENR)
2273 pub APB2ENR: RWRegister<u32>,
2274
2275 /// APB1 peripheral clock enable register (RCC_APB1ENR)
2276 pub APB1ENR: RWRegister<u32>,
2277
2278 /// Backup domain control register (RCC_BDCR)
2279 pub BDCR: RWRegister<u32>,
2280
2281 /// Control/status register (RCC_CSR)
2282 pub CSR: RWRegister<u32>,
2283}
2284pub struct ResetValues {
2285 pub CR: u32,
2286 pub CFGR: u32,
2287 pub CIR: u32,
2288 pub APB2RSTR: u32,
2289 pub APB1RSTR: u32,
2290 pub AHBENR: u32,
2291 pub APB2ENR: u32,
2292 pub APB1ENR: u32,
2293 pub BDCR: u32,
2294 pub CSR: u32,
2295}
2296#[cfg(not(feature = "nosync"))]
2297pub struct Instance {
2298 pub(crate) addr: u32,
2299 pub(crate) _marker: PhantomData<*const RegisterBlock>,
2300}
2301#[cfg(not(feature = "nosync"))]
2302impl ::core::ops::Deref for Instance {
2303 type Target = RegisterBlock;
2304 #[inline(always)]
2305 fn deref(&self) -> &RegisterBlock {
2306 unsafe { &*(self.addr as *const _) }
2307 }
2308}
2309#[cfg(feature = "rtic")]
2310unsafe impl Send for Instance {}
2311
2312/// Access functions for the RCC peripheral instance
2313pub mod RCC {
2314 use super::ResetValues;
2315
2316 #[cfg(not(feature = "nosync"))]
2317 use super::Instance;
2318
2319 #[cfg(not(feature = "nosync"))]
2320 const INSTANCE: Instance = Instance {
2321 addr: 0x40021000,
2322 _marker: ::core::marker::PhantomData,
2323 };
2324
2325 /// Reset values for each field in RCC
2326 pub const reset: ResetValues = ResetValues {
2327 CR: 0x00000083,
2328 CFGR: 0x00000000,
2329 CIR: 0x00000000,
2330 APB2RSTR: 0x00000000,
2331 APB1RSTR: 0x00000000,
2332 AHBENR: 0x00000014,
2333 APB2ENR: 0x00000000,
2334 APB1ENR: 0x00000000,
2335 BDCR: 0x00000000,
2336 CSR: 0x0C000000,
2337 };
2338
2339 #[cfg(not(feature = "nosync"))]
2340 #[allow(renamed_and_removed_lints)]
2341 #[allow(private_no_mangle_statics)]
2342 #[no_mangle]
2343 static mut RCC_TAKEN: bool = false;
2344
2345 /// Safe access to RCC
2346 ///
2347 /// This function returns `Some(Instance)` if this instance is not
2348 /// currently taken, and `None` if it is. This ensures that if you
2349 /// do get `Some(Instance)`, you are ensured unique access to
2350 /// the peripheral and there cannot be data races (unless other
2351 /// code uses `unsafe`, of course). You can then pass the
2352 /// `Instance` around to other functions as required. When you're
2353 /// done with it, you can call `release(instance)` to return it.
2354 ///
2355 /// `Instance` itself dereferences to a `RegisterBlock`, which
2356 /// provides access to the peripheral's registers.
2357 #[cfg(not(feature = "nosync"))]
2358 #[inline]
2359 pub fn take() -> Option<Instance> {
2360 external_cortex_m::interrupt::free(|_| unsafe {
2361 if RCC_TAKEN {
2362 None
2363 } else {
2364 RCC_TAKEN = true;
2365 Some(INSTANCE)
2366 }
2367 })
2368 }
2369
2370 /// Release exclusive access to RCC
2371 ///
2372 /// This function allows you to return an `Instance` so that it
2373 /// is available to `take()` again. This function will panic if
2374 /// you return a different `Instance` or if this instance is not
2375 /// already taken.
2376 #[cfg(not(feature = "nosync"))]
2377 #[inline]
2378 pub fn release(inst: Instance) {
2379 external_cortex_m::interrupt::free(|_| unsafe {
2380 if RCC_TAKEN && inst.addr == INSTANCE.addr {
2381 RCC_TAKEN = false;
2382 } else {
2383 panic!("Released a peripheral which was not taken");
2384 }
2385 });
2386 }
2387
2388 /// Unsafely steal RCC
2389 ///
2390 /// This function is similar to take() but forcibly takes the
2391 /// Instance, marking it as taken irregardless of its previous
2392 /// state.
2393 #[cfg(not(feature = "nosync"))]
2394 #[inline]
2395 pub unsafe fn steal() -> Instance {
2396 RCC_TAKEN = true;
2397 INSTANCE
2398 }
2399}
2400
2401/// Raw pointer to RCC
2402///
2403/// Dereferencing this is unsafe because you are not ensured unique
2404/// access to the peripheral, so you may encounter data races with
2405/// other users of this peripheral. It is up to you to ensure you
2406/// will not cause data races.
2407///
2408/// This constant is provided for ease of use in unsafe code: you can
2409/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
2410pub const RCC: *const RegisterBlock = 0x40021000 as *const _;