stm32ral/stm32f2/peripherals/can.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Controller area network
4//!
5//! Used by: stm32f215, stm32f217
6
7use crate::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// master control register
12pub mod MCR {
13
14 /// DBF
15 pub mod DBF {
16 /// Offset (16 bits)
17 pub const offset: u32 = 16;
18 /// Mask (1 bit: 1 << 16)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// RESET
29 pub mod RESET {
30 /// Offset (15 bits)
31 pub const offset: u32 = 15;
32 /// Mask (1 bit: 1 << 15)
33 pub const mask: u32 = 1 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// TTCM
43 pub mod TTCM {
44 /// Offset (7 bits)
45 pub const offset: u32 = 7;
46 /// Mask (1 bit: 1 << 7)
47 pub const mask: u32 = 1 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// ABOM
57 pub mod ABOM {
58 /// Offset (6 bits)
59 pub const offset: u32 = 6;
60 /// Mask (1 bit: 1 << 6)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// AWUM
71 pub mod AWUM {
72 /// Offset (5 bits)
73 pub const offset: u32 = 5;
74 /// Mask (1 bit: 1 << 5)
75 pub const mask: u32 = 1 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83
84 /// NART
85 pub mod NART {
86 /// Offset (4 bits)
87 pub const offset: u32 = 4;
88 /// Mask (1 bit: 1 << 4)
89 pub const mask: u32 = 1 << offset;
90 /// Read-only values (empty)
91 pub mod R {}
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values (empty)
95 pub mod RW {}
96 }
97
98 /// RFLM
99 pub mod RFLM {
100 /// Offset (3 bits)
101 pub const offset: u32 = 3;
102 /// Mask (1 bit: 1 << 3)
103 pub const mask: u32 = 1 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values (empty)
109 pub mod RW {}
110 }
111
112 /// TXFP
113 pub mod TXFP {
114 /// Offset (2 bits)
115 pub const offset: u32 = 2;
116 /// Mask (1 bit: 1 << 2)
117 pub const mask: u32 = 1 << offset;
118 /// Read-only values (empty)
119 pub mod R {}
120 /// Write-only values (empty)
121 pub mod W {}
122 /// Read-write values (empty)
123 pub mod RW {}
124 }
125
126 /// SLEEP
127 pub mod SLEEP {
128 /// Offset (1 bits)
129 pub const offset: u32 = 1;
130 /// Mask (1 bit: 1 << 1)
131 pub const mask: u32 = 1 << offset;
132 /// Read-only values (empty)
133 pub mod R {}
134 /// Write-only values (empty)
135 pub mod W {}
136 /// Read-write values (empty)
137 pub mod RW {}
138 }
139
140 /// INRQ
141 pub mod INRQ {
142 /// Offset (0 bits)
143 pub const offset: u32 = 0;
144 /// Mask (1 bit: 1 << 0)
145 pub const mask: u32 = 1 << offset;
146 /// Read-only values (empty)
147 pub mod R {}
148 /// Write-only values (empty)
149 pub mod W {}
150 /// Read-write values (empty)
151 pub mod RW {}
152 }
153}
154
155/// master status register
156pub mod MSR {
157
158 /// RX
159 pub mod RX {
160 /// Offset (11 bits)
161 pub const offset: u32 = 11;
162 /// Mask (1 bit: 1 << 11)
163 pub const mask: u32 = 1 << offset;
164 /// Read-only values (empty)
165 pub mod R {}
166 /// Write-only values (empty)
167 pub mod W {}
168 /// Read-write values (empty)
169 pub mod RW {}
170 }
171
172 /// SAMP
173 pub mod SAMP {
174 /// Offset (10 bits)
175 pub const offset: u32 = 10;
176 /// Mask (1 bit: 1 << 10)
177 pub const mask: u32 = 1 << offset;
178 /// Read-only values (empty)
179 pub mod R {}
180 /// Write-only values (empty)
181 pub mod W {}
182 /// Read-write values (empty)
183 pub mod RW {}
184 }
185
186 /// RXM
187 pub mod RXM {
188 /// Offset (9 bits)
189 pub const offset: u32 = 9;
190 /// Mask (1 bit: 1 << 9)
191 pub const mask: u32 = 1 << offset;
192 /// Read-only values (empty)
193 pub mod R {}
194 /// Write-only values (empty)
195 pub mod W {}
196 /// Read-write values (empty)
197 pub mod RW {}
198 }
199
200 /// TXM
201 pub mod TXM {
202 /// Offset (8 bits)
203 pub const offset: u32 = 8;
204 /// Mask (1 bit: 1 << 8)
205 pub const mask: u32 = 1 << offset;
206 /// Read-only values (empty)
207 pub mod R {}
208 /// Write-only values (empty)
209 pub mod W {}
210 /// Read-write values (empty)
211 pub mod RW {}
212 }
213
214 /// SLAKI
215 pub mod SLAKI {
216 /// Offset (4 bits)
217 pub const offset: u32 = 4;
218 /// Mask (1 bit: 1 << 4)
219 pub const mask: u32 = 1 << offset;
220 /// Read-only values (empty)
221 pub mod R {}
222 /// Write-only values (empty)
223 pub mod W {}
224 /// Read-write values (empty)
225 pub mod RW {}
226 }
227
228 /// WKUI
229 pub mod WKUI {
230 /// Offset (3 bits)
231 pub const offset: u32 = 3;
232 /// Mask (1 bit: 1 << 3)
233 pub const mask: u32 = 1 << offset;
234 /// Read-only values (empty)
235 pub mod R {}
236 /// Write-only values (empty)
237 pub mod W {}
238 /// Read-write values (empty)
239 pub mod RW {}
240 }
241
242 /// ERRI
243 pub mod ERRI {
244 /// Offset (2 bits)
245 pub const offset: u32 = 2;
246 /// Mask (1 bit: 1 << 2)
247 pub const mask: u32 = 1 << offset;
248 /// Read-only values (empty)
249 pub mod R {}
250 /// Write-only values (empty)
251 pub mod W {}
252 /// Read-write values (empty)
253 pub mod RW {}
254 }
255
256 /// SLAK
257 pub mod SLAK {
258 /// Offset (1 bits)
259 pub const offset: u32 = 1;
260 /// Mask (1 bit: 1 << 1)
261 pub const mask: u32 = 1 << offset;
262 /// Read-only values (empty)
263 pub mod R {}
264 /// Write-only values (empty)
265 pub mod W {}
266 /// Read-write values (empty)
267 pub mod RW {}
268 }
269
270 /// INAK
271 pub mod INAK {
272 /// Offset (0 bits)
273 pub const offset: u32 = 0;
274 /// Mask (1 bit: 1 << 0)
275 pub const mask: u32 = 1 << offset;
276 /// Read-only values (empty)
277 pub mod R {}
278 /// Write-only values (empty)
279 pub mod W {}
280 /// Read-write values (empty)
281 pub mod RW {}
282 }
283}
284
285/// transmit status register
286pub mod TSR {
287
288 /// Lowest priority flag for mailbox 2
289 pub mod LOW2 {
290 /// Offset (31 bits)
291 pub const offset: u32 = 31;
292 /// Mask (1 bit: 1 << 31)
293 pub const mask: u32 = 1 << offset;
294 /// Read-only values (empty)
295 pub mod R {}
296 /// Write-only values (empty)
297 pub mod W {}
298 /// Read-write values (empty)
299 pub mod RW {}
300 }
301
302 /// Lowest priority flag for mailbox 1
303 pub mod LOW1 {
304 /// Offset (30 bits)
305 pub const offset: u32 = 30;
306 /// Mask (1 bit: 1 << 30)
307 pub const mask: u32 = 1 << offset;
308 /// Read-only values (empty)
309 pub mod R {}
310 /// Write-only values (empty)
311 pub mod W {}
312 /// Read-write values (empty)
313 pub mod RW {}
314 }
315
316 /// Lowest priority flag for mailbox 0
317 pub mod LOW0 {
318 /// Offset (29 bits)
319 pub const offset: u32 = 29;
320 /// Mask (1 bit: 1 << 29)
321 pub const mask: u32 = 1 << offset;
322 /// Read-only values (empty)
323 pub mod R {}
324 /// Write-only values (empty)
325 pub mod W {}
326 /// Read-write values (empty)
327 pub mod RW {}
328 }
329
330 /// Lowest priority flag for mailbox 2
331 pub mod TME2 {
332 /// Offset (28 bits)
333 pub const offset: u32 = 28;
334 /// Mask (1 bit: 1 << 28)
335 pub const mask: u32 = 1 << offset;
336 /// Read-only values (empty)
337 pub mod R {}
338 /// Write-only values (empty)
339 pub mod W {}
340 /// Read-write values (empty)
341 pub mod RW {}
342 }
343
344 /// Lowest priority flag for mailbox 1
345 pub mod TME1 {
346 /// Offset (27 bits)
347 pub const offset: u32 = 27;
348 /// Mask (1 bit: 1 << 27)
349 pub const mask: u32 = 1 << offset;
350 /// Read-only values (empty)
351 pub mod R {}
352 /// Write-only values (empty)
353 pub mod W {}
354 /// Read-write values (empty)
355 pub mod RW {}
356 }
357
358 /// Lowest priority flag for mailbox 0
359 pub mod TME0 {
360 /// Offset (26 bits)
361 pub const offset: u32 = 26;
362 /// Mask (1 bit: 1 << 26)
363 pub const mask: u32 = 1 << offset;
364 /// Read-only values (empty)
365 pub mod R {}
366 /// Write-only values (empty)
367 pub mod W {}
368 /// Read-write values (empty)
369 pub mod RW {}
370 }
371
372 /// CODE
373 pub mod CODE {
374 /// Offset (24 bits)
375 pub const offset: u32 = 24;
376 /// Mask (2 bits: 0b11 << 24)
377 pub const mask: u32 = 0b11 << offset;
378 /// Read-only values (empty)
379 pub mod R {}
380 /// Write-only values (empty)
381 pub mod W {}
382 /// Read-write values (empty)
383 pub mod RW {}
384 }
385
386 /// ABRQ2
387 pub mod ABRQ2 {
388 /// Offset (23 bits)
389 pub const offset: u32 = 23;
390 /// Mask (1 bit: 1 << 23)
391 pub const mask: u32 = 1 << offset;
392 /// Read-only values (empty)
393 pub mod R {}
394 /// Write-only values (empty)
395 pub mod W {}
396 /// Read-write values (empty)
397 pub mod RW {}
398 }
399
400 /// TERR2
401 pub mod TERR2 {
402 /// Offset (19 bits)
403 pub const offset: u32 = 19;
404 /// Mask (1 bit: 1 << 19)
405 pub const mask: u32 = 1 << offset;
406 /// Read-only values (empty)
407 pub mod R {}
408 /// Write-only values (empty)
409 pub mod W {}
410 /// Read-write values (empty)
411 pub mod RW {}
412 }
413
414 /// ALST2
415 pub mod ALST2 {
416 /// Offset (18 bits)
417 pub const offset: u32 = 18;
418 /// Mask (1 bit: 1 << 18)
419 pub const mask: u32 = 1 << offset;
420 /// Read-only values (empty)
421 pub mod R {}
422 /// Write-only values (empty)
423 pub mod W {}
424 /// Read-write values (empty)
425 pub mod RW {}
426 }
427
428 /// TXOK2
429 pub mod TXOK2 {
430 /// Offset (17 bits)
431 pub const offset: u32 = 17;
432 /// Mask (1 bit: 1 << 17)
433 pub const mask: u32 = 1 << offset;
434 /// Read-only values (empty)
435 pub mod R {}
436 /// Write-only values (empty)
437 pub mod W {}
438 /// Read-write values (empty)
439 pub mod RW {}
440 }
441
442 /// RQCP2
443 pub mod RQCP2 {
444 /// Offset (16 bits)
445 pub const offset: u32 = 16;
446 /// Mask (1 bit: 1 << 16)
447 pub const mask: u32 = 1 << offset;
448 /// Read-only values (empty)
449 pub mod R {}
450 /// Write-only values (empty)
451 pub mod W {}
452 /// Read-write values (empty)
453 pub mod RW {}
454 }
455
456 /// ABRQ1
457 pub mod ABRQ1 {
458 /// Offset (15 bits)
459 pub const offset: u32 = 15;
460 /// Mask (1 bit: 1 << 15)
461 pub const mask: u32 = 1 << offset;
462 /// Read-only values (empty)
463 pub mod R {}
464 /// Write-only values (empty)
465 pub mod W {}
466 /// Read-write values (empty)
467 pub mod RW {}
468 }
469
470 /// TERR1
471 pub mod TERR1 {
472 /// Offset (11 bits)
473 pub const offset: u32 = 11;
474 /// Mask (1 bit: 1 << 11)
475 pub const mask: u32 = 1 << offset;
476 /// Read-only values (empty)
477 pub mod R {}
478 /// Write-only values (empty)
479 pub mod W {}
480 /// Read-write values (empty)
481 pub mod RW {}
482 }
483
484 /// ALST1
485 pub mod ALST1 {
486 /// Offset (10 bits)
487 pub const offset: u32 = 10;
488 /// Mask (1 bit: 1 << 10)
489 pub const mask: u32 = 1 << offset;
490 /// Read-only values (empty)
491 pub mod R {}
492 /// Write-only values (empty)
493 pub mod W {}
494 /// Read-write values (empty)
495 pub mod RW {}
496 }
497
498 /// TXOK1
499 pub mod TXOK1 {
500 /// Offset (9 bits)
501 pub const offset: u32 = 9;
502 /// Mask (1 bit: 1 << 9)
503 pub const mask: u32 = 1 << offset;
504 /// Read-only values (empty)
505 pub mod R {}
506 /// Write-only values (empty)
507 pub mod W {}
508 /// Read-write values (empty)
509 pub mod RW {}
510 }
511
512 /// RQCP1
513 pub mod RQCP1 {
514 /// Offset (8 bits)
515 pub const offset: u32 = 8;
516 /// Mask (1 bit: 1 << 8)
517 pub const mask: u32 = 1 << offset;
518 /// Read-only values (empty)
519 pub mod R {}
520 /// Write-only values (empty)
521 pub mod W {}
522 /// Read-write values (empty)
523 pub mod RW {}
524 }
525
526 /// ABRQ0
527 pub mod ABRQ0 {
528 /// Offset (7 bits)
529 pub const offset: u32 = 7;
530 /// Mask (1 bit: 1 << 7)
531 pub const mask: u32 = 1 << offset;
532 /// Read-only values (empty)
533 pub mod R {}
534 /// Write-only values (empty)
535 pub mod W {}
536 /// Read-write values (empty)
537 pub mod RW {}
538 }
539
540 /// TERR0
541 pub mod TERR0 {
542 /// Offset (3 bits)
543 pub const offset: u32 = 3;
544 /// Mask (1 bit: 1 << 3)
545 pub const mask: u32 = 1 << offset;
546 /// Read-only values (empty)
547 pub mod R {}
548 /// Write-only values (empty)
549 pub mod W {}
550 /// Read-write values (empty)
551 pub mod RW {}
552 }
553
554 /// ALST0
555 pub mod ALST0 {
556 /// Offset (2 bits)
557 pub const offset: u32 = 2;
558 /// Mask (1 bit: 1 << 2)
559 pub const mask: u32 = 1 << offset;
560 /// Read-only values (empty)
561 pub mod R {}
562 /// Write-only values (empty)
563 pub mod W {}
564 /// Read-write values (empty)
565 pub mod RW {}
566 }
567
568 /// TXOK0
569 pub mod TXOK0 {
570 /// Offset (1 bits)
571 pub const offset: u32 = 1;
572 /// Mask (1 bit: 1 << 1)
573 pub const mask: u32 = 1 << offset;
574 /// Read-only values (empty)
575 pub mod R {}
576 /// Write-only values (empty)
577 pub mod W {}
578 /// Read-write values (empty)
579 pub mod RW {}
580 }
581
582 /// RQCP0
583 pub mod RQCP0 {
584 /// Offset (0 bits)
585 pub const offset: u32 = 0;
586 /// Mask (1 bit: 1 << 0)
587 pub const mask: u32 = 1 << offset;
588 /// Read-only values (empty)
589 pub mod R {}
590 /// Write-only values (empty)
591 pub mod W {}
592 /// Read-write values (empty)
593 pub mod RW {}
594 }
595}
596
597/// receive FIFO %s register
598pub mod RF0R {
599
600 /// RFOM0
601 pub mod RFOM {
602 /// Offset (5 bits)
603 pub const offset: u32 = 5;
604 /// Mask (1 bit: 1 << 5)
605 pub const mask: u32 = 1 << offset;
606 /// Read-only values (empty)
607 pub mod R {}
608 /// Write-only values
609 pub mod W {
610
611 /// 0b1: Set by software to release the output mailbox of the FIFO
612 pub const Release: u32 = 0b1;
613 }
614 /// Read-write values (empty)
615 pub mod RW {}
616 }
617
618 /// FOVR0
619 pub mod FOVR {
620 /// Offset (4 bits)
621 pub const offset: u32 = 4;
622 /// Mask (1 bit: 1 << 4)
623 pub const mask: u32 = 1 << offset;
624 /// Read-only values
625 pub mod R {
626
627 /// 0b0: No FIFO x overrun
628 pub const NoOverrun: u32 = 0b0;
629
630 /// 0b1: FIFO x overrun
631 pub const Overrun: u32 = 0b1;
632 }
633 /// Write-only values
634 pub mod W {
635
636 /// 0b1: Clear flag
637 pub const Clear: u32 = 0b1;
638 }
639 /// Read-write values (empty)
640 pub mod RW {}
641 }
642
643 /// FULL0
644 pub mod FULL {
645 /// Offset (3 bits)
646 pub const offset: u32 = 3;
647 /// Mask (1 bit: 1 << 3)
648 pub const mask: u32 = 1 << offset;
649 /// Read-only values
650 pub mod R {
651
652 /// 0b0: FIFO x is not full
653 pub const NotFull: u32 = 0b0;
654
655 /// 0b1: FIFO x is full
656 pub const Full: u32 = 0b1;
657 }
658 pub use super::FOVR::W;
659 /// Read-write values (empty)
660 pub mod RW {}
661 }
662
663 /// FMP0
664 pub mod FMP {
665 /// Offset (0 bits)
666 pub const offset: u32 = 0;
667 /// Mask (2 bits: 0b11 << 0)
668 pub const mask: u32 = 0b11 << offset;
669 /// Read-only values (empty)
670 pub mod R {}
671 /// Write-only values (empty)
672 pub mod W {}
673 /// Read-write values (empty)
674 pub mod RW {}
675 }
676}
677
678/// receive FIFO %s register
679pub mod RF1R {
680 pub use super::RF0R::FMP;
681 pub use super::RF0R::FOVR;
682 pub use super::RF0R::FULL;
683 pub use super::RF0R::RFOM;
684}
685
686/// interrupt enable register
687pub mod IER {
688
689 /// SLKIE
690 pub mod SLKIE {
691 /// Offset (17 bits)
692 pub const offset: u32 = 17;
693 /// Mask (1 bit: 1 << 17)
694 pub const mask: u32 = 1 << offset;
695 /// Read-only values (empty)
696 pub mod R {}
697 /// Write-only values (empty)
698 pub mod W {}
699 /// Read-write values
700 pub mod RW {
701
702 /// 0b0: No interrupt when SLAKI bit is set
703 pub const Disabled: u32 = 0b0;
704
705 /// 0b1: Interrupt generated when SLAKI bit is set
706 pub const Enabled: u32 = 0b1;
707 }
708 }
709
710 /// WKUIE
711 pub mod WKUIE {
712 /// Offset (16 bits)
713 pub const offset: u32 = 16;
714 /// Mask (1 bit: 1 << 16)
715 pub const mask: u32 = 1 << offset;
716 /// Read-only values (empty)
717 pub mod R {}
718 /// Write-only values (empty)
719 pub mod W {}
720 /// Read-write values
721 pub mod RW {
722
723 /// 0b0: No interrupt when WKUI is set
724 pub const Disabled: u32 = 0b0;
725
726 /// 0b1: Interrupt generated when WKUI bit is set
727 pub const Enabled: u32 = 0b1;
728 }
729 }
730
731 /// ERRIE
732 pub mod ERRIE {
733 /// Offset (15 bits)
734 pub const offset: u32 = 15;
735 /// Mask (1 bit: 1 << 15)
736 pub const mask: u32 = 1 << offset;
737 /// Read-only values (empty)
738 pub mod R {}
739 /// Write-only values (empty)
740 pub mod W {}
741 /// Read-write values
742 pub mod RW {
743
744 /// 0b0: No interrupt will be generated when an error condition is pending in the CAN_ESR
745 pub const Disabled: u32 = 0b0;
746
747 /// 0b1: An interrupt will be generation when an error condition is pending in the CAN_ESR
748 pub const Enabled: u32 = 0b1;
749 }
750 }
751
752 /// LECIE
753 pub mod LECIE {
754 /// Offset (11 bits)
755 pub const offset: u32 = 11;
756 /// Mask (1 bit: 1 << 11)
757 pub const mask: u32 = 1 << offset;
758 /// Read-only values (empty)
759 pub mod R {}
760 /// Write-only values (empty)
761 pub mod W {}
762 /// Read-write values
763 pub mod RW {
764
765 /// 0b0: ERRI bit will not be set when the error code in LEC\[2:0\] is set by hardware on error detection
766 pub const Disabled: u32 = 0b0;
767
768 /// 0b1: ERRI bit will be set when the error code in LEC\[2:0\] is set by hardware on error detection
769 pub const Enabled: u32 = 0b1;
770 }
771 }
772
773 /// BOFIE
774 pub mod BOFIE {
775 /// Offset (10 bits)
776 pub const offset: u32 = 10;
777 /// Mask (1 bit: 1 << 10)
778 pub const mask: u32 = 1 << offset;
779 /// Read-only values (empty)
780 pub mod R {}
781 /// Write-only values (empty)
782 pub mod W {}
783 /// Read-write values
784 pub mod RW {
785
786 /// 0b0: ERRI bit will not be set when BOFF is set
787 pub const Disabled: u32 = 0b0;
788
789 /// 0b1: ERRI bit will be set when BOFF is set
790 pub const Enabled: u32 = 0b1;
791 }
792 }
793
794 /// EPVIE
795 pub mod EPVIE {
796 /// Offset (9 bits)
797 pub const offset: u32 = 9;
798 /// Mask (1 bit: 1 << 9)
799 pub const mask: u32 = 1 << offset;
800 /// Read-only values (empty)
801 pub mod R {}
802 /// Write-only values (empty)
803 pub mod W {}
804 /// Read-write values
805 pub mod RW {
806
807 /// 0b0: ERRI bit will not be set when EPVF is set
808 pub const Disabled: u32 = 0b0;
809
810 /// 0b1: ERRI bit will be set when EPVF is set
811 pub const Enabled: u32 = 0b1;
812 }
813 }
814
815 /// EWGIE
816 pub mod EWGIE {
817 /// Offset (8 bits)
818 pub const offset: u32 = 8;
819 /// Mask (1 bit: 1 << 8)
820 pub const mask: u32 = 1 << offset;
821 /// Read-only values (empty)
822 pub mod R {}
823 /// Write-only values (empty)
824 pub mod W {}
825 /// Read-write values
826 pub mod RW {
827
828 /// 0b0: ERRI bit will not be set when EWGF is set
829 pub const Disabled: u32 = 0b0;
830
831 /// 0b1: ERRI bit will be set when EWGF is set
832 pub const Enabled: u32 = 0b1;
833 }
834 }
835
836 /// FOVIE1
837 pub mod FOVIE1 {
838 /// Offset (6 bits)
839 pub const offset: u32 = 6;
840 /// Mask (1 bit: 1 << 6)
841 pub const mask: u32 = 1 << offset;
842 /// Read-only values (empty)
843 pub mod R {}
844 /// Write-only values (empty)
845 pub mod W {}
846 /// Read-write values
847 pub mod RW {
848
849 /// 0b0: No interrupt when FOVR is set
850 pub const Disabled: u32 = 0b0;
851
852 /// 0b1: Interrupt generation when FOVR is set
853 pub const Enabled: u32 = 0b1;
854 }
855 }
856
857 /// FFIE1
858 pub mod FFIE1 {
859 /// Offset (5 bits)
860 pub const offset: u32 = 5;
861 /// Mask (1 bit: 1 << 5)
862 pub const mask: u32 = 1 << offset;
863 /// Read-only values (empty)
864 pub mod R {}
865 /// Write-only values (empty)
866 pub mod W {}
867 /// Read-write values
868 pub mod RW {
869
870 /// 0b0: No interrupt when FULL bit is set
871 pub const Disabled: u32 = 0b0;
872
873 /// 0b1: Interrupt generated when FULL bit is set
874 pub const Enabled: u32 = 0b1;
875 }
876 }
877
878 /// FMPIE1
879 pub mod FMPIE1 {
880 /// Offset (4 bits)
881 pub const offset: u32 = 4;
882 /// Mask (1 bit: 1 << 4)
883 pub const mask: u32 = 1 << offset;
884 /// Read-only values (empty)
885 pub mod R {}
886 /// Write-only values (empty)
887 pub mod W {}
888 /// Read-write values
889 pub mod RW {
890
891 /// 0b0: No interrupt generated when state of FMP\[1:0\] bits are not 00b
892 pub const Disabled: u32 = 0b0;
893
894 /// 0b1: Interrupt generated when state of FMP\[1:0\] bits are not 00b
895 pub const Enabled: u32 = 0b1;
896 }
897 }
898
899 /// FOVIE0
900 pub mod FOVIE0 {
901 /// Offset (3 bits)
902 pub const offset: u32 = 3;
903 /// Mask (1 bit: 1 << 3)
904 pub const mask: u32 = 1 << offset;
905 /// Read-only values (empty)
906 pub mod R {}
907 /// Write-only values (empty)
908 pub mod W {}
909 /// Read-write values
910 pub mod RW {
911
912 /// 0b0: No interrupt when FOVR bit is set
913 pub const Disabled: u32 = 0b0;
914
915 /// 0b1: Interrupt generated when FOVR bit is set
916 pub const Enabled: u32 = 0b1;
917 }
918 }
919
920 /// FFIE0
921 pub mod FFIE0 {
922 /// Offset (2 bits)
923 pub const offset: u32 = 2;
924 /// Mask (1 bit: 1 << 2)
925 pub const mask: u32 = 1 << offset;
926 /// Read-only values (empty)
927 pub mod R {}
928 /// Write-only values (empty)
929 pub mod W {}
930 pub use super::FFIE1::RW;
931 }
932
933 /// FMPIE0
934 pub mod FMPIE0 {
935 /// Offset (1 bits)
936 pub const offset: u32 = 1;
937 /// Mask (1 bit: 1 << 1)
938 pub const mask: u32 = 1 << offset;
939 /// Read-only values (empty)
940 pub mod R {}
941 /// Write-only values (empty)
942 pub mod W {}
943 /// Read-write values
944 pub mod RW {
945
946 /// 0b0: No interrupt generated when state of FMP\[1:0\] bits are not 00
947 pub const Disabled: u32 = 0b0;
948
949 /// 0b1: Interrupt generated when state of FMP\[1:0\] bits are not 00b
950 pub const Enabled: u32 = 0b1;
951 }
952 }
953
954 /// TMEIE
955 pub mod TMEIE {
956 /// Offset (0 bits)
957 pub const offset: u32 = 0;
958 /// Mask (1 bit: 1 << 0)
959 pub const mask: u32 = 1 << offset;
960 /// Read-only values (empty)
961 pub mod R {}
962 /// Write-only values (empty)
963 pub mod W {}
964 /// Read-write values
965 pub mod RW {
966
967 /// 0b0: No interrupt when RQCPx bit is set
968 pub const Disabled: u32 = 0b0;
969
970 /// 0b1: Interrupt generated when RQCPx bit is set
971 pub const Enabled: u32 = 0b1;
972 }
973 }
974}
975
976/// interrupt enable register
977pub mod ESR {
978
979 /// REC
980 pub mod REC {
981 /// Offset (24 bits)
982 pub const offset: u32 = 24;
983 /// Mask (8 bits: 0xff << 24)
984 pub const mask: u32 = 0xff << offset;
985 /// Read-only values (empty)
986 pub mod R {}
987 /// Write-only values (empty)
988 pub mod W {}
989 /// Read-write values (empty)
990 pub mod RW {}
991 }
992
993 /// TEC
994 pub mod TEC {
995 /// Offset (16 bits)
996 pub const offset: u32 = 16;
997 /// Mask (8 bits: 0xff << 16)
998 pub const mask: u32 = 0xff << offset;
999 /// Read-only values (empty)
1000 pub mod R {}
1001 /// Write-only values (empty)
1002 pub mod W {}
1003 /// Read-write values (empty)
1004 pub mod RW {}
1005 }
1006
1007 /// LEC
1008 pub mod LEC {
1009 /// Offset (4 bits)
1010 pub const offset: u32 = 4;
1011 /// Mask (3 bits: 0b111 << 4)
1012 pub const mask: u32 = 0b111 << offset;
1013 /// Read-only values (empty)
1014 pub mod R {}
1015 /// Write-only values (empty)
1016 pub mod W {}
1017 /// Read-write values
1018 pub mod RW {
1019
1020 /// 0b000: No Error
1021 pub const NoError: u32 = 0b000;
1022
1023 /// 0b001: Stuff Error
1024 pub const Stuff: u32 = 0b001;
1025
1026 /// 0b010: Form Error
1027 pub const Form: u32 = 0b010;
1028
1029 /// 0b011: Acknowledgment Error
1030 pub const Ack: u32 = 0b011;
1031
1032 /// 0b100: Bit recessive Error
1033 pub const BitRecessive: u32 = 0b100;
1034
1035 /// 0b101: Bit dominant Error
1036 pub const BitDominant: u32 = 0b101;
1037
1038 /// 0b110: CRC Error
1039 pub const Crc: u32 = 0b110;
1040
1041 /// 0b111: Set by software
1042 pub const Custom: u32 = 0b111;
1043 }
1044 }
1045
1046 /// BOFF
1047 pub mod BOFF {
1048 /// Offset (2 bits)
1049 pub const offset: u32 = 2;
1050 /// Mask (1 bit: 1 << 2)
1051 pub const mask: u32 = 1 << offset;
1052 /// Read-only values (empty)
1053 pub mod R {}
1054 /// Write-only values (empty)
1055 pub mod W {}
1056 /// Read-write values (empty)
1057 pub mod RW {}
1058 }
1059
1060 /// EPVF
1061 pub mod EPVF {
1062 /// Offset (1 bits)
1063 pub const offset: u32 = 1;
1064 /// Mask (1 bit: 1 << 1)
1065 pub const mask: u32 = 1 << offset;
1066 /// Read-only values (empty)
1067 pub mod R {}
1068 /// Write-only values (empty)
1069 pub mod W {}
1070 /// Read-write values (empty)
1071 pub mod RW {}
1072 }
1073
1074 /// EWGF
1075 pub mod EWGF {
1076 /// Offset (0 bits)
1077 pub const offset: u32 = 0;
1078 /// Mask (1 bit: 1 << 0)
1079 pub const mask: u32 = 1 << offset;
1080 /// Read-only values (empty)
1081 pub mod R {}
1082 /// Write-only values (empty)
1083 pub mod W {}
1084 /// Read-write values (empty)
1085 pub mod RW {}
1086 }
1087}
1088
1089/// bit timing register
1090pub mod BTR {
1091
1092 /// SILM
1093 pub mod SILM {
1094 /// Offset (31 bits)
1095 pub const offset: u32 = 31;
1096 /// Mask (1 bit: 1 << 31)
1097 pub const mask: u32 = 1 << offset;
1098 /// Read-only values (empty)
1099 pub mod R {}
1100 /// Write-only values (empty)
1101 pub mod W {}
1102 /// Read-write values
1103 pub mod RW {
1104
1105 /// 0b0: Normal operation
1106 pub const Normal: u32 = 0b0;
1107
1108 /// 0b1: Silent Mode
1109 pub const Silent: u32 = 0b1;
1110 }
1111 }
1112
1113 /// LBKM
1114 pub mod LBKM {
1115 /// Offset (30 bits)
1116 pub const offset: u32 = 30;
1117 /// Mask (1 bit: 1 << 30)
1118 pub const mask: u32 = 1 << offset;
1119 /// Read-only values (empty)
1120 pub mod R {}
1121 /// Write-only values (empty)
1122 pub mod W {}
1123 /// Read-write values
1124 pub mod RW {
1125
1126 /// 0b0: Loop Back Mode disabled
1127 pub const Disabled: u32 = 0b0;
1128
1129 /// 0b1: Loop Back Mode enabled
1130 pub const Enabled: u32 = 0b1;
1131 }
1132 }
1133
1134 /// SJW
1135 pub mod SJW {
1136 /// Offset (24 bits)
1137 pub const offset: u32 = 24;
1138 /// Mask (2 bits: 0b11 << 24)
1139 pub const mask: u32 = 0b11 << offset;
1140 /// Read-only values (empty)
1141 pub mod R {}
1142 /// Write-only values (empty)
1143 pub mod W {}
1144 /// Read-write values (empty)
1145 pub mod RW {}
1146 }
1147
1148 /// TS2
1149 pub mod TS2 {
1150 /// Offset (20 bits)
1151 pub const offset: u32 = 20;
1152 /// Mask (3 bits: 0b111 << 20)
1153 pub const mask: u32 = 0b111 << offset;
1154 /// Read-only values (empty)
1155 pub mod R {}
1156 /// Write-only values (empty)
1157 pub mod W {}
1158 /// Read-write values (empty)
1159 pub mod RW {}
1160 }
1161
1162 /// TS1
1163 pub mod TS1 {
1164 /// Offset (16 bits)
1165 pub const offset: u32 = 16;
1166 /// Mask (4 bits: 0b1111 << 16)
1167 pub const mask: u32 = 0b1111 << offset;
1168 /// Read-only values (empty)
1169 pub mod R {}
1170 /// Write-only values (empty)
1171 pub mod W {}
1172 /// Read-write values (empty)
1173 pub mod RW {}
1174 }
1175
1176 /// BRP
1177 pub mod BRP {
1178 /// Offset (0 bits)
1179 pub const offset: u32 = 0;
1180 /// Mask (10 bits: 0x3ff << 0)
1181 pub const mask: u32 = 0x3ff << offset;
1182 /// Read-only values (empty)
1183 pub mod R {}
1184 /// Write-only values (empty)
1185 pub mod W {}
1186 /// Read-write values (empty)
1187 pub mod RW {}
1188 }
1189}
1190
1191/// filter master register
1192pub mod FMR {
1193
1194 /// CAN2SB
1195 pub mod CAN2SB {
1196 /// Offset (8 bits)
1197 pub const offset: u32 = 8;
1198 /// Mask (6 bits: 0x3f << 8)
1199 pub const mask: u32 = 0x3f << offset;
1200 /// Read-only values (empty)
1201 pub mod R {}
1202 /// Write-only values (empty)
1203 pub mod W {}
1204 /// Read-write values (empty)
1205 pub mod RW {}
1206 }
1207
1208 /// FINIT
1209 pub mod FINIT {
1210 /// Offset (0 bits)
1211 pub const offset: u32 = 0;
1212 /// Mask (1 bit: 1 << 0)
1213 pub const mask: u32 = 1 << offset;
1214 /// Read-only values (empty)
1215 pub mod R {}
1216 /// Write-only values (empty)
1217 pub mod W {}
1218 /// Read-write values (empty)
1219 pub mod RW {}
1220 }
1221}
1222
1223/// filter mode register
1224pub mod FM1R {
1225
1226 /// Filter mode
1227 pub mod FBM0 {
1228 /// Offset (0 bits)
1229 pub const offset: u32 = 0;
1230 /// Mask (1 bit: 1 << 0)
1231 pub const mask: u32 = 1 << offset;
1232 /// Read-only values (empty)
1233 pub mod R {}
1234 /// Write-only values (empty)
1235 pub mod W {}
1236 /// Read-write values (empty)
1237 pub mod RW {}
1238 }
1239
1240 /// Filter mode
1241 pub mod FBM1 {
1242 /// Offset (1 bits)
1243 pub const offset: u32 = 1;
1244 /// Mask (1 bit: 1 << 1)
1245 pub const mask: u32 = 1 << offset;
1246 /// Read-only values (empty)
1247 pub mod R {}
1248 /// Write-only values (empty)
1249 pub mod W {}
1250 /// Read-write values (empty)
1251 pub mod RW {}
1252 }
1253
1254 /// Filter mode
1255 pub mod FBM2 {
1256 /// Offset (2 bits)
1257 pub const offset: u32 = 2;
1258 /// Mask (1 bit: 1 << 2)
1259 pub const mask: u32 = 1 << offset;
1260 /// Read-only values (empty)
1261 pub mod R {}
1262 /// Write-only values (empty)
1263 pub mod W {}
1264 /// Read-write values (empty)
1265 pub mod RW {}
1266 }
1267
1268 /// Filter mode
1269 pub mod FBM3 {
1270 /// Offset (3 bits)
1271 pub const offset: u32 = 3;
1272 /// Mask (1 bit: 1 << 3)
1273 pub const mask: u32 = 1 << offset;
1274 /// Read-only values (empty)
1275 pub mod R {}
1276 /// Write-only values (empty)
1277 pub mod W {}
1278 /// Read-write values (empty)
1279 pub mod RW {}
1280 }
1281
1282 /// Filter mode
1283 pub mod FBM4 {
1284 /// Offset (4 bits)
1285 pub const offset: u32 = 4;
1286 /// Mask (1 bit: 1 << 4)
1287 pub const mask: u32 = 1 << offset;
1288 /// Read-only values (empty)
1289 pub mod R {}
1290 /// Write-only values (empty)
1291 pub mod W {}
1292 /// Read-write values (empty)
1293 pub mod RW {}
1294 }
1295
1296 /// Filter mode
1297 pub mod FBM5 {
1298 /// Offset (5 bits)
1299 pub const offset: u32 = 5;
1300 /// Mask (1 bit: 1 << 5)
1301 pub const mask: u32 = 1 << offset;
1302 /// Read-only values (empty)
1303 pub mod R {}
1304 /// Write-only values (empty)
1305 pub mod W {}
1306 /// Read-write values (empty)
1307 pub mod RW {}
1308 }
1309
1310 /// Filter mode
1311 pub mod FBM6 {
1312 /// Offset (6 bits)
1313 pub const offset: u32 = 6;
1314 /// Mask (1 bit: 1 << 6)
1315 pub const mask: u32 = 1 << offset;
1316 /// Read-only values (empty)
1317 pub mod R {}
1318 /// Write-only values (empty)
1319 pub mod W {}
1320 /// Read-write values (empty)
1321 pub mod RW {}
1322 }
1323
1324 /// Filter mode
1325 pub mod FBM7 {
1326 /// Offset (7 bits)
1327 pub const offset: u32 = 7;
1328 /// Mask (1 bit: 1 << 7)
1329 pub const mask: u32 = 1 << offset;
1330 /// Read-only values (empty)
1331 pub mod R {}
1332 /// Write-only values (empty)
1333 pub mod W {}
1334 /// Read-write values (empty)
1335 pub mod RW {}
1336 }
1337
1338 /// Filter mode
1339 pub mod FBM8 {
1340 /// Offset (8 bits)
1341 pub const offset: u32 = 8;
1342 /// Mask (1 bit: 1 << 8)
1343 pub const mask: u32 = 1 << offset;
1344 /// Read-only values (empty)
1345 pub mod R {}
1346 /// Write-only values (empty)
1347 pub mod W {}
1348 /// Read-write values (empty)
1349 pub mod RW {}
1350 }
1351
1352 /// Filter mode
1353 pub mod FBM9 {
1354 /// Offset (9 bits)
1355 pub const offset: u32 = 9;
1356 /// Mask (1 bit: 1 << 9)
1357 pub const mask: u32 = 1 << offset;
1358 /// Read-only values (empty)
1359 pub mod R {}
1360 /// Write-only values (empty)
1361 pub mod W {}
1362 /// Read-write values (empty)
1363 pub mod RW {}
1364 }
1365
1366 /// Filter mode
1367 pub mod FBM10 {
1368 /// Offset (10 bits)
1369 pub const offset: u32 = 10;
1370 /// Mask (1 bit: 1 << 10)
1371 pub const mask: u32 = 1 << offset;
1372 /// Read-only values (empty)
1373 pub mod R {}
1374 /// Write-only values (empty)
1375 pub mod W {}
1376 /// Read-write values (empty)
1377 pub mod RW {}
1378 }
1379
1380 /// Filter mode
1381 pub mod FBM11 {
1382 /// Offset (11 bits)
1383 pub const offset: u32 = 11;
1384 /// Mask (1 bit: 1 << 11)
1385 pub const mask: u32 = 1 << offset;
1386 /// Read-only values (empty)
1387 pub mod R {}
1388 /// Write-only values (empty)
1389 pub mod W {}
1390 /// Read-write values (empty)
1391 pub mod RW {}
1392 }
1393
1394 /// Filter mode
1395 pub mod FBM12 {
1396 /// Offset (12 bits)
1397 pub const offset: u32 = 12;
1398 /// Mask (1 bit: 1 << 12)
1399 pub const mask: u32 = 1 << offset;
1400 /// Read-only values (empty)
1401 pub mod R {}
1402 /// Write-only values (empty)
1403 pub mod W {}
1404 /// Read-write values (empty)
1405 pub mod RW {}
1406 }
1407
1408 /// Filter mode
1409 pub mod FBM13 {
1410 /// Offset (13 bits)
1411 pub const offset: u32 = 13;
1412 /// Mask (1 bit: 1 << 13)
1413 pub const mask: u32 = 1 << offset;
1414 /// Read-only values (empty)
1415 pub mod R {}
1416 /// Write-only values (empty)
1417 pub mod W {}
1418 /// Read-write values (empty)
1419 pub mod RW {}
1420 }
1421
1422 /// Filter mode
1423 pub mod FBM14 {
1424 /// Offset (14 bits)
1425 pub const offset: u32 = 14;
1426 /// Mask (1 bit: 1 << 14)
1427 pub const mask: u32 = 1 << offset;
1428 /// Read-only values (empty)
1429 pub mod R {}
1430 /// Write-only values (empty)
1431 pub mod W {}
1432 /// Read-write values (empty)
1433 pub mod RW {}
1434 }
1435
1436 /// Filter mode
1437 pub mod FBM15 {
1438 /// Offset (15 bits)
1439 pub const offset: u32 = 15;
1440 /// Mask (1 bit: 1 << 15)
1441 pub const mask: u32 = 1 << offset;
1442 /// Read-only values (empty)
1443 pub mod R {}
1444 /// Write-only values (empty)
1445 pub mod W {}
1446 /// Read-write values (empty)
1447 pub mod RW {}
1448 }
1449
1450 /// Filter mode
1451 pub mod FBM16 {
1452 /// Offset (16 bits)
1453 pub const offset: u32 = 16;
1454 /// Mask (1 bit: 1 << 16)
1455 pub const mask: u32 = 1 << offset;
1456 /// Read-only values (empty)
1457 pub mod R {}
1458 /// Write-only values (empty)
1459 pub mod W {}
1460 /// Read-write values (empty)
1461 pub mod RW {}
1462 }
1463
1464 /// Filter mode
1465 pub mod FBM17 {
1466 /// Offset (17 bits)
1467 pub const offset: u32 = 17;
1468 /// Mask (1 bit: 1 << 17)
1469 pub const mask: u32 = 1 << offset;
1470 /// Read-only values (empty)
1471 pub mod R {}
1472 /// Write-only values (empty)
1473 pub mod W {}
1474 /// Read-write values (empty)
1475 pub mod RW {}
1476 }
1477
1478 /// Filter mode
1479 pub mod FBM18 {
1480 /// Offset (18 bits)
1481 pub const offset: u32 = 18;
1482 /// Mask (1 bit: 1 << 18)
1483 pub const mask: u32 = 1 << offset;
1484 /// Read-only values (empty)
1485 pub mod R {}
1486 /// Write-only values (empty)
1487 pub mod W {}
1488 /// Read-write values (empty)
1489 pub mod RW {}
1490 }
1491
1492 /// Filter mode
1493 pub mod FBM19 {
1494 /// Offset (19 bits)
1495 pub const offset: u32 = 19;
1496 /// Mask (1 bit: 1 << 19)
1497 pub const mask: u32 = 1 << offset;
1498 /// Read-only values (empty)
1499 pub mod R {}
1500 /// Write-only values (empty)
1501 pub mod W {}
1502 /// Read-write values (empty)
1503 pub mod RW {}
1504 }
1505
1506 /// Filter mode
1507 pub mod FBM20 {
1508 /// Offset (20 bits)
1509 pub const offset: u32 = 20;
1510 /// Mask (1 bit: 1 << 20)
1511 pub const mask: u32 = 1 << offset;
1512 /// Read-only values (empty)
1513 pub mod R {}
1514 /// Write-only values (empty)
1515 pub mod W {}
1516 /// Read-write values (empty)
1517 pub mod RW {}
1518 }
1519
1520 /// Filter mode
1521 pub mod FBM21 {
1522 /// Offset (21 bits)
1523 pub const offset: u32 = 21;
1524 /// Mask (1 bit: 1 << 21)
1525 pub const mask: u32 = 1 << offset;
1526 /// Read-only values (empty)
1527 pub mod R {}
1528 /// Write-only values (empty)
1529 pub mod W {}
1530 /// Read-write values (empty)
1531 pub mod RW {}
1532 }
1533
1534 /// Filter mode
1535 pub mod FBM22 {
1536 /// Offset (22 bits)
1537 pub const offset: u32 = 22;
1538 /// Mask (1 bit: 1 << 22)
1539 pub const mask: u32 = 1 << offset;
1540 /// Read-only values (empty)
1541 pub mod R {}
1542 /// Write-only values (empty)
1543 pub mod W {}
1544 /// Read-write values (empty)
1545 pub mod RW {}
1546 }
1547
1548 /// Filter mode
1549 pub mod FBM23 {
1550 /// Offset (23 bits)
1551 pub const offset: u32 = 23;
1552 /// Mask (1 bit: 1 << 23)
1553 pub const mask: u32 = 1 << offset;
1554 /// Read-only values (empty)
1555 pub mod R {}
1556 /// Write-only values (empty)
1557 pub mod W {}
1558 /// Read-write values (empty)
1559 pub mod RW {}
1560 }
1561
1562 /// Filter mode
1563 pub mod FBM24 {
1564 /// Offset (24 bits)
1565 pub const offset: u32 = 24;
1566 /// Mask (1 bit: 1 << 24)
1567 pub const mask: u32 = 1 << offset;
1568 /// Read-only values (empty)
1569 pub mod R {}
1570 /// Write-only values (empty)
1571 pub mod W {}
1572 /// Read-write values (empty)
1573 pub mod RW {}
1574 }
1575
1576 /// Filter mode
1577 pub mod FBM25 {
1578 /// Offset (25 bits)
1579 pub const offset: u32 = 25;
1580 /// Mask (1 bit: 1 << 25)
1581 pub const mask: u32 = 1 << offset;
1582 /// Read-only values (empty)
1583 pub mod R {}
1584 /// Write-only values (empty)
1585 pub mod W {}
1586 /// Read-write values (empty)
1587 pub mod RW {}
1588 }
1589
1590 /// Filter mode
1591 pub mod FBM26 {
1592 /// Offset (26 bits)
1593 pub const offset: u32 = 26;
1594 /// Mask (1 bit: 1 << 26)
1595 pub const mask: u32 = 1 << offset;
1596 /// Read-only values (empty)
1597 pub mod R {}
1598 /// Write-only values (empty)
1599 pub mod W {}
1600 /// Read-write values (empty)
1601 pub mod RW {}
1602 }
1603
1604 /// Filter mode
1605 pub mod FBM27 {
1606 /// Offset (27 bits)
1607 pub const offset: u32 = 27;
1608 /// Mask (1 bit: 1 << 27)
1609 pub const mask: u32 = 1 << offset;
1610 /// Read-only values (empty)
1611 pub mod R {}
1612 /// Write-only values (empty)
1613 pub mod W {}
1614 /// Read-write values (empty)
1615 pub mod RW {}
1616 }
1617}
1618
1619/// filter scale register
1620pub mod FS1R {
1621
1622 /// Filter scale configuration
1623 pub mod FSC0 {
1624 /// Offset (0 bits)
1625 pub const offset: u32 = 0;
1626 /// Mask (1 bit: 1 << 0)
1627 pub const mask: u32 = 1 << offset;
1628 /// Read-only values (empty)
1629 pub mod R {}
1630 /// Write-only values (empty)
1631 pub mod W {}
1632 /// Read-write values (empty)
1633 pub mod RW {}
1634 }
1635
1636 /// Filter scale configuration
1637 pub mod FSC1 {
1638 /// Offset (1 bits)
1639 pub const offset: u32 = 1;
1640 /// Mask (1 bit: 1 << 1)
1641 pub const mask: u32 = 1 << offset;
1642 /// Read-only values (empty)
1643 pub mod R {}
1644 /// Write-only values (empty)
1645 pub mod W {}
1646 /// Read-write values (empty)
1647 pub mod RW {}
1648 }
1649
1650 /// Filter scale configuration
1651 pub mod FSC2 {
1652 /// Offset (2 bits)
1653 pub const offset: u32 = 2;
1654 /// Mask (1 bit: 1 << 2)
1655 pub const mask: u32 = 1 << offset;
1656 /// Read-only values (empty)
1657 pub mod R {}
1658 /// Write-only values (empty)
1659 pub mod W {}
1660 /// Read-write values (empty)
1661 pub mod RW {}
1662 }
1663
1664 /// Filter scale configuration
1665 pub mod FSC3 {
1666 /// Offset (3 bits)
1667 pub const offset: u32 = 3;
1668 /// Mask (1 bit: 1 << 3)
1669 pub const mask: u32 = 1 << offset;
1670 /// Read-only values (empty)
1671 pub mod R {}
1672 /// Write-only values (empty)
1673 pub mod W {}
1674 /// Read-write values (empty)
1675 pub mod RW {}
1676 }
1677
1678 /// Filter scale configuration
1679 pub mod FSC4 {
1680 /// Offset (4 bits)
1681 pub const offset: u32 = 4;
1682 /// Mask (1 bit: 1 << 4)
1683 pub const mask: u32 = 1 << offset;
1684 /// Read-only values (empty)
1685 pub mod R {}
1686 /// Write-only values (empty)
1687 pub mod W {}
1688 /// Read-write values (empty)
1689 pub mod RW {}
1690 }
1691
1692 /// Filter scale configuration
1693 pub mod FSC5 {
1694 /// Offset (5 bits)
1695 pub const offset: u32 = 5;
1696 /// Mask (1 bit: 1 << 5)
1697 pub const mask: u32 = 1 << offset;
1698 /// Read-only values (empty)
1699 pub mod R {}
1700 /// Write-only values (empty)
1701 pub mod W {}
1702 /// Read-write values (empty)
1703 pub mod RW {}
1704 }
1705
1706 /// Filter scale configuration
1707 pub mod FSC6 {
1708 /// Offset (6 bits)
1709 pub const offset: u32 = 6;
1710 /// Mask (1 bit: 1 << 6)
1711 pub const mask: u32 = 1 << offset;
1712 /// Read-only values (empty)
1713 pub mod R {}
1714 /// Write-only values (empty)
1715 pub mod W {}
1716 /// Read-write values (empty)
1717 pub mod RW {}
1718 }
1719
1720 /// Filter scale configuration
1721 pub mod FSC7 {
1722 /// Offset (7 bits)
1723 pub const offset: u32 = 7;
1724 /// Mask (1 bit: 1 << 7)
1725 pub const mask: u32 = 1 << offset;
1726 /// Read-only values (empty)
1727 pub mod R {}
1728 /// Write-only values (empty)
1729 pub mod W {}
1730 /// Read-write values (empty)
1731 pub mod RW {}
1732 }
1733
1734 /// Filter scale configuration
1735 pub mod FSC8 {
1736 /// Offset (8 bits)
1737 pub const offset: u32 = 8;
1738 /// Mask (1 bit: 1 << 8)
1739 pub const mask: u32 = 1 << offset;
1740 /// Read-only values (empty)
1741 pub mod R {}
1742 /// Write-only values (empty)
1743 pub mod W {}
1744 /// Read-write values (empty)
1745 pub mod RW {}
1746 }
1747
1748 /// Filter scale configuration
1749 pub mod FSC9 {
1750 /// Offset (9 bits)
1751 pub const offset: u32 = 9;
1752 /// Mask (1 bit: 1 << 9)
1753 pub const mask: u32 = 1 << offset;
1754 /// Read-only values (empty)
1755 pub mod R {}
1756 /// Write-only values (empty)
1757 pub mod W {}
1758 /// Read-write values (empty)
1759 pub mod RW {}
1760 }
1761
1762 /// Filter scale configuration
1763 pub mod FSC10 {
1764 /// Offset (10 bits)
1765 pub const offset: u32 = 10;
1766 /// Mask (1 bit: 1 << 10)
1767 pub const mask: u32 = 1 << offset;
1768 /// Read-only values (empty)
1769 pub mod R {}
1770 /// Write-only values (empty)
1771 pub mod W {}
1772 /// Read-write values (empty)
1773 pub mod RW {}
1774 }
1775
1776 /// Filter scale configuration
1777 pub mod FSC11 {
1778 /// Offset (11 bits)
1779 pub const offset: u32 = 11;
1780 /// Mask (1 bit: 1 << 11)
1781 pub const mask: u32 = 1 << offset;
1782 /// Read-only values (empty)
1783 pub mod R {}
1784 /// Write-only values (empty)
1785 pub mod W {}
1786 /// Read-write values (empty)
1787 pub mod RW {}
1788 }
1789
1790 /// Filter scale configuration
1791 pub mod FSC12 {
1792 /// Offset (12 bits)
1793 pub const offset: u32 = 12;
1794 /// Mask (1 bit: 1 << 12)
1795 pub const mask: u32 = 1 << offset;
1796 /// Read-only values (empty)
1797 pub mod R {}
1798 /// Write-only values (empty)
1799 pub mod W {}
1800 /// Read-write values (empty)
1801 pub mod RW {}
1802 }
1803
1804 /// Filter scale configuration
1805 pub mod FSC13 {
1806 /// Offset (13 bits)
1807 pub const offset: u32 = 13;
1808 /// Mask (1 bit: 1 << 13)
1809 pub const mask: u32 = 1 << offset;
1810 /// Read-only values (empty)
1811 pub mod R {}
1812 /// Write-only values (empty)
1813 pub mod W {}
1814 /// Read-write values (empty)
1815 pub mod RW {}
1816 }
1817
1818 /// Filter scale configuration
1819 pub mod FSC14 {
1820 /// Offset (14 bits)
1821 pub const offset: u32 = 14;
1822 /// Mask (1 bit: 1 << 14)
1823 pub const mask: u32 = 1 << offset;
1824 /// Read-only values (empty)
1825 pub mod R {}
1826 /// Write-only values (empty)
1827 pub mod W {}
1828 /// Read-write values (empty)
1829 pub mod RW {}
1830 }
1831
1832 /// Filter scale configuration
1833 pub mod FSC15 {
1834 /// Offset (15 bits)
1835 pub const offset: u32 = 15;
1836 /// Mask (1 bit: 1 << 15)
1837 pub const mask: u32 = 1 << offset;
1838 /// Read-only values (empty)
1839 pub mod R {}
1840 /// Write-only values (empty)
1841 pub mod W {}
1842 /// Read-write values (empty)
1843 pub mod RW {}
1844 }
1845
1846 /// Filter scale configuration
1847 pub mod FSC16 {
1848 /// Offset (16 bits)
1849 pub const offset: u32 = 16;
1850 /// Mask (1 bit: 1 << 16)
1851 pub const mask: u32 = 1 << offset;
1852 /// Read-only values (empty)
1853 pub mod R {}
1854 /// Write-only values (empty)
1855 pub mod W {}
1856 /// Read-write values (empty)
1857 pub mod RW {}
1858 }
1859
1860 /// Filter scale configuration
1861 pub mod FSC17 {
1862 /// Offset (17 bits)
1863 pub const offset: u32 = 17;
1864 /// Mask (1 bit: 1 << 17)
1865 pub const mask: u32 = 1 << offset;
1866 /// Read-only values (empty)
1867 pub mod R {}
1868 /// Write-only values (empty)
1869 pub mod W {}
1870 /// Read-write values (empty)
1871 pub mod RW {}
1872 }
1873
1874 /// Filter scale configuration
1875 pub mod FSC18 {
1876 /// Offset (18 bits)
1877 pub const offset: u32 = 18;
1878 /// Mask (1 bit: 1 << 18)
1879 pub const mask: u32 = 1 << offset;
1880 /// Read-only values (empty)
1881 pub mod R {}
1882 /// Write-only values (empty)
1883 pub mod W {}
1884 /// Read-write values (empty)
1885 pub mod RW {}
1886 }
1887
1888 /// Filter scale configuration
1889 pub mod FSC19 {
1890 /// Offset (19 bits)
1891 pub const offset: u32 = 19;
1892 /// Mask (1 bit: 1 << 19)
1893 pub const mask: u32 = 1 << offset;
1894 /// Read-only values (empty)
1895 pub mod R {}
1896 /// Write-only values (empty)
1897 pub mod W {}
1898 /// Read-write values (empty)
1899 pub mod RW {}
1900 }
1901
1902 /// Filter scale configuration
1903 pub mod FSC20 {
1904 /// Offset (20 bits)
1905 pub const offset: u32 = 20;
1906 /// Mask (1 bit: 1 << 20)
1907 pub const mask: u32 = 1 << offset;
1908 /// Read-only values (empty)
1909 pub mod R {}
1910 /// Write-only values (empty)
1911 pub mod W {}
1912 /// Read-write values (empty)
1913 pub mod RW {}
1914 }
1915
1916 /// Filter scale configuration
1917 pub mod FSC21 {
1918 /// Offset (21 bits)
1919 pub const offset: u32 = 21;
1920 /// Mask (1 bit: 1 << 21)
1921 pub const mask: u32 = 1 << offset;
1922 /// Read-only values (empty)
1923 pub mod R {}
1924 /// Write-only values (empty)
1925 pub mod W {}
1926 /// Read-write values (empty)
1927 pub mod RW {}
1928 }
1929
1930 /// Filter scale configuration
1931 pub mod FSC22 {
1932 /// Offset (22 bits)
1933 pub const offset: u32 = 22;
1934 /// Mask (1 bit: 1 << 22)
1935 pub const mask: u32 = 1 << offset;
1936 /// Read-only values (empty)
1937 pub mod R {}
1938 /// Write-only values (empty)
1939 pub mod W {}
1940 /// Read-write values (empty)
1941 pub mod RW {}
1942 }
1943
1944 /// Filter scale configuration
1945 pub mod FSC23 {
1946 /// Offset (23 bits)
1947 pub const offset: u32 = 23;
1948 /// Mask (1 bit: 1 << 23)
1949 pub const mask: u32 = 1 << offset;
1950 /// Read-only values (empty)
1951 pub mod R {}
1952 /// Write-only values (empty)
1953 pub mod W {}
1954 /// Read-write values (empty)
1955 pub mod RW {}
1956 }
1957
1958 /// Filter scale configuration
1959 pub mod FSC24 {
1960 /// Offset (24 bits)
1961 pub const offset: u32 = 24;
1962 /// Mask (1 bit: 1 << 24)
1963 pub const mask: u32 = 1 << offset;
1964 /// Read-only values (empty)
1965 pub mod R {}
1966 /// Write-only values (empty)
1967 pub mod W {}
1968 /// Read-write values (empty)
1969 pub mod RW {}
1970 }
1971
1972 /// Filter scale configuration
1973 pub mod FSC25 {
1974 /// Offset (25 bits)
1975 pub const offset: u32 = 25;
1976 /// Mask (1 bit: 1 << 25)
1977 pub const mask: u32 = 1 << offset;
1978 /// Read-only values (empty)
1979 pub mod R {}
1980 /// Write-only values (empty)
1981 pub mod W {}
1982 /// Read-write values (empty)
1983 pub mod RW {}
1984 }
1985
1986 /// Filter scale configuration
1987 pub mod FSC26 {
1988 /// Offset (26 bits)
1989 pub const offset: u32 = 26;
1990 /// Mask (1 bit: 1 << 26)
1991 pub const mask: u32 = 1 << offset;
1992 /// Read-only values (empty)
1993 pub mod R {}
1994 /// Write-only values (empty)
1995 pub mod W {}
1996 /// Read-write values (empty)
1997 pub mod RW {}
1998 }
1999
2000 /// Filter scale configuration
2001 pub mod FSC27 {
2002 /// Offset (27 bits)
2003 pub const offset: u32 = 27;
2004 /// Mask (1 bit: 1 << 27)
2005 pub const mask: u32 = 1 << offset;
2006 /// Read-only values (empty)
2007 pub mod R {}
2008 /// Write-only values (empty)
2009 pub mod W {}
2010 /// Read-write values (empty)
2011 pub mod RW {}
2012 }
2013}
2014
2015/// filter FIFO assignment register
2016pub mod FFA1R {
2017
2018 /// Filter FIFO assignment for filter 0
2019 pub mod FFA0 {
2020 /// Offset (0 bits)
2021 pub const offset: u32 = 0;
2022 /// Mask (1 bit: 1 << 0)
2023 pub const mask: u32 = 1 << offset;
2024 /// Read-only values (empty)
2025 pub mod R {}
2026 /// Write-only values (empty)
2027 pub mod W {}
2028 /// Read-write values (empty)
2029 pub mod RW {}
2030 }
2031
2032 /// Filter FIFO assignment for filter 1
2033 pub mod FFA1 {
2034 /// Offset (1 bits)
2035 pub const offset: u32 = 1;
2036 /// Mask (1 bit: 1 << 1)
2037 pub const mask: u32 = 1 << offset;
2038 /// Read-only values (empty)
2039 pub mod R {}
2040 /// Write-only values (empty)
2041 pub mod W {}
2042 /// Read-write values (empty)
2043 pub mod RW {}
2044 }
2045
2046 /// Filter FIFO assignment for filter 2
2047 pub mod FFA2 {
2048 /// Offset (2 bits)
2049 pub const offset: u32 = 2;
2050 /// Mask (1 bit: 1 << 2)
2051 pub const mask: u32 = 1 << offset;
2052 /// Read-only values (empty)
2053 pub mod R {}
2054 /// Write-only values (empty)
2055 pub mod W {}
2056 /// Read-write values (empty)
2057 pub mod RW {}
2058 }
2059
2060 /// Filter FIFO assignment for filter 3
2061 pub mod FFA3 {
2062 /// Offset (3 bits)
2063 pub const offset: u32 = 3;
2064 /// Mask (1 bit: 1 << 3)
2065 pub const mask: u32 = 1 << offset;
2066 /// Read-only values (empty)
2067 pub mod R {}
2068 /// Write-only values (empty)
2069 pub mod W {}
2070 /// Read-write values (empty)
2071 pub mod RW {}
2072 }
2073
2074 /// Filter FIFO assignment for filter 4
2075 pub mod FFA4 {
2076 /// Offset (4 bits)
2077 pub const offset: u32 = 4;
2078 /// Mask (1 bit: 1 << 4)
2079 pub const mask: u32 = 1 << offset;
2080 /// Read-only values (empty)
2081 pub mod R {}
2082 /// Write-only values (empty)
2083 pub mod W {}
2084 /// Read-write values (empty)
2085 pub mod RW {}
2086 }
2087
2088 /// Filter FIFO assignment for filter 5
2089 pub mod FFA5 {
2090 /// Offset (5 bits)
2091 pub const offset: u32 = 5;
2092 /// Mask (1 bit: 1 << 5)
2093 pub const mask: u32 = 1 << offset;
2094 /// Read-only values (empty)
2095 pub mod R {}
2096 /// Write-only values (empty)
2097 pub mod W {}
2098 /// Read-write values (empty)
2099 pub mod RW {}
2100 }
2101
2102 /// Filter FIFO assignment for filter 6
2103 pub mod FFA6 {
2104 /// Offset (6 bits)
2105 pub const offset: u32 = 6;
2106 /// Mask (1 bit: 1 << 6)
2107 pub const mask: u32 = 1 << offset;
2108 /// Read-only values (empty)
2109 pub mod R {}
2110 /// Write-only values (empty)
2111 pub mod W {}
2112 /// Read-write values (empty)
2113 pub mod RW {}
2114 }
2115
2116 /// Filter FIFO assignment for filter 7
2117 pub mod FFA7 {
2118 /// Offset (7 bits)
2119 pub const offset: u32 = 7;
2120 /// Mask (1 bit: 1 << 7)
2121 pub const mask: u32 = 1 << offset;
2122 /// Read-only values (empty)
2123 pub mod R {}
2124 /// Write-only values (empty)
2125 pub mod W {}
2126 /// Read-write values (empty)
2127 pub mod RW {}
2128 }
2129
2130 /// Filter FIFO assignment for filter 8
2131 pub mod FFA8 {
2132 /// Offset (8 bits)
2133 pub const offset: u32 = 8;
2134 /// Mask (1 bit: 1 << 8)
2135 pub const mask: u32 = 1 << offset;
2136 /// Read-only values (empty)
2137 pub mod R {}
2138 /// Write-only values (empty)
2139 pub mod W {}
2140 /// Read-write values (empty)
2141 pub mod RW {}
2142 }
2143
2144 /// Filter FIFO assignment for filter 9
2145 pub mod FFA9 {
2146 /// Offset (9 bits)
2147 pub const offset: u32 = 9;
2148 /// Mask (1 bit: 1 << 9)
2149 pub const mask: u32 = 1 << offset;
2150 /// Read-only values (empty)
2151 pub mod R {}
2152 /// Write-only values (empty)
2153 pub mod W {}
2154 /// Read-write values (empty)
2155 pub mod RW {}
2156 }
2157
2158 /// Filter FIFO assignment for filter 10
2159 pub mod FFA10 {
2160 /// Offset (10 bits)
2161 pub const offset: u32 = 10;
2162 /// Mask (1 bit: 1 << 10)
2163 pub const mask: u32 = 1 << offset;
2164 /// Read-only values (empty)
2165 pub mod R {}
2166 /// Write-only values (empty)
2167 pub mod W {}
2168 /// Read-write values (empty)
2169 pub mod RW {}
2170 }
2171
2172 /// Filter FIFO assignment for filter 11
2173 pub mod FFA11 {
2174 /// Offset (11 bits)
2175 pub const offset: u32 = 11;
2176 /// Mask (1 bit: 1 << 11)
2177 pub const mask: u32 = 1 << offset;
2178 /// Read-only values (empty)
2179 pub mod R {}
2180 /// Write-only values (empty)
2181 pub mod W {}
2182 /// Read-write values (empty)
2183 pub mod RW {}
2184 }
2185
2186 /// Filter FIFO assignment for filter 12
2187 pub mod FFA12 {
2188 /// Offset (12 bits)
2189 pub const offset: u32 = 12;
2190 /// Mask (1 bit: 1 << 12)
2191 pub const mask: u32 = 1 << offset;
2192 /// Read-only values (empty)
2193 pub mod R {}
2194 /// Write-only values (empty)
2195 pub mod W {}
2196 /// Read-write values (empty)
2197 pub mod RW {}
2198 }
2199
2200 /// Filter FIFO assignment for filter 13
2201 pub mod FFA13 {
2202 /// Offset (13 bits)
2203 pub const offset: u32 = 13;
2204 /// Mask (1 bit: 1 << 13)
2205 pub const mask: u32 = 1 << offset;
2206 /// Read-only values (empty)
2207 pub mod R {}
2208 /// Write-only values (empty)
2209 pub mod W {}
2210 /// Read-write values (empty)
2211 pub mod RW {}
2212 }
2213
2214 /// Filter FIFO assignment for filter 14
2215 pub mod FFA14 {
2216 /// Offset (14 bits)
2217 pub const offset: u32 = 14;
2218 /// Mask (1 bit: 1 << 14)
2219 pub const mask: u32 = 1 << offset;
2220 /// Read-only values (empty)
2221 pub mod R {}
2222 /// Write-only values (empty)
2223 pub mod W {}
2224 /// Read-write values (empty)
2225 pub mod RW {}
2226 }
2227
2228 /// Filter FIFO assignment for filter 15
2229 pub mod FFA15 {
2230 /// Offset (15 bits)
2231 pub const offset: u32 = 15;
2232 /// Mask (1 bit: 1 << 15)
2233 pub const mask: u32 = 1 << offset;
2234 /// Read-only values (empty)
2235 pub mod R {}
2236 /// Write-only values (empty)
2237 pub mod W {}
2238 /// Read-write values (empty)
2239 pub mod RW {}
2240 }
2241
2242 /// Filter FIFO assignment for filter 16
2243 pub mod FFA16 {
2244 /// Offset (16 bits)
2245 pub const offset: u32 = 16;
2246 /// Mask (1 bit: 1 << 16)
2247 pub const mask: u32 = 1 << offset;
2248 /// Read-only values (empty)
2249 pub mod R {}
2250 /// Write-only values (empty)
2251 pub mod W {}
2252 /// Read-write values (empty)
2253 pub mod RW {}
2254 }
2255
2256 /// Filter FIFO assignment for filter 17
2257 pub mod FFA17 {
2258 /// Offset (17 bits)
2259 pub const offset: u32 = 17;
2260 /// Mask (1 bit: 1 << 17)
2261 pub const mask: u32 = 1 << offset;
2262 /// Read-only values (empty)
2263 pub mod R {}
2264 /// Write-only values (empty)
2265 pub mod W {}
2266 /// Read-write values (empty)
2267 pub mod RW {}
2268 }
2269
2270 /// Filter FIFO assignment for filter 18
2271 pub mod FFA18 {
2272 /// Offset (18 bits)
2273 pub const offset: u32 = 18;
2274 /// Mask (1 bit: 1 << 18)
2275 pub const mask: u32 = 1 << offset;
2276 /// Read-only values (empty)
2277 pub mod R {}
2278 /// Write-only values (empty)
2279 pub mod W {}
2280 /// Read-write values (empty)
2281 pub mod RW {}
2282 }
2283
2284 /// Filter FIFO assignment for filter 19
2285 pub mod FFA19 {
2286 /// Offset (19 bits)
2287 pub const offset: u32 = 19;
2288 /// Mask (1 bit: 1 << 19)
2289 pub const mask: u32 = 1 << offset;
2290 /// Read-only values (empty)
2291 pub mod R {}
2292 /// Write-only values (empty)
2293 pub mod W {}
2294 /// Read-write values (empty)
2295 pub mod RW {}
2296 }
2297
2298 /// Filter FIFO assignment for filter 20
2299 pub mod FFA20 {
2300 /// Offset (20 bits)
2301 pub const offset: u32 = 20;
2302 /// Mask (1 bit: 1 << 20)
2303 pub const mask: u32 = 1 << offset;
2304 /// Read-only values (empty)
2305 pub mod R {}
2306 /// Write-only values (empty)
2307 pub mod W {}
2308 /// Read-write values (empty)
2309 pub mod RW {}
2310 }
2311
2312 /// Filter FIFO assignment for filter 21
2313 pub mod FFA21 {
2314 /// Offset (21 bits)
2315 pub const offset: u32 = 21;
2316 /// Mask (1 bit: 1 << 21)
2317 pub const mask: u32 = 1 << offset;
2318 /// Read-only values (empty)
2319 pub mod R {}
2320 /// Write-only values (empty)
2321 pub mod W {}
2322 /// Read-write values (empty)
2323 pub mod RW {}
2324 }
2325
2326 /// Filter FIFO assignment for filter 22
2327 pub mod FFA22 {
2328 /// Offset (22 bits)
2329 pub const offset: u32 = 22;
2330 /// Mask (1 bit: 1 << 22)
2331 pub const mask: u32 = 1 << offset;
2332 /// Read-only values (empty)
2333 pub mod R {}
2334 /// Write-only values (empty)
2335 pub mod W {}
2336 /// Read-write values (empty)
2337 pub mod RW {}
2338 }
2339
2340 /// Filter FIFO assignment for filter 23
2341 pub mod FFA23 {
2342 /// Offset (23 bits)
2343 pub const offset: u32 = 23;
2344 /// Mask (1 bit: 1 << 23)
2345 pub const mask: u32 = 1 << offset;
2346 /// Read-only values (empty)
2347 pub mod R {}
2348 /// Write-only values (empty)
2349 pub mod W {}
2350 /// Read-write values (empty)
2351 pub mod RW {}
2352 }
2353
2354 /// Filter FIFO assignment for filter 24
2355 pub mod FFA24 {
2356 /// Offset (24 bits)
2357 pub const offset: u32 = 24;
2358 /// Mask (1 bit: 1 << 24)
2359 pub const mask: u32 = 1 << offset;
2360 /// Read-only values (empty)
2361 pub mod R {}
2362 /// Write-only values (empty)
2363 pub mod W {}
2364 /// Read-write values (empty)
2365 pub mod RW {}
2366 }
2367
2368 /// Filter FIFO assignment for filter 25
2369 pub mod FFA25 {
2370 /// Offset (25 bits)
2371 pub const offset: u32 = 25;
2372 /// Mask (1 bit: 1 << 25)
2373 pub const mask: u32 = 1 << offset;
2374 /// Read-only values (empty)
2375 pub mod R {}
2376 /// Write-only values (empty)
2377 pub mod W {}
2378 /// Read-write values (empty)
2379 pub mod RW {}
2380 }
2381
2382 /// Filter FIFO assignment for filter 26
2383 pub mod FFA26 {
2384 /// Offset (26 bits)
2385 pub const offset: u32 = 26;
2386 /// Mask (1 bit: 1 << 26)
2387 pub const mask: u32 = 1 << offset;
2388 /// Read-only values (empty)
2389 pub mod R {}
2390 /// Write-only values (empty)
2391 pub mod W {}
2392 /// Read-write values (empty)
2393 pub mod RW {}
2394 }
2395
2396 /// Filter FIFO assignment for filter 27
2397 pub mod FFA27 {
2398 /// Offset (27 bits)
2399 pub const offset: u32 = 27;
2400 /// Mask (1 bit: 1 << 27)
2401 pub const mask: u32 = 1 << offset;
2402 /// Read-only values (empty)
2403 pub mod R {}
2404 /// Write-only values (empty)
2405 pub mod W {}
2406 /// Read-write values (empty)
2407 pub mod RW {}
2408 }
2409}
2410
2411/// filter activation register
2412pub mod FA1R {
2413
2414 /// Filter active
2415 pub mod FACT0 {
2416 /// Offset (0 bits)
2417 pub const offset: u32 = 0;
2418 /// Mask (1 bit: 1 << 0)
2419 pub const mask: u32 = 1 << offset;
2420 /// Read-only values (empty)
2421 pub mod R {}
2422 /// Write-only values (empty)
2423 pub mod W {}
2424 /// Read-write values (empty)
2425 pub mod RW {}
2426 }
2427
2428 /// Filter active
2429 pub mod FACT1 {
2430 /// Offset (1 bits)
2431 pub const offset: u32 = 1;
2432 /// Mask (1 bit: 1 << 1)
2433 pub const mask: u32 = 1 << offset;
2434 /// Read-only values (empty)
2435 pub mod R {}
2436 /// Write-only values (empty)
2437 pub mod W {}
2438 /// Read-write values (empty)
2439 pub mod RW {}
2440 }
2441
2442 /// Filter active
2443 pub mod FACT2 {
2444 /// Offset (2 bits)
2445 pub const offset: u32 = 2;
2446 /// Mask (1 bit: 1 << 2)
2447 pub const mask: u32 = 1 << offset;
2448 /// Read-only values (empty)
2449 pub mod R {}
2450 /// Write-only values (empty)
2451 pub mod W {}
2452 /// Read-write values (empty)
2453 pub mod RW {}
2454 }
2455
2456 /// Filter active
2457 pub mod FACT3 {
2458 /// Offset (3 bits)
2459 pub const offset: u32 = 3;
2460 /// Mask (1 bit: 1 << 3)
2461 pub const mask: u32 = 1 << offset;
2462 /// Read-only values (empty)
2463 pub mod R {}
2464 /// Write-only values (empty)
2465 pub mod W {}
2466 /// Read-write values (empty)
2467 pub mod RW {}
2468 }
2469
2470 /// Filter active
2471 pub mod FACT4 {
2472 /// Offset (4 bits)
2473 pub const offset: u32 = 4;
2474 /// Mask (1 bit: 1 << 4)
2475 pub const mask: u32 = 1 << offset;
2476 /// Read-only values (empty)
2477 pub mod R {}
2478 /// Write-only values (empty)
2479 pub mod W {}
2480 /// Read-write values (empty)
2481 pub mod RW {}
2482 }
2483
2484 /// Filter active
2485 pub mod FACT5 {
2486 /// Offset (5 bits)
2487 pub const offset: u32 = 5;
2488 /// Mask (1 bit: 1 << 5)
2489 pub const mask: u32 = 1 << offset;
2490 /// Read-only values (empty)
2491 pub mod R {}
2492 /// Write-only values (empty)
2493 pub mod W {}
2494 /// Read-write values (empty)
2495 pub mod RW {}
2496 }
2497
2498 /// Filter active
2499 pub mod FACT6 {
2500 /// Offset (6 bits)
2501 pub const offset: u32 = 6;
2502 /// Mask (1 bit: 1 << 6)
2503 pub const mask: u32 = 1 << offset;
2504 /// Read-only values (empty)
2505 pub mod R {}
2506 /// Write-only values (empty)
2507 pub mod W {}
2508 /// Read-write values (empty)
2509 pub mod RW {}
2510 }
2511
2512 /// Filter active
2513 pub mod FACT7 {
2514 /// Offset (7 bits)
2515 pub const offset: u32 = 7;
2516 /// Mask (1 bit: 1 << 7)
2517 pub const mask: u32 = 1 << offset;
2518 /// Read-only values (empty)
2519 pub mod R {}
2520 /// Write-only values (empty)
2521 pub mod W {}
2522 /// Read-write values (empty)
2523 pub mod RW {}
2524 }
2525
2526 /// Filter active
2527 pub mod FACT8 {
2528 /// Offset (8 bits)
2529 pub const offset: u32 = 8;
2530 /// Mask (1 bit: 1 << 8)
2531 pub const mask: u32 = 1 << offset;
2532 /// Read-only values (empty)
2533 pub mod R {}
2534 /// Write-only values (empty)
2535 pub mod W {}
2536 /// Read-write values (empty)
2537 pub mod RW {}
2538 }
2539
2540 /// Filter active
2541 pub mod FACT9 {
2542 /// Offset (9 bits)
2543 pub const offset: u32 = 9;
2544 /// Mask (1 bit: 1 << 9)
2545 pub const mask: u32 = 1 << offset;
2546 /// Read-only values (empty)
2547 pub mod R {}
2548 /// Write-only values (empty)
2549 pub mod W {}
2550 /// Read-write values (empty)
2551 pub mod RW {}
2552 }
2553
2554 /// Filter active
2555 pub mod FACT10 {
2556 /// Offset (10 bits)
2557 pub const offset: u32 = 10;
2558 /// Mask (1 bit: 1 << 10)
2559 pub const mask: u32 = 1 << offset;
2560 /// Read-only values (empty)
2561 pub mod R {}
2562 /// Write-only values (empty)
2563 pub mod W {}
2564 /// Read-write values (empty)
2565 pub mod RW {}
2566 }
2567
2568 /// Filter active
2569 pub mod FACT11 {
2570 /// Offset (11 bits)
2571 pub const offset: u32 = 11;
2572 /// Mask (1 bit: 1 << 11)
2573 pub const mask: u32 = 1 << offset;
2574 /// Read-only values (empty)
2575 pub mod R {}
2576 /// Write-only values (empty)
2577 pub mod W {}
2578 /// Read-write values (empty)
2579 pub mod RW {}
2580 }
2581
2582 /// Filter active
2583 pub mod FACT12 {
2584 /// Offset (12 bits)
2585 pub const offset: u32 = 12;
2586 /// Mask (1 bit: 1 << 12)
2587 pub const mask: u32 = 1 << offset;
2588 /// Read-only values (empty)
2589 pub mod R {}
2590 /// Write-only values (empty)
2591 pub mod W {}
2592 /// Read-write values (empty)
2593 pub mod RW {}
2594 }
2595
2596 /// Filter active
2597 pub mod FACT13 {
2598 /// Offset (13 bits)
2599 pub const offset: u32 = 13;
2600 /// Mask (1 bit: 1 << 13)
2601 pub const mask: u32 = 1 << offset;
2602 /// Read-only values (empty)
2603 pub mod R {}
2604 /// Write-only values (empty)
2605 pub mod W {}
2606 /// Read-write values (empty)
2607 pub mod RW {}
2608 }
2609
2610 /// Filter active
2611 pub mod FACT14 {
2612 /// Offset (14 bits)
2613 pub const offset: u32 = 14;
2614 /// Mask (1 bit: 1 << 14)
2615 pub const mask: u32 = 1 << offset;
2616 /// Read-only values (empty)
2617 pub mod R {}
2618 /// Write-only values (empty)
2619 pub mod W {}
2620 /// Read-write values (empty)
2621 pub mod RW {}
2622 }
2623
2624 /// Filter active
2625 pub mod FACT15 {
2626 /// Offset (15 bits)
2627 pub const offset: u32 = 15;
2628 /// Mask (1 bit: 1 << 15)
2629 pub const mask: u32 = 1 << offset;
2630 /// Read-only values (empty)
2631 pub mod R {}
2632 /// Write-only values (empty)
2633 pub mod W {}
2634 /// Read-write values (empty)
2635 pub mod RW {}
2636 }
2637
2638 /// Filter active
2639 pub mod FACT16 {
2640 /// Offset (16 bits)
2641 pub const offset: u32 = 16;
2642 /// Mask (1 bit: 1 << 16)
2643 pub const mask: u32 = 1 << offset;
2644 /// Read-only values (empty)
2645 pub mod R {}
2646 /// Write-only values (empty)
2647 pub mod W {}
2648 /// Read-write values (empty)
2649 pub mod RW {}
2650 }
2651
2652 /// Filter active
2653 pub mod FACT17 {
2654 /// Offset (17 bits)
2655 pub const offset: u32 = 17;
2656 /// Mask (1 bit: 1 << 17)
2657 pub const mask: u32 = 1 << offset;
2658 /// Read-only values (empty)
2659 pub mod R {}
2660 /// Write-only values (empty)
2661 pub mod W {}
2662 /// Read-write values (empty)
2663 pub mod RW {}
2664 }
2665
2666 /// Filter active
2667 pub mod FACT18 {
2668 /// Offset (18 bits)
2669 pub const offset: u32 = 18;
2670 /// Mask (1 bit: 1 << 18)
2671 pub const mask: u32 = 1 << offset;
2672 /// Read-only values (empty)
2673 pub mod R {}
2674 /// Write-only values (empty)
2675 pub mod W {}
2676 /// Read-write values (empty)
2677 pub mod RW {}
2678 }
2679
2680 /// Filter active
2681 pub mod FACT19 {
2682 /// Offset (19 bits)
2683 pub const offset: u32 = 19;
2684 /// Mask (1 bit: 1 << 19)
2685 pub const mask: u32 = 1 << offset;
2686 /// Read-only values (empty)
2687 pub mod R {}
2688 /// Write-only values (empty)
2689 pub mod W {}
2690 /// Read-write values (empty)
2691 pub mod RW {}
2692 }
2693
2694 /// Filter active
2695 pub mod FACT20 {
2696 /// Offset (20 bits)
2697 pub const offset: u32 = 20;
2698 /// Mask (1 bit: 1 << 20)
2699 pub const mask: u32 = 1 << offset;
2700 /// Read-only values (empty)
2701 pub mod R {}
2702 /// Write-only values (empty)
2703 pub mod W {}
2704 /// Read-write values (empty)
2705 pub mod RW {}
2706 }
2707
2708 /// Filter active
2709 pub mod FACT21 {
2710 /// Offset (21 bits)
2711 pub const offset: u32 = 21;
2712 /// Mask (1 bit: 1 << 21)
2713 pub const mask: u32 = 1 << offset;
2714 /// Read-only values (empty)
2715 pub mod R {}
2716 /// Write-only values (empty)
2717 pub mod W {}
2718 /// Read-write values (empty)
2719 pub mod RW {}
2720 }
2721
2722 /// Filter active
2723 pub mod FACT22 {
2724 /// Offset (22 bits)
2725 pub const offset: u32 = 22;
2726 /// Mask (1 bit: 1 << 22)
2727 pub const mask: u32 = 1 << offset;
2728 /// Read-only values (empty)
2729 pub mod R {}
2730 /// Write-only values (empty)
2731 pub mod W {}
2732 /// Read-write values (empty)
2733 pub mod RW {}
2734 }
2735
2736 /// Filter active
2737 pub mod FACT23 {
2738 /// Offset (23 bits)
2739 pub const offset: u32 = 23;
2740 /// Mask (1 bit: 1 << 23)
2741 pub const mask: u32 = 1 << offset;
2742 /// Read-only values (empty)
2743 pub mod R {}
2744 /// Write-only values (empty)
2745 pub mod W {}
2746 /// Read-write values (empty)
2747 pub mod RW {}
2748 }
2749
2750 /// Filter active
2751 pub mod FACT24 {
2752 /// Offset (24 bits)
2753 pub const offset: u32 = 24;
2754 /// Mask (1 bit: 1 << 24)
2755 pub const mask: u32 = 1 << offset;
2756 /// Read-only values (empty)
2757 pub mod R {}
2758 /// Write-only values (empty)
2759 pub mod W {}
2760 /// Read-write values (empty)
2761 pub mod RW {}
2762 }
2763
2764 /// Filter active
2765 pub mod FACT25 {
2766 /// Offset (25 bits)
2767 pub const offset: u32 = 25;
2768 /// Mask (1 bit: 1 << 25)
2769 pub const mask: u32 = 1 << offset;
2770 /// Read-only values (empty)
2771 pub mod R {}
2772 /// Write-only values (empty)
2773 pub mod W {}
2774 /// Read-write values (empty)
2775 pub mod RW {}
2776 }
2777
2778 /// Filter active
2779 pub mod FACT26 {
2780 /// Offset (26 bits)
2781 pub const offset: u32 = 26;
2782 /// Mask (1 bit: 1 << 26)
2783 pub const mask: u32 = 1 << offset;
2784 /// Read-only values (empty)
2785 pub mod R {}
2786 /// Write-only values (empty)
2787 pub mod W {}
2788 /// Read-write values (empty)
2789 pub mod RW {}
2790 }
2791
2792 /// Filter active
2793 pub mod FACT27 {
2794 /// Offset (27 bits)
2795 pub const offset: u32 = 27;
2796 /// Mask (1 bit: 1 << 27)
2797 pub const mask: u32 = 1 << offset;
2798 /// Read-only values (empty)
2799 pub mod R {}
2800 /// Write-only values (empty)
2801 pub mod W {}
2802 /// Read-write values (empty)
2803 pub mod RW {}
2804 }
2805}
2806
2807/// TX mailbox identifier register
2808pub mod TIR0 {
2809
2810 /// STID
2811 pub mod STID {
2812 /// Offset (21 bits)
2813 pub const offset: u32 = 21;
2814 /// Mask (11 bits: 0x7ff << 21)
2815 pub const mask: u32 = 0x7ff << offset;
2816 /// Read-only values (empty)
2817 pub mod R {}
2818 /// Write-only values (empty)
2819 pub mod W {}
2820 /// Read-write values (empty)
2821 pub mod RW {}
2822 }
2823
2824 /// EXID
2825 pub mod EXID {
2826 /// Offset (3 bits)
2827 pub const offset: u32 = 3;
2828 /// Mask (18 bits: 0x3ffff << 3)
2829 pub const mask: u32 = 0x3ffff << offset;
2830 /// Read-only values (empty)
2831 pub mod R {}
2832 /// Write-only values (empty)
2833 pub mod W {}
2834 /// Read-write values (empty)
2835 pub mod RW {}
2836 }
2837
2838 /// IDE
2839 pub mod IDE {
2840 /// Offset (2 bits)
2841 pub const offset: u32 = 2;
2842 /// Mask (1 bit: 1 << 2)
2843 pub const mask: u32 = 1 << offset;
2844 /// Read-only values (empty)
2845 pub mod R {}
2846 /// Write-only values (empty)
2847 pub mod W {}
2848 /// Read-write values
2849 pub mod RW {
2850
2851 /// 0b0: Standard identifier
2852 pub const Standard: u32 = 0b0;
2853
2854 /// 0b1: Extended identifier
2855 pub const Extended: u32 = 0b1;
2856 }
2857 }
2858
2859 /// RTR
2860 pub mod RTR {
2861 /// Offset (1 bits)
2862 pub const offset: u32 = 1;
2863 /// Mask (1 bit: 1 << 1)
2864 pub const mask: u32 = 1 << offset;
2865 /// Read-only values (empty)
2866 pub mod R {}
2867 /// Write-only values (empty)
2868 pub mod W {}
2869 /// Read-write values
2870 pub mod RW {
2871
2872 /// 0b0: Data frame
2873 pub const Data: u32 = 0b0;
2874
2875 /// 0b1: Remote frame
2876 pub const Remote: u32 = 0b1;
2877 }
2878 }
2879
2880 /// TXRQ
2881 pub mod TXRQ {
2882 /// Offset (0 bits)
2883 pub const offset: u32 = 0;
2884 /// Mask (1 bit: 1 << 0)
2885 pub const mask: u32 = 1 << offset;
2886 /// Read-only values (empty)
2887 pub mod R {}
2888 /// Write-only values (empty)
2889 pub mod W {}
2890 /// Read-write values (empty)
2891 pub mod RW {}
2892 }
2893}
2894
2895/// mailbox data length control and time stamp register
2896pub mod TDTR0 {
2897
2898 /// TIME
2899 pub mod TIME {
2900 /// Offset (16 bits)
2901 pub const offset: u32 = 16;
2902 /// Mask (16 bits: 0xffff << 16)
2903 pub const mask: u32 = 0xffff << offset;
2904 /// Read-only values (empty)
2905 pub mod R {}
2906 /// Write-only values (empty)
2907 pub mod W {}
2908 /// Read-write values (empty)
2909 pub mod RW {}
2910 }
2911
2912 /// TGT
2913 pub mod TGT {
2914 /// Offset (8 bits)
2915 pub const offset: u32 = 8;
2916 /// Mask (1 bit: 1 << 8)
2917 pub const mask: u32 = 1 << offset;
2918 /// Read-only values (empty)
2919 pub mod R {}
2920 /// Write-only values (empty)
2921 pub mod W {}
2922 /// Read-write values (empty)
2923 pub mod RW {}
2924 }
2925
2926 /// DLC
2927 pub mod DLC {
2928 /// Offset (0 bits)
2929 pub const offset: u32 = 0;
2930 /// Mask (4 bits: 0b1111 << 0)
2931 pub const mask: u32 = 0b1111 << offset;
2932 /// Read-only values (empty)
2933 pub mod R {}
2934 /// Write-only values (empty)
2935 pub mod W {}
2936 /// Read-write values (empty)
2937 pub mod RW {}
2938 }
2939}
2940
2941/// mailbox data low register
2942pub mod TDLR0 {
2943
2944 /// DATA3
2945 pub mod DATA3 {
2946 /// Offset (24 bits)
2947 pub const offset: u32 = 24;
2948 /// Mask (8 bits: 0xff << 24)
2949 pub const mask: u32 = 0xff << offset;
2950 /// Read-only values (empty)
2951 pub mod R {}
2952 /// Write-only values (empty)
2953 pub mod W {}
2954 /// Read-write values (empty)
2955 pub mod RW {}
2956 }
2957
2958 /// DATA2
2959 pub mod DATA2 {
2960 /// Offset (16 bits)
2961 pub const offset: u32 = 16;
2962 /// Mask (8 bits: 0xff << 16)
2963 pub const mask: u32 = 0xff << offset;
2964 /// Read-only values (empty)
2965 pub mod R {}
2966 /// Write-only values (empty)
2967 pub mod W {}
2968 /// Read-write values (empty)
2969 pub mod RW {}
2970 }
2971
2972 /// DATA1
2973 pub mod DATA1 {
2974 /// Offset (8 bits)
2975 pub const offset: u32 = 8;
2976 /// Mask (8 bits: 0xff << 8)
2977 pub const mask: u32 = 0xff << offset;
2978 /// Read-only values (empty)
2979 pub mod R {}
2980 /// Write-only values (empty)
2981 pub mod W {}
2982 /// Read-write values (empty)
2983 pub mod RW {}
2984 }
2985
2986 /// DATA0
2987 pub mod DATA0 {
2988 /// Offset (0 bits)
2989 pub const offset: u32 = 0;
2990 /// Mask (8 bits: 0xff << 0)
2991 pub const mask: u32 = 0xff << offset;
2992 /// Read-only values (empty)
2993 pub mod R {}
2994 /// Write-only values (empty)
2995 pub mod W {}
2996 /// Read-write values (empty)
2997 pub mod RW {}
2998 }
2999}
3000
3001/// mailbox data high register
3002pub mod TDHR0 {
3003
3004 /// DATA7
3005 pub mod DATA7 {
3006 /// Offset (24 bits)
3007 pub const offset: u32 = 24;
3008 /// Mask (8 bits: 0xff << 24)
3009 pub const mask: u32 = 0xff << offset;
3010 /// Read-only values (empty)
3011 pub mod R {}
3012 /// Write-only values (empty)
3013 pub mod W {}
3014 /// Read-write values (empty)
3015 pub mod RW {}
3016 }
3017
3018 /// DATA6
3019 pub mod DATA6 {
3020 /// Offset (16 bits)
3021 pub const offset: u32 = 16;
3022 /// Mask (8 bits: 0xff << 16)
3023 pub const mask: u32 = 0xff << offset;
3024 /// Read-only values (empty)
3025 pub mod R {}
3026 /// Write-only values (empty)
3027 pub mod W {}
3028 /// Read-write values (empty)
3029 pub mod RW {}
3030 }
3031
3032 /// DATA5
3033 pub mod DATA5 {
3034 /// Offset (8 bits)
3035 pub const offset: u32 = 8;
3036 /// Mask (8 bits: 0xff << 8)
3037 pub const mask: u32 = 0xff << offset;
3038 /// Read-only values (empty)
3039 pub mod R {}
3040 /// Write-only values (empty)
3041 pub mod W {}
3042 /// Read-write values (empty)
3043 pub mod RW {}
3044 }
3045
3046 /// DATA4
3047 pub mod DATA4 {
3048 /// Offset (0 bits)
3049 pub const offset: u32 = 0;
3050 /// Mask (8 bits: 0xff << 0)
3051 pub const mask: u32 = 0xff << offset;
3052 /// Read-only values (empty)
3053 pub mod R {}
3054 /// Write-only values (empty)
3055 pub mod W {}
3056 /// Read-write values (empty)
3057 pub mod RW {}
3058 }
3059}
3060
3061/// TX mailbox identifier register
3062pub mod TIR1 {
3063 pub use super::TIR0::EXID;
3064 pub use super::TIR0::IDE;
3065 pub use super::TIR0::RTR;
3066 pub use super::TIR0::STID;
3067 pub use super::TIR0::TXRQ;
3068}
3069
3070/// mailbox data length control and time stamp register
3071pub mod TDTR1 {
3072 pub use super::TDTR0::DLC;
3073 pub use super::TDTR0::TGT;
3074 pub use super::TDTR0::TIME;
3075}
3076
3077/// mailbox data low register
3078pub mod TDLR1 {
3079 pub use super::TDLR0::DATA0;
3080 pub use super::TDLR0::DATA1;
3081 pub use super::TDLR0::DATA2;
3082 pub use super::TDLR0::DATA3;
3083}
3084
3085/// mailbox data high register
3086pub mod TDHR1 {
3087 pub use super::TDHR0::DATA4;
3088 pub use super::TDHR0::DATA5;
3089 pub use super::TDHR0::DATA6;
3090 pub use super::TDHR0::DATA7;
3091}
3092
3093/// TX mailbox identifier register
3094pub mod TIR2 {
3095 pub use super::TIR0::EXID;
3096 pub use super::TIR0::IDE;
3097 pub use super::TIR0::RTR;
3098 pub use super::TIR0::STID;
3099 pub use super::TIR0::TXRQ;
3100}
3101
3102/// mailbox data length control and time stamp register
3103pub mod TDTR2 {
3104 pub use super::TDTR0::DLC;
3105 pub use super::TDTR0::TGT;
3106 pub use super::TDTR0::TIME;
3107}
3108
3109/// mailbox data low register
3110pub mod TDLR2 {
3111 pub use super::TDLR0::DATA0;
3112 pub use super::TDLR0::DATA1;
3113 pub use super::TDLR0::DATA2;
3114 pub use super::TDLR0::DATA3;
3115}
3116
3117/// mailbox data high register
3118pub mod TDHR2 {
3119 pub use super::TDHR0::DATA4;
3120 pub use super::TDHR0::DATA5;
3121 pub use super::TDHR0::DATA6;
3122 pub use super::TDHR0::DATA7;
3123}
3124
3125/// receive FIFO mailbox identifier register
3126pub mod RIR0 {
3127
3128 /// STID
3129 pub mod STID {
3130 /// Offset (21 bits)
3131 pub const offset: u32 = 21;
3132 /// Mask (11 bits: 0x7ff << 21)
3133 pub const mask: u32 = 0x7ff << offset;
3134 /// Read-only values (empty)
3135 pub mod R {}
3136 /// Write-only values (empty)
3137 pub mod W {}
3138 /// Read-write values (empty)
3139 pub mod RW {}
3140 }
3141
3142 /// EXID
3143 pub mod EXID {
3144 /// Offset (3 bits)
3145 pub const offset: u32 = 3;
3146 /// Mask (18 bits: 0x3ffff << 3)
3147 pub const mask: u32 = 0x3ffff << offset;
3148 /// Read-only values (empty)
3149 pub mod R {}
3150 /// Write-only values (empty)
3151 pub mod W {}
3152 /// Read-write values (empty)
3153 pub mod RW {}
3154 }
3155
3156 /// IDE
3157 pub mod IDE {
3158 /// Offset (2 bits)
3159 pub const offset: u32 = 2;
3160 /// Mask (1 bit: 1 << 2)
3161 pub const mask: u32 = 1 << offset;
3162 /// Read-only values
3163 pub mod R {
3164
3165 /// 0b0: Standard identifier
3166 pub const Standard: u32 = 0b0;
3167
3168 /// 0b1: Extended identifier
3169 pub const Extended: u32 = 0b1;
3170 }
3171 /// Write-only values (empty)
3172 pub mod W {}
3173 /// Read-write values (empty)
3174 pub mod RW {}
3175 }
3176
3177 /// RTR
3178 pub mod RTR {
3179 /// Offset (1 bits)
3180 pub const offset: u32 = 1;
3181 /// Mask (1 bit: 1 << 1)
3182 pub const mask: u32 = 1 << offset;
3183 /// Read-only values
3184 pub mod R {
3185
3186 /// 0b0: Data frame
3187 pub const Data: u32 = 0b0;
3188
3189 /// 0b1: Remote frame
3190 pub const Remote: u32 = 0b1;
3191 }
3192 /// Write-only values (empty)
3193 pub mod W {}
3194 /// Read-write values (empty)
3195 pub mod RW {}
3196 }
3197}
3198
3199/// mailbox data high register
3200pub mod RDTR0 {
3201
3202 /// TIME
3203 pub mod TIME {
3204 /// Offset (16 bits)
3205 pub const offset: u32 = 16;
3206 /// Mask (16 bits: 0xffff << 16)
3207 pub const mask: u32 = 0xffff << offset;
3208 /// Read-only values (empty)
3209 pub mod R {}
3210 /// Write-only values (empty)
3211 pub mod W {}
3212 /// Read-write values (empty)
3213 pub mod RW {}
3214 }
3215
3216 /// FMI
3217 pub mod FMI {
3218 /// Offset (8 bits)
3219 pub const offset: u32 = 8;
3220 /// Mask (8 bits: 0xff << 8)
3221 pub const mask: u32 = 0xff << offset;
3222 /// Read-only values (empty)
3223 pub mod R {}
3224 /// Write-only values (empty)
3225 pub mod W {}
3226 /// Read-write values (empty)
3227 pub mod RW {}
3228 }
3229
3230 /// DLC
3231 pub mod DLC {
3232 /// Offset (0 bits)
3233 pub const offset: u32 = 0;
3234 /// Mask (4 bits: 0b1111 << 0)
3235 pub const mask: u32 = 0b1111 << offset;
3236 /// Read-only values (empty)
3237 pub mod R {}
3238 /// Write-only values (empty)
3239 pub mod W {}
3240 /// Read-write values (empty)
3241 pub mod RW {}
3242 }
3243}
3244
3245/// mailbox data high register
3246pub mod RDLR0 {
3247
3248 /// DATA3
3249 pub mod DATA3 {
3250 /// Offset (24 bits)
3251 pub const offset: u32 = 24;
3252 /// Mask (8 bits: 0xff << 24)
3253 pub const mask: u32 = 0xff << offset;
3254 /// Read-only values (empty)
3255 pub mod R {}
3256 /// Write-only values (empty)
3257 pub mod W {}
3258 /// Read-write values (empty)
3259 pub mod RW {}
3260 }
3261
3262 /// DATA2
3263 pub mod DATA2 {
3264 /// Offset (16 bits)
3265 pub const offset: u32 = 16;
3266 /// Mask (8 bits: 0xff << 16)
3267 pub const mask: u32 = 0xff << offset;
3268 /// Read-only values (empty)
3269 pub mod R {}
3270 /// Write-only values (empty)
3271 pub mod W {}
3272 /// Read-write values (empty)
3273 pub mod RW {}
3274 }
3275
3276 /// DATA1
3277 pub mod DATA1 {
3278 /// Offset (8 bits)
3279 pub const offset: u32 = 8;
3280 /// Mask (8 bits: 0xff << 8)
3281 pub const mask: u32 = 0xff << offset;
3282 /// Read-only values (empty)
3283 pub mod R {}
3284 /// Write-only values (empty)
3285 pub mod W {}
3286 /// Read-write values (empty)
3287 pub mod RW {}
3288 }
3289
3290 /// DATA0
3291 pub mod DATA0 {
3292 /// Offset (0 bits)
3293 pub const offset: u32 = 0;
3294 /// Mask (8 bits: 0xff << 0)
3295 pub const mask: u32 = 0xff << offset;
3296 /// Read-only values (empty)
3297 pub mod R {}
3298 /// Write-only values (empty)
3299 pub mod W {}
3300 /// Read-write values (empty)
3301 pub mod RW {}
3302 }
3303}
3304
3305/// receive FIFO mailbox data high register
3306pub mod RDHR0 {
3307
3308 /// DATA7
3309 pub mod DATA7 {
3310 /// Offset (24 bits)
3311 pub const offset: u32 = 24;
3312 /// Mask (8 bits: 0xff << 24)
3313 pub const mask: u32 = 0xff << offset;
3314 /// Read-only values (empty)
3315 pub mod R {}
3316 /// Write-only values (empty)
3317 pub mod W {}
3318 /// Read-write values (empty)
3319 pub mod RW {}
3320 }
3321
3322 /// DATA6
3323 pub mod DATA6 {
3324 /// Offset (16 bits)
3325 pub const offset: u32 = 16;
3326 /// Mask (8 bits: 0xff << 16)
3327 pub const mask: u32 = 0xff << offset;
3328 /// Read-only values (empty)
3329 pub mod R {}
3330 /// Write-only values (empty)
3331 pub mod W {}
3332 /// Read-write values (empty)
3333 pub mod RW {}
3334 }
3335
3336 /// DATA5
3337 pub mod DATA5 {
3338 /// Offset (8 bits)
3339 pub const offset: u32 = 8;
3340 /// Mask (8 bits: 0xff << 8)
3341 pub const mask: u32 = 0xff << offset;
3342 /// Read-only values (empty)
3343 pub mod R {}
3344 /// Write-only values (empty)
3345 pub mod W {}
3346 /// Read-write values (empty)
3347 pub mod RW {}
3348 }
3349
3350 /// DATA4
3351 pub mod DATA4 {
3352 /// Offset (0 bits)
3353 pub const offset: u32 = 0;
3354 /// Mask (8 bits: 0xff << 0)
3355 pub const mask: u32 = 0xff << offset;
3356 /// Read-only values (empty)
3357 pub mod R {}
3358 /// Write-only values (empty)
3359 pub mod W {}
3360 /// Read-write values (empty)
3361 pub mod RW {}
3362 }
3363}
3364
3365/// receive FIFO mailbox identifier register
3366pub mod RIR1 {
3367 pub use super::RIR0::EXID;
3368 pub use super::RIR0::IDE;
3369 pub use super::RIR0::RTR;
3370 pub use super::RIR0::STID;
3371}
3372
3373/// mailbox data high register
3374pub mod RDTR1 {
3375 pub use super::RDTR0::DLC;
3376 pub use super::RDTR0::FMI;
3377 pub use super::RDTR0::TIME;
3378}
3379
3380/// mailbox data high register
3381pub mod RDLR1 {
3382 pub use super::RDLR0::DATA0;
3383 pub use super::RDLR0::DATA1;
3384 pub use super::RDLR0::DATA2;
3385 pub use super::RDLR0::DATA3;
3386}
3387
3388/// receive FIFO mailbox data high register
3389pub mod RDHR1 {
3390 pub use super::RDHR0::DATA4;
3391 pub use super::RDHR0::DATA5;
3392 pub use super::RDHR0::DATA6;
3393 pub use super::RDHR0::DATA7;
3394}
3395
3396/// Filter bank 0 register 1
3397pub mod FR10 {
3398
3399 /// Filter bits
3400 pub mod FB {
3401 /// Offset (0 bits)
3402 pub const offset: u32 = 0;
3403 /// Mask (32 bits: 0xffffffff << 0)
3404 pub const mask: u32 = 0xffffffff << offset;
3405 /// Read-only values (empty)
3406 pub mod R {}
3407 /// Write-only values (empty)
3408 pub mod W {}
3409 /// Read-write values (empty)
3410 pub mod RW {}
3411 }
3412}
3413
3414/// Filter bank 0 register 2
3415pub mod FR20 {
3416 pub use super::FR10::FB;
3417}
3418
3419/// Filter bank 0 register 1
3420pub mod FR11 {
3421 pub use super::FR10::FB;
3422}
3423
3424/// Filter bank 0 register 2
3425pub mod FR21 {
3426 pub use super::FR10::FB;
3427}
3428
3429/// Filter bank 0 register 1
3430pub mod FR12 {
3431 pub use super::FR10::FB;
3432}
3433
3434/// Filter bank 0 register 2
3435pub mod FR22 {
3436 pub use super::FR10::FB;
3437}
3438
3439/// Filter bank 0 register 1
3440pub mod FR13 {
3441 pub use super::FR10::FB;
3442}
3443
3444/// Filter bank 0 register 2
3445pub mod FR23 {
3446 pub use super::FR10::FB;
3447}
3448
3449/// Filter bank 0 register 1
3450pub mod FR14 {
3451 pub use super::FR10::FB;
3452}
3453
3454/// Filter bank 0 register 2
3455pub mod FR24 {
3456 pub use super::FR10::FB;
3457}
3458
3459/// Filter bank 0 register 1
3460pub mod FR15 {
3461 pub use super::FR10::FB;
3462}
3463
3464/// Filter bank 0 register 2
3465pub mod FR25 {
3466 pub use super::FR10::FB;
3467}
3468
3469/// Filter bank 0 register 1
3470pub mod FR16 {
3471 pub use super::FR10::FB;
3472}
3473
3474/// Filter bank 0 register 2
3475pub mod FR26 {
3476 pub use super::FR10::FB;
3477}
3478
3479/// Filter bank 0 register 1
3480pub mod FR17 {
3481 pub use super::FR10::FB;
3482}
3483
3484/// Filter bank 0 register 2
3485pub mod FR27 {
3486 pub use super::FR10::FB;
3487}
3488
3489/// Filter bank 0 register 1
3490pub mod FR18 {
3491 pub use super::FR10::FB;
3492}
3493
3494/// Filter bank 0 register 2
3495pub mod FR28 {
3496 pub use super::FR10::FB;
3497}
3498
3499/// Filter bank 0 register 1
3500pub mod FR19 {
3501 pub use super::FR10::FB;
3502}
3503
3504/// Filter bank 0 register 2
3505pub mod FR29 {
3506 pub use super::FR10::FB;
3507}
3508
3509/// Filter bank 0 register 1
3510pub mod FR110 {
3511 pub use super::FR10::FB;
3512}
3513
3514/// Filter bank 0 register 2
3515pub mod FR210 {
3516 pub use super::FR10::FB;
3517}
3518
3519/// Filter bank 0 register 1
3520pub mod FR111 {
3521 pub use super::FR10::FB;
3522}
3523
3524/// Filter bank 0 register 2
3525pub mod FR211 {
3526 pub use super::FR10::FB;
3527}
3528
3529/// Filter bank 0 register 1
3530pub mod FR112 {
3531 pub use super::FR10::FB;
3532}
3533
3534/// Filter bank 0 register 2
3535pub mod FR212 {
3536 pub use super::FR10::FB;
3537}
3538
3539/// Filter bank 0 register 1
3540pub mod FR113 {
3541 pub use super::FR10::FB;
3542}
3543
3544/// Filter bank 0 register 2
3545pub mod FR213 {
3546 pub use super::FR10::FB;
3547}
3548
3549/// Filter bank 0 register 1
3550pub mod FR114 {
3551 pub use super::FR10::FB;
3552}
3553
3554/// Filter bank 0 register 2
3555pub mod FR214 {
3556 pub use super::FR10::FB;
3557}
3558
3559/// Filter bank 0 register 1
3560pub mod FR115 {
3561 pub use super::FR10::FB;
3562}
3563
3564/// Filter bank 0 register 2
3565pub mod FR215 {
3566 pub use super::FR10::FB;
3567}
3568
3569/// Filter bank 0 register 1
3570pub mod FR116 {
3571 pub use super::FR10::FB;
3572}
3573
3574/// Filter bank 0 register 2
3575pub mod FR216 {
3576 pub use super::FR10::FB;
3577}
3578
3579/// Filter bank 0 register 1
3580pub mod FR117 {
3581 pub use super::FR10::FB;
3582}
3583
3584/// Filter bank 0 register 2
3585pub mod FR217 {
3586 pub use super::FR10::FB;
3587}
3588
3589/// Filter bank 0 register 1
3590pub mod FR118 {
3591 pub use super::FR10::FB;
3592}
3593
3594/// Filter bank 0 register 2
3595pub mod FR218 {
3596 pub use super::FR10::FB;
3597}
3598
3599/// Filter bank 0 register 1
3600pub mod FR119 {
3601 pub use super::FR10::FB;
3602}
3603
3604/// Filter bank 0 register 2
3605pub mod FR219 {
3606 pub use super::FR10::FB;
3607}
3608
3609/// Filter bank 0 register 1
3610pub mod FR120 {
3611 pub use super::FR10::FB;
3612}
3613
3614/// Filter bank 0 register 2
3615pub mod FR220 {
3616 pub use super::FR10::FB;
3617}
3618
3619/// Filter bank 0 register 1
3620pub mod FR121 {
3621 pub use super::FR10::FB;
3622}
3623
3624/// Filter bank 0 register 2
3625pub mod FR221 {
3626 pub use super::FR10::FB;
3627}
3628
3629/// Filter bank 0 register 1
3630pub mod FR122 {
3631 pub use super::FR10::FB;
3632}
3633
3634/// Filter bank 0 register 2
3635pub mod FR222 {
3636 pub use super::FR10::FB;
3637}
3638
3639/// Filter bank 0 register 1
3640pub mod FR123 {
3641 pub use super::FR10::FB;
3642}
3643
3644/// Filter bank 0 register 2
3645pub mod FR223 {
3646 pub use super::FR10::FB;
3647}
3648
3649/// Filter bank 0 register 1
3650pub mod FR124 {
3651 pub use super::FR10::FB;
3652}
3653
3654/// Filter bank 0 register 2
3655pub mod FR224 {
3656 pub use super::FR10::FB;
3657}
3658
3659/// Filter bank 0 register 1
3660pub mod FR125 {
3661 pub use super::FR10::FB;
3662}
3663
3664/// Filter bank 0 register 2
3665pub mod FR225 {
3666 pub use super::FR10::FB;
3667}
3668
3669/// Filter bank 0 register 1
3670pub mod FR126 {
3671 pub use super::FR10::FB;
3672}
3673
3674/// Filter bank 0 register 2
3675pub mod FR226 {
3676 pub use super::FR10::FB;
3677}
3678
3679/// Filter bank 0 register 1
3680pub mod FR127 {
3681 pub use super::FR10::FB;
3682}
3683
3684/// Filter bank 0 register 2
3685pub mod FR227 {
3686 pub use super::FR10::FB;
3687}
3688#[repr(C)]
3689pub struct RegisterBlock {
3690 /// master control register
3691 pub MCR: RWRegister<u32>,
3692
3693 /// master status register
3694 pub MSR: RWRegister<u32>,
3695
3696 /// transmit status register
3697 pub TSR: RWRegister<u32>,
3698
3699 /// receive FIFO %s register
3700 pub RF0R: RWRegister<u32>,
3701
3702 /// receive FIFO %s register
3703 pub RF1R: RWRegister<u32>,
3704
3705 /// interrupt enable register
3706 pub IER: RWRegister<u32>,
3707
3708 /// interrupt enable register
3709 pub ESR: RWRegister<u32>,
3710
3711 /// bit timing register
3712 pub BTR: RWRegister<u32>,
3713
3714 _reserved1: [u8; 352],
3715
3716 /// TX mailbox identifier register
3717 pub TIR0: RWRegister<u32>,
3718
3719 /// mailbox data length control and time stamp register
3720 pub TDTR0: RWRegister<u32>,
3721
3722 /// mailbox data low register
3723 pub TDLR0: RWRegister<u32>,
3724
3725 /// mailbox data high register
3726 pub TDHR0: RWRegister<u32>,
3727
3728 /// TX mailbox identifier register
3729 pub TIR1: RWRegister<u32>,
3730
3731 /// mailbox data length control and time stamp register
3732 pub TDTR1: RWRegister<u32>,
3733
3734 /// mailbox data low register
3735 pub TDLR1: RWRegister<u32>,
3736
3737 /// mailbox data high register
3738 pub TDHR1: RWRegister<u32>,
3739
3740 /// TX mailbox identifier register
3741 pub TIR2: RWRegister<u32>,
3742
3743 /// mailbox data length control and time stamp register
3744 pub TDTR2: RWRegister<u32>,
3745
3746 /// mailbox data low register
3747 pub TDLR2: RWRegister<u32>,
3748
3749 /// mailbox data high register
3750 pub TDHR2: RWRegister<u32>,
3751
3752 /// receive FIFO mailbox identifier register
3753 pub RIR0: RORegister<u32>,
3754
3755 /// mailbox data high register
3756 pub RDTR0: RORegister<u32>,
3757
3758 /// mailbox data high register
3759 pub RDLR0: RORegister<u32>,
3760
3761 /// receive FIFO mailbox data high register
3762 pub RDHR0: RORegister<u32>,
3763
3764 /// receive FIFO mailbox identifier register
3765 pub RIR1: RORegister<u32>,
3766
3767 /// mailbox data high register
3768 pub RDTR1: RORegister<u32>,
3769
3770 /// mailbox data high register
3771 pub RDLR1: RORegister<u32>,
3772
3773 /// receive FIFO mailbox data high register
3774 pub RDHR1: RORegister<u32>,
3775
3776 _reserved2: [u8; 48],
3777
3778 /// filter master register
3779 pub FMR: RWRegister<u32>,
3780
3781 /// filter mode register
3782 pub FM1R: RWRegister<u32>,
3783
3784 _reserved3: [u8; 4],
3785
3786 /// filter scale register
3787 pub FS1R: RWRegister<u32>,
3788
3789 _reserved4: [u8; 4],
3790
3791 /// filter FIFO assignment register
3792 pub FFA1R: RWRegister<u32>,
3793
3794 _reserved5: [u8; 4],
3795
3796 /// filter activation register
3797 pub FA1R: RWRegister<u32>,
3798
3799 _reserved6: [u8; 32],
3800
3801 /// Filter bank 0 register 1
3802 pub FR10: RWRegister<u32>,
3803
3804 /// Filter bank 0 register 2
3805 pub FR20: RWRegister<u32>,
3806
3807 /// Filter bank 0 register 1
3808 pub FR11: RWRegister<u32>,
3809
3810 /// Filter bank 0 register 2
3811 pub FR21: RWRegister<u32>,
3812
3813 /// Filter bank 0 register 1
3814 pub FR12: RWRegister<u32>,
3815
3816 /// Filter bank 0 register 2
3817 pub FR22: RWRegister<u32>,
3818
3819 /// Filter bank 0 register 1
3820 pub FR13: RWRegister<u32>,
3821
3822 /// Filter bank 0 register 2
3823 pub FR23: RWRegister<u32>,
3824
3825 /// Filter bank 0 register 1
3826 pub FR14: RWRegister<u32>,
3827
3828 /// Filter bank 0 register 2
3829 pub FR24: RWRegister<u32>,
3830
3831 /// Filter bank 0 register 1
3832 pub FR15: RWRegister<u32>,
3833
3834 /// Filter bank 0 register 2
3835 pub FR25: RWRegister<u32>,
3836
3837 /// Filter bank 0 register 1
3838 pub FR16: RWRegister<u32>,
3839
3840 /// Filter bank 0 register 2
3841 pub FR26: RWRegister<u32>,
3842
3843 /// Filter bank 0 register 1
3844 pub FR17: RWRegister<u32>,
3845
3846 /// Filter bank 0 register 2
3847 pub FR27: RWRegister<u32>,
3848
3849 /// Filter bank 0 register 1
3850 pub FR18: RWRegister<u32>,
3851
3852 /// Filter bank 0 register 2
3853 pub FR28: RWRegister<u32>,
3854
3855 /// Filter bank 0 register 1
3856 pub FR19: RWRegister<u32>,
3857
3858 /// Filter bank 0 register 2
3859 pub FR29: RWRegister<u32>,
3860
3861 /// Filter bank 0 register 1
3862 pub FR110: RWRegister<u32>,
3863
3864 /// Filter bank 0 register 2
3865 pub FR210: RWRegister<u32>,
3866
3867 /// Filter bank 0 register 1
3868 pub FR111: RWRegister<u32>,
3869
3870 /// Filter bank 0 register 2
3871 pub FR211: RWRegister<u32>,
3872
3873 /// Filter bank 0 register 1
3874 pub FR112: RWRegister<u32>,
3875
3876 /// Filter bank 0 register 2
3877 pub FR212: RWRegister<u32>,
3878
3879 /// Filter bank 0 register 1
3880 pub FR113: RWRegister<u32>,
3881
3882 /// Filter bank 0 register 2
3883 pub FR213: RWRegister<u32>,
3884
3885 /// Filter bank 0 register 1
3886 pub FR114: RWRegister<u32>,
3887
3888 /// Filter bank 0 register 2
3889 pub FR214: RWRegister<u32>,
3890
3891 /// Filter bank 0 register 1
3892 pub FR115: RWRegister<u32>,
3893
3894 /// Filter bank 0 register 2
3895 pub FR215: RWRegister<u32>,
3896
3897 /// Filter bank 0 register 1
3898 pub FR116: RWRegister<u32>,
3899
3900 /// Filter bank 0 register 2
3901 pub FR216: RWRegister<u32>,
3902
3903 /// Filter bank 0 register 1
3904 pub FR117: RWRegister<u32>,
3905
3906 /// Filter bank 0 register 2
3907 pub FR217: RWRegister<u32>,
3908
3909 /// Filter bank 0 register 1
3910 pub FR118: RWRegister<u32>,
3911
3912 /// Filter bank 0 register 2
3913 pub FR218: RWRegister<u32>,
3914
3915 /// Filter bank 0 register 1
3916 pub FR119: RWRegister<u32>,
3917
3918 /// Filter bank 0 register 2
3919 pub FR219: RWRegister<u32>,
3920
3921 /// Filter bank 0 register 1
3922 pub FR120: RWRegister<u32>,
3923
3924 /// Filter bank 0 register 2
3925 pub FR220: RWRegister<u32>,
3926
3927 /// Filter bank 0 register 1
3928 pub FR121: RWRegister<u32>,
3929
3930 /// Filter bank 0 register 2
3931 pub FR221: RWRegister<u32>,
3932
3933 /// Filter bank 0 register 1
3934 pub FR122: RWRegister<u32>,
3935
3936 /// Filter bank 0 register 2
3937 pub FR222: RWRegister<u32>,
3938
3939 /// Filter bank 0 register 1
3940 pub FR123: RWRegister<u32>,
3941
3942 /// Filter bank 0 register 2
3943 pub FR223: RWRegister<u32>,
3944
3945 /// Filter bank 0 register 1
3946 pub FR124: RWRegister<u32>,
3947
3948 /// Filter bank 0 register 2
3949 pub FR224: RWRegister<u32>,
3950
3951 /// Filter bank 0 register 1
3952 pub FR125: RWRegister<u32>,
3953
3954 /// Filter bank 0 register 2
3955 pub FR225: RWRegister<u32>,
3956
3957 /// Filter bank 0 register 1
3958 pub FR126: RWRegister<u32>,
3959
3960 /// Filter bank 0 register 2
3961 pub FR226: RWRegister<u32>,
3962
3963 /// Filter bank 0 register 1
3964 pub FR127: RWRegister<u32>,
3965
3966 /// Filter bank 0 register 2
3967 pub FR227: RWRegister<u32>,
3968}
3969pub struct ResetValues {
3970 pub MCR: u32,
3971 pub MSR: u32,
3972 pub TSR: u32,
3973 pub RF0R: u32,
3974 pub RF1R: u32,
3975 pub IER: u32,
3976 pub ESR: u32,
3977 pub BTR: u32,
3978 pub TIR0: u32,
3979 pub TDTR0: u32,
3980 pub TDLR0: u32,
3981 pub TDHR0: u32,
3982 pub TIR1: u32,
3983 pub TDTR1: u32,
3984 pub TDLR1: u32,
3985 pub TDHR1: u32,
3986 pub TIR2: u32,
3987 pub TDTR2: u32,
3988 pub TDLR2: u32,
3989 pub TDHR2: u32,
3990 pub RIR0: u32,
3991 pub RDTR0: u32,
3992 pub RDLR0: u32,
3993 pub RDHR0: u32,
3994 pub RIR1: u32,
3995 pub RDTR1: u32,
3996 pub RDLR1: u32,
3997 pub RDHR1: u32,
3998 pub FMR: u32,
3999 pub FM1R: u32,
4000 pub FS1R: u32,
4001 pub FFA1R: u32,
4002 pub FA1R: u32,
4003 pub FR10: u32,
4004 pub FR20: u32,
4005 pub FR11: u32,
4006 pub FR21: u32,
4007 pub FR12: u32,
4008 pub FR22: u32,
4009 pub FR13: u32,
4010 pub FR23: u32,
4011 pub FR14: u32,
4012 pub FR24: u32,
4013 pub FR15: u32,
4014 pub FR25: u32,
4015 pub FR16: u32,
4016 pub FR26: u32,
4017 pub FR17: u32,
4018 pub FR27: u32,
4019 pub FR18: u32,
4020 pub FR28: u32,
4021 pub FR19: u32,
4022 pub FR29: u32,
4023 pub FR110: u32,
4024 pub FR210: u32,
4025 pub FR111: u32,
4026 pub FR211: u32,
4027 pub FR112: u32,
4028 pub FR212: u32,
4029 pub FR113: u32,
4030 pub FR213: u32,
4031 pub FR114: u32,
4032 pub FR214: u32,
4033 pub FR115: u32,
4034 pub FR215: u32,
4035 pub FR116: u32,
4036 pub FR216: u32,
4037 pub FR117: u32,
4038 pub FR217: u32,
4039 pub FR118: u32,
4040 pub FR218: u32,
4041 pub FR119: u32,
4042 pub FR219: u32,
4043 pub FR120: u32,
4044 pub FR220: u32,
4045 pub FR121: u32,
4046 pub FR221: u32,
4047 pub FR122: u32,
4048 pub FR222: u32,
4049 pub FR123: u32,
4050 pub FR223: u32,
4051 pub FR124: u32,
4052 pub FR224: u32,
4053 pub FR125: u32,
4054 pub FR225: u32,
4055 pub FR126: u32,
4056 pub FR226: u32,
4057 pub FR127: u32,
4058 pub FR227: u32,
4059}
4060#[cfg(not(feature = "nosync"))]
4061pub struct Instance {
4062 pub(crate) addr: u32,
4063 pub(crate) _marker: PhantomData<*const RegisterBlock>,
4064}
4065#[cfg(not(feature = "nosync"))]
4066impl ::core::ops::Deref for Instance {
4067 type Target = RegisterBlock;
4068 #[inline(always)]
4069 fn deref(&self) -> &RegisterBlock {
4070 unsafe { &*(self.addr as *const _) }
4071 }
4072}
4073#[cfg(feature = "rtic")]
4074unsafe impl Send for Instance {}