stm32ral/stm32f4/stm32f429/
interrupts.rs

1#[cfg(feature = "rt")]
2extern "C" {
3    fn WWDG();
4    fn PVD();
5    fn TAMP_STAMP();
6    fn RTC_WKUP();
7    fn FLASH();
8    fn RCC();
9    fn EXTI0();
10    fn EXTI1();
11    fn EXTI2();
12    fn EXTI3();
13    fn EXTI4();
14    fn DMA1_Stream0();
15    fn DMA1_Stream1();
16    fn DMA1_Stream2();
17    fn DMA1_Stream3();
18    fn DMA1_Stream4();
19    fn DMA1_Stream5();
20    fn DMA1_Stream6();
21    fn ADC();
22    fn CAN1_TX();
23    fn CAN1_RX0();
24    fn CAN1_RX1();
25    fn CAN1_SCE();
26    fn EXTI9_5();
27    fn TIM1_BRK_TIM9();
28    fn TIM1_UP_TIM10();
29    fn TIM1_TRG_COM_TIM11();
30    fn TIM1_CC();
31    fn TIM2();
32    fn TIM3();
33    fn TIM4();
34    fn I2C1_EV();
35    fn I2C1_ER();
36    fn I2C2_EV();
37    fn I2C2_ER();
38    fn SPI1();
39    fn SPI2();
40    fn USART1();
41    fn USART2();
42    fn USART3();
43    fn EXTI15_10();
44    fn RTC_Alarm();
45    fn OTG_FS_WKUP();
46    fn TIM8_BRK_TIM12();
47    fn TIM8_UP_TIM13();
48    fn TIM8_TRG_COM_TIM14();
49    fn TIM8_CC();
50    fn DMA1_Stream7();
51    fn FMC();
52    fn SDIO();
53    fn TIM5();
54    fn SPI3();
55    fn UART4();
56    fn UART5();
57    fn TIM6_DAC();
58    fn TIM7();
59    fn DMA2_Stream0();
60    fn DMA2_Stream1();
61    fn DMA2_Stream2();
62    fn DMA2_Stream3();
63    fn DMA2_Stream4();
64    fn ETH();
65    fn ETH_WKUP();
66    fn CAN2_TX();
67    fn CAN2_RX0();
68    fn CAN2_RX1();
69    fn CAN2_SCE();
70    fn OTG_FS();
71    fn DMA2_Stream5();
72    fn DMA2_Stream6();
73    fn DMA2_Stream7();
74    fn USART6();
75    fn I2C3_EV();
76    fn I2C3_ER();
77    fn OTG_HS_EP1_OUT();
78    fn OTG_HS_EP1_IN();
79    fn OTG_HS_WKUP();
80    fn OTG_HS();
81    fn DCMI();
82    fn CRYP();
83    fn HASH_RNG();
84    fn FPU();
85    fn UART7();
86    fn UART8();
87    fn SPI4();
88    fn SPI5();
89    fn SPI6();
90    fn SAI1();
91    fn LCD_TFT();
92    fn LCD_TFT_1();
93    fn DMA2D();
94}
95
96#[doc(hidden)]
97pub union Vector {
98    _handler: unsafe extern "C" fn(),
99    _reserved: u32,
100}
101
102#[cfg(feature = "rt")]
103#[doc(hidden)]
104#[link_section = ".vector_table.interrupts"]
105#[no_mangle]
106pub static __INTERRUPTS: [Vector; 91] = [
107    Vector { _handler: WWDG },
108    Vector { _handler: PVD },
109    Vector {
110        _handler: TAMP_STAMP,
111    },
112    Vector { _handler: RTC_WKUP },
113    Vector { _handler: FLASH },
114    Vector { _handler: RCC },
115    Vector { _handler: EXTI0 },
116    Vector { _handler: EXTI1 },
117    Vector { _handler: EXTI2 },
118    Vector { _handler: EXTI3 },
119    Vector { _handler: EXTI4 },
120    Vector {
121        _handler: DMA1_Stream0,
122    },
123    Vector {
124        _handler: DMA1_Stream1,
125    },
126    Vector {
127        _handler: DMA1_Stream2,
128    },
129    Vector {
130        _handler: DMA1_Stream3,
131    },
132    Vector {
133        _handler: DMA1_Stream4,
134    },
135    Vector {
136        _handler: DMA1_Stream5,
137    },
138    Vector {
139        _handler: DMA1_Stream6,
140    },
141    Vector { _handler: ADC },
142    Vector { _handler: CAN1_TX },
143    Vector { _handler: CAN1_RX0 },
144    Vector { _handler: CAN1_RX1 },
145    Vector { _handler: CAN1_SCE },
146    Vector { _handler: EXTI9_5 },
147    Vector {
148        _handler: TIM1_BRK_TIM9,
149    },
150    Vector {
151        _handler: TIM1_UP_TIM10,
152    },
153    Vector {
154        _handler: TIM1_TRG_COM_TIM11,
155    },
156    Vector { _handler: TIM1_CC },
157    Vector { _handler: TIM2 },
158    Vector { _handler: TIM3 },
159    Vector { _handler: TIM4 },
160    Vector { _handler: I2C1_EV },
161    Vector { _handler: I2C1_ER },
162    Vector { _handler: I2C2_EV },
163    Vector { _handler: I2C2_ER },
164    Vector { _handler: SPI1 },
165    Vector { _handler: SPI2 },
166    Vector { _handler: USART1 },
167    Vector { _handler: USART2 },
168    Vector { _handler: USART3 },
169    Vector {
170        _handler: EXTI15_10,
171    },
172    Vector {
173        _handler: RTC_Alarm,
174    },
175    Vector {
176        _handler: OTG_FS_WKUP,
177    },
178    Vector {
179        _handler: TIM8_BRK_TIM12,
180    },
181    Vector {
182        _handler: TIM8_UP_TIM13,
183    },
184    Vector {
185        _handler: TIM8_TRG_COM_TIM14,
186    },
187    Vector { _handler: TIM8_CC },
188    Vector {
189        _handler: DMA1_Stream7,
190    },
191    Vector { _handler: FMC },
192    Vector { _handler: SDIO },
193    Vector { _handler: TIM5 },
194    Vector { _handler: SPI3 },
195    Vector { _handler: UART4 },
196    Vector { _handler: UART5 },
197    Vector { _handler: TIM6_DAC },
198    Vector { _handler: TIM7 },
199    Vector {
200        _handler: DMA2_Stream0,
201    },
202    Vector {
203        _handler: DMA2_Stream1,
204    },
205    Vector {
206        _handler: DMA2_Stream2,
207    },
208    Vector {
209        _handler: DMA2_Stream3,
210    },
211    Vector {
212        _handler: DMA2_Stream4,
213    },
214    Vector { _handler: ETH },
215    Vector { _handler: ETH_WKUP },
216    Vector { _handler: CAN2_TX },
217    Vector { _handler: CAN2_RX0 },
218    Vector { _handler: CAN2_RX1 },
219    Vector { _handler: CAN2_SCE },
220    Vector { _handler: OTG_FS },
221    Vector {
222        _handler: DMA2_Stream5,
223    },
224    Vector {
225        _handler: DMA2_Stream6,
226    },
227    Vector {
228        _handler: DMA2_Stream7,
229    },
230    Vector { _handler: USART6 },
231    Vector { _handler: I2C3_EV },
232    Vector { _handler: I2C3_ER },
233    Vector {
234        _handler: OTG_HS_EP1_OUT,
235    },
236    Vector {
237        _handler: OTG_HS_EP1_IN,
238    },
239    Vector {
240        _handler: OTG_HS_WKUP,
241    },
242    Vector { _handler: OTG_HS },
243    Vector { _handler: DCMI },
244    Vector { _handler: CRYP },
245    Vector { _handler: HASH_RNG },
246    Vector { _handler: FPU },
247    Vector { _handler: UART7 },
248    Vector { _handler: UART8 },
249    Vector { _handler: SPI4 },
250    Vector { _handler: SPI5 },
251    Vector { _handler: SPI6 },
252    Vector { _handler: SAI1 },
253    Vector { _handler: LCD_TFT },
254    Vector {
255        _handler: LCD_TFT_1,
256    },
257    Vector { _handler: DMA2D },
258];
259
260/// Available interrupts for this device
261#[repr(u16)]
262#[derive(Copy, Clone, Debug, PartialEq, Eq)]
263#[allow(non_camel_case_types)]
264pub enum Interrupt {
265    /// 0: Window Watchdog interrupt
266    WWDG = 0,
267    /// 1: PVD through EXTI line detection interrupt
268    PVD = 1,
269    /// 2: Tamper and TimeStamp interrupts through the EXTI line
270    TAMP_STAMP = 2,
271    /// 3: RTC Wakeup interrupt through the EXTI line
272    RTC_WKUP = 3,
273    /// 4: Flash global interrupt
274    FLASH = 4,
275    /// 5: RCC global interrupt
276    RCC = 5,
277    /// 6: EXTI Line0 interrupt
278    EXTI0 = 6,
279    /// 7: EXTI Line1 interrupt
280    EXTI1 = 7,
281    /// 8: EXTI Line2 interrupt
282    EXTI2 = 8,
283    /// 9: EXTI Line3 interrupt
284    EXTI3 = 9,
285    /// 10: EXTI Line4 interrupt
286    EXTI4 = 10,
287    /// 11: DMA1 Stream0 global interrupt
288    DMA1_Stream0 = 11,
289    /// 12: DMA1 Stream1 global interrupt
290    DMA1_Stream1 = 12,
291    /// 13: DMA1 Stream2 global interrupt
292    DMA1_Stream2 = 13,
293    /// 14: DMA1 Stream3 global interrupt
294    DMA1_Stream3 = 14,
295    /// 15: DMA1 Stream4 global interrupt
296    DMA1_Stream4 = 15,
297    /// 16: DMA1 Stream5 global interrupt
298    DMA1_Stream5 = 16,
299    /// 17: DMA1 Stream6 global interrupt
300    DMA1_Stream6 = 17,
301    /// 18: ADC2 global interrupts
302    ADC = 18,
303    /// 19: CAN1 TX interrupts
304    CAN1_TX = 19,
305    /// 20: CAN1 RX0 interrupts
306    CAN1_RX0 = 20,
307    /// 21: CAN1 RX1 interrupts
308    CAN1_RX1 = 21,
309    /// 22: CAN1 SCE interrupt
310    CAN1_SCE = 22,
311    /// 23: EXTI Line\[9:5\] interrupts
312    EXTI9_5 = 23,
313    /// 24: TIM1 Break interrupt and TIM9 global interrupt
314    TIM1_BRK_TIM9 = 24,
315    /// 25: TIM1 Update interrupt and TIM10 global interrupt
316    TIM1_UP_TIM10 = 25,
317    /// 26: TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
318    TIM1_TRG_COM_TIM11 = 26,
319    /// 27: TIM1 Capture Compare interrupt
320    TIM1_CC = 27,
321    /// 28: TIM2 global interrupt
322    TIM2 = 28,
323    /// 29: TIM3 global interrupt
324    TIM3 = 29,
325    /// 30: TIM4 global interrupt
326    TIM4 = 30,
327    /// 31: I2C1 event interrupt
328    I2C1_EV = 31,
329    /// 32: I2C1 error interrupt
330    I2C1_ER = 32,
331    /// 33: I2C2 event interrupt
332    I2C2_EV = 33,
333    /// 34: I2C2 error interrupt
334    I2C2_ER = 34,
335    /// 35: SPI1 global interrupt
336    SPI1 = 35,
337    /// 36: SPI2 global interrupt
338    SPI2 = 36,
339    /// 37: USART1 global interrupt
340    USART1 = 37,
341    /// 38: USART2 global interrupt
342    USART2 = 38,
343    /// 39: USART3 global interrupt
344    USART3 = 39,
345    /// 40: EXTI Line\[15:10\] interrupts
346    EXTI15_10 = 40,
347    /// 41: RTC Alarms (A and B) through EXTI line interrupt
348    RTC_Alarm = 41,
349    /// 42: USB On-The-Go FS Wakeup through EXTI line interrupt
350    OTG_FS_WKUP = 42,
351    /// 43: TIM8 Break interrupt and TIM12 global interrupt
352    TIM8_BRK_TIM12 = 43,
353    /// 44: TIM8 Update interrupt and TIM13 global interrupt
354    TIM8_UP_TIM13 = 44,
355    /// 45: TIM8 Trigger and Commutation interrupts and TIM14 global interrupt
356    TIM8_TRG_COM_TIM14 = 45,
357    /// 46: TIM8 Capture Compare interrupt
358    TIM8_CC = 46,
359    /// 47: DMA1 Stream7 global interrupt
360    DMA1_Stream7 = 47,
361    /// 48: FMC global interrupt
362    FMC = 48,
363    /// 49: SDIO global interrupt
364    SDIO = 49,
365    /// 50: TIM5 global interrupt
366    TIM5 = 50,
367    /// 51: SPI3 global interrupt
368    SPI3 = 51,
369    /// 52: UART4 global interrupt
370    UART4 = 52,
371    /// 53: UART5 global interrupt
372    UART5 = 53,
373    /// 54: TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt
374    TIM6_DAC = 54,
375    /// 55: TIM7 global interrupt
376    TIM7 = 55,
377    /// 56: DMA2 Stream0 global interrupt
378    DMA2_Stream0 = 56,
379    /// 57: DMA2 Stream1 global interrupt
380    DMA2_Stream1 = 57,
381    /// 58: DMA2 Stream2 global interrupt
382    DMA2_Stream2 = 58,
383    /// 59: DMA2 Stream3 global interrupt
384    DMA2_Stream3 = 59,
385    /// 60: DMA2 Stream4 global interrupt
386    DMA2_Stream4 = 60,
387    /// 61: Ethernet global interrupt
388    ETH = 61,
389    /// 62: Ethernet Wakeup through EXTI line interrupt
390    ETH_WKUP = 62,
391    /// 63: CAN2 TX interrupts
392    CAN2_TX = 63,
393    /// 64: CAN2 RX0 interrupts
394    CAN2_RX0 = 64,
395    /// 65: CAN2 RX1 interrupts
396    CAN2_RX1 = 65,
397    /// 66: CAN2 SCE interrupt
398    CAN2_SCE = 66,
399    /// 67: USB On The Go FS global interrupt
400    OTG_FS = 67,
401    /// 68: DMA2 Stream5 global interrupt
402    DMA2_Stream5 = 68,
403    /// 69: DMA2 Stream6 global interrupt
404    DMA2_Stream6 = 69,
405    /// 70: DMA2 Stream7 global interrupt
406    DMA2_Stream7 = 70,
407    /// 71: USART6 global interrupt
408    USART6 = 71,
409    /// 72: I2C3 event interrupt
410    I2C3_EV = 72,
411    /// 73: I2C3 error interrupt
412    I2C3_ER = 73,
413    /// 74: USB On The Go HS End Point 1 Out global interrupt
414    OTG_HS_EP1_OUT = 74,
415    /// 75: USB On The Go HS End Point 1 In global interrupt
416    OTG_HS_EP1_IN = 75,
417    /// 76: USB On The Go HS Wakeup through EXTI interrupt
418    OTG_HS_WKUP = 76,
419    /// 77: USB On The Go HS global interrupt
420    OTG_HS = 77,
421    /// 78: DCMI global interrupt
422    DCMI = 78,
423    /// 79: CRYP crypto global interrupt
424    CRYP = 79,
425    /// 80: Hash and Rng global interrupt
426    HASH_RNG = 80,
427    /// 81: FPU interrupt
428    FPU = 81,
429    /// 82: UART 7 global interrupt
430    UART7 = 82,
431    /// 83: UART 8 global interrupt
432    UART8 = 83,
433    /// 84: SPI 4 global interrupt
434    SPI4 = 84,
435    /// 85: SPI 5 global interrupt
436    SPI5 = 85,
437    /// 86: SPI 6 global interrupt
438    SPI6 = 86,
439    /// 87: SAI1 global interrupt
440    SAI1 = 87,
441    /// 88: LTDC global interrupt
442    LCD_TFT = 88,
443    /// 89: LTDC global error interrupt
444    LCD_TFT_1 = 89,
445    /// 90: DMA2D global interrupt
446    DMA2D = 90,
447}
448unsafe impl external_cortex_m::interrupt::InterruptNumber for Interrupt {
449    #[inline(always)]
450    fn number(self) -> u16 {
451        self as u16
452    }
453}
stm32ral/stm32f4/stm32f429/interrupts.rs

stm32ral/stm32f4/stm32f429/
interrupts.rs
