stm32ral/stm32f1/stm32f103/
interrupts.rs

1#[cfg(feature = "rt")]
2extern "C" {
3    fn WWDG();
4    fn PVD();
5    fn TAMPER();
6    fn RTC();
7    fn FLASH();
8    fn RCC();
9    fn EXTI0();
10    fn EXTI1();
11    fn EXTI2();
12    fn EXTI3();
13    fn EXTI4();
14    fn DMA1_Channel1();
15    fn DMA1_Channel2();
16    fn DMA1_Channel3();
17    fn DMA1_Channel4();
18    fn DMA1_Channel5();
19    fn DMA1_Channel6();
20    fn DMA1_Channel7();
21    fn ADC1_2();
22    fn USB_HP_CAN_TX();
23    fn USB_LP_CAN_RX0();
24    fn CAN_RX1();
25    fn CAN_SCE();
26    fn EXTI9_5();
27    fn TIM1_BRK();
28    fn TIM1_UP();
29    fn TIM1_TRG_COM();
30    fn TIM1_CC();
31    fn TIM2();
32    fn TIM3();
33    fn TIM4();
34    fn I2C1_EV();
35    fn I2C1_ER();
36    fn I2C2_EV();
37    fn I2C2_ER();
38    fn SPI1();
39    fn SPI2();
40    fn USART1();
41    fn USART2();
42    fn USART3();
43    fn EXTI15_10();
44    fn RTCAlarm();
45    fn TIM8_BRK();
46    fn TIM8_UP();
47    fn TIM8_TRG_COM();
48    fn TIM8_CC();
49    fn ADC3();
50    fn FSMC();
51    fn SDIO();
52    fn TIM5();
53    fn SPI3();
54    fn UART4();
55    fn UART5();
56    fn TIM6();
57    fn TIM7();
58    fn DMA2_Channel1();
59    fn DMA2_Channel2();
60    fn DMA2_Channel3();
61    fn DMA2_Channel4_5();
62}
63
64#[doc(hidden)]
65pub union Vector {
66    _handler: unsafe extern "C" fn(),
67    _reserved: u32,
68}
69
70#[cfg(feature = "rt")]
71#[doc(hidden)]
72#[link_section = ".vector_table.interrupts"]
73#[no_mangle]
74pub static __INTERRUPTS: [Vector; 60] = [
75    Vector { _handler: WWDG },
76    Vector { _handler: PVD },
77    Vector { _handler: TAMPER },
78    Vector { _handler: RTC },
79    Vector { _handler: FLASH },
80    Vector { _handler: RCC },
81    Vector { _handler: EXTI0 },
82    Vector { _handler: EXTI1 },
83    Vector { _handler: EXTI2 },
84    Vector { _handler: EXTI3 },
85    Vector { _handler: EXTI4 },
86    Vector {
87        _handler: DMA1_Channel1,
88    },
89    Vector {
90        _handler: DMA1_Channel2,
91    },
92    Vector {
93        _handler: DMA1_Channel3,
94    },
95    Vector {
96        _handler: DMA1_Channel4,
97    },
98    Vector {
99        _handler: DMA1_Channel5,
100    },
101    Vector {
102        _handler: DMA1_Channel6,
103    },
104    Vector {
105        _handler: DMA1_Channel7,
106    },
107    Vector { _handler: ADC1_2 },
108    Vector {
109        _handler: USB_HP_CAN_TX,
110    },
111    Vector {
112        _handler: USB_LP_CAN_RX0,
113    },
114    Vector { _handler: CAN_RX1 },
115    Vector { _handler: CAN_SCE },
116    Vector { _handler: EXTI9_5 },
117    Vector { _handler: TIM1_BRK },
118    Vector { _handler: TIM1_UP },
119    Vector {
120        _handler: TIM1_TRG_COM,
121    },
122    Vector { _handler: TIM1_CC },
123    Vector { _handler: TIM2 },
124    Vector { _handler: TIM3 },
125    Vector { _handler: TIM4 },
126    Vector { _handler: I2C1_EV },
127    Vector { _handler: I2C1_ER },
128    Vector { _handler: I2C2_EV },
129    Vector { _handler: I2C2_ER },
130    Vector { _handler: SPI1 },
131    Vector { _handler: SPI2 },
132    Vector { _handler: USART1 },
133    Vector { _handler: USART2 },
134    Vector { _handler: USART3 },
135    Vector {
136        _handler: EXTI15_10,
137    },
138    Vector { _handler: RTCAlarm },
139    Vector { _reserved: 0 },
140    Vector { _handler: TIM8_BRK },
141    Vector { _handler: TIM8_UP },
142    Vector {
143        _handler: TIM8_TRG_COM,
144    },
145    Vector { _handler: TIM8_CC },
146    Vector { _handler: ADC3 },
147    Vector { _handler: FSMC },
148    Vector { _handler: SDIO },
149    Vector { _handler: TIM5 },
150    Vector { _handler: SPI3 },
151    Vector { _handler: UART4 },
152    Vector { _handler: UART5 },
153    Vector { _handler: TIM6 },
154    Vector { _handler: TIM7 },
155    Vector {
156        _handler: DMA2_Channel1,
157    },
158    Vector {
159        _handler: DMA2_Channel2,
160    },
161    Vector {
162        _handler: DMA2_Channel3,
163    },
164    Vector {
165        _handler: DMA2_Channel4_5,
166    },
167];
168
169/// Available interrupts for this device
170#[repr(u16)]
171#[derive(Copy, Clone, Debug, PartialEq, Eq)]
172#[allow(non_camel_case_types)]
173pub enum Interrupt {
174    /// 0: Window Watchdog interrupt
175    WWDG = 0,
176    /// 1: PVD through EXTI line detection interrupt
177    PVD = 1,
178    /// 2: Tamper interrupt
179    TAMPER = 2,
180    /// 3: RTC global interrupt
181    RTC = 3,
182    /// 4: Flash global interrupt
183    FLASH = 4,
184    /// 5: RCC global interrupt
185    RCC = 5,
186    /// 6: EXTI Line0 interrupt
187    EXTI0 = 6,
188    /// 7: EXTI Line1 interrupt
189    EXTI1 = 7,
190    /// 8: EXTI Line2 interrupt
191    EXTI2 = 8,
192    /// 9: EXTI Line3 interrupt
193    EXTI3 = 9,
194    /// 10: EXTI Line4 interrupt
195    EXTI4 = 10,
196    /// 11: DMA1 Channel1 global interrupt
197    DMA1_Channel1 = 11,
198    /// 12: DMA1 Channel2 global interrupt
199    DMA1_Channel2 = 12,
200    /// 13: DMA1 Channel3 global interrupt
201    DMA1_Channel3 = 13,
202    /// 14: DMA1 Channel4 global interrupt
203    DMA1_Channel4 = 14,
204    /// 15: DMA1 Channel5 global interrupt
205    DMA1_Channel5 = 15,
206    /// 16: DMA1 Channel6 global interrupt
207    DMA1_Channel6 = 16,
208    /// 17: DMA1 Channel7 global interrupt
209    DMA1_Channel7 = 17,
210    /// 18: ADC1 and ADC2 global interrupt
211    ADC1_2 = 18,
212    /// 19: USB High Priority or CAN TX interrupts
213    USB_HP_CAN_TX = 19,
214    /// 20: USB Low Priority or CAN RX0 interrupts
215    USB_LP_CAN_RX0 = 20,
216    /// 21: CAN RX1 interrupt
217    CAN_RX1 = 21,
218    /// 22: CAN SCE interrupt
219    CAN_SCE = 22,
220    /// 23: EXTI Line\[9:5\] interrupts
221    EXTI9_5 = 23,
222    /// 24: TIM1 Break interrupt
223    TIM1_BRK = 24,
224    /// 25: TIM1 Update interrupt
225    TIM1_UP = 25,
226    /// 26: TIM1 Trigger and Commutation interrupts
227    TIM1_TRG_COM = 26,
228    /// 27: TIM1 Capture Compare interrupt
229    TIM1_CC = 27,
230    /// 28: TIM2 global interrupt
231    TIM2 = 28,
232    /// 29: TIM3 global interrupt
233    TIM3 = 29,
234    /// 30: TIM4 global interrupt
235    TIM4 = 30,
236    /// 31: I2C1 event interrupt
237    I2C1_EV = 31,
238    /// 32: I2C1 error interrupt
239    I2C1_ER = 32,
240    /// 33: I2C2 event interrupt
241    I2C2_EV = 33,
242    /// 34: I2C2 error interrupt
243    I2C2_ER = 34,
244    /// 35: SPI1 global interrupt
245    SPI1 = 35,
246    /// 36: SPI2 global interrupt
247    SPI2 = 36,
248    /// 37: USART1 global interrupt
249    USART1 = 37,
250    /// 38: USART2 global interrupt
251    USART2 = 38,
252    /// 39: USART3 global interrupt
253    USART3 = 39,
254    /// 40: EXTI Line\[15:10\] interrupts
255    EXTI15_10 = 40,
256    /// 41: RTC Alarms through EXTI line interrupt
257    RTCAlarm = 41,
258    /// 43: TIM8 Break interrupt
259    TIM8_BRK = 43,
260    /// 44: TIM8 Update interrupt
261    TIM8_UP = 44,
262    /// 45: TIM8 Trigger and Commutation interrupts
263    TIM8_TRG_COM = 45,
264    /// 46: TIM8 Capture Compare interrupt
265    TIM8_CC = 46,
266    /// 47: ADC3 global interrupt
267    ADC3 = 47,
268    /// 48: FSMC global interrupt
269    FSMC = 48,
270    /// 49: SDIO global interrupt
271    SDIO = 49,
272    /// 50: TIM5 global interrupt
273    TIM5 = 50,
274    /// 51: SPI3 global interrupt
275    SPI3 = 51,
276    /// 52: UART4 global interrupt
277    UART4 = 52,
278    /// 53: UART5 global interrupt
279    UART5 = 53,
280    /// 54: TIM6 global interrupt
281    TIM6 = 54,
282    /// 55: TIM7 global interrupt
283    TIM7 = 55,
284    /// 56: DMA2 Channel1 global interrupt
285    DMA2_Channel1 = 56,
286    /// 57: DMA2 Channel2 global interrupt
287    DMA2_Channel2 = 57,
288    /// 58: DMA2 Channel3 global interrupt
289    DMA2_Channel3 = 58,
290    /// 59: DMA2 Channel4 and DMA2 Channel5 global interrupt
291    DMA2_Channel4_5 = 59,
292}
293unsafe impl external_cortex_m::interrupt::InterruptNumber for Interrupt {
294    #[inline(always)]
295    fn number(self) -> u16 {
296        self as u16
297    }
298}
stm32ral/stm32f1/stm32f103/interrupts.rs

stm32ral/stm32f1/stm32f103/
interrupts.rs
