stm32ral/stm32g0/stm32g030/syscfg_itline.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! System configuration controller
4
5use crate::RORegister;
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// interrupt line 0 status register
10pub mod ITLINE0 {
11
12 /// Window watchdog interrupt pending flag
13 pub mod WWDG {
14 /// Offset (0 bits)
15 pub const offset: u32 = 0;
16 /// Mask (1 bit: 1 << 0)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25}
26
27/// interrupt line 1 status register
28pub mod ITLINE1 {
29
30 /// PVD supply monitoring interrupt request pending (EXTI line 16).
31 pub mod PVDOUT {
32 /// Offset (0 bits)
33 pub const offset: u32 = 0;
34 /// Mask (1 bit: 1 << 0)
35 pub const mask: u32 = 1 << offset;
36 /// Read-only values (empty)
37 pub mod R {}
38 /// Write-only values (empty)
39 pub mod W {}
40 /// Read-write values (empty)
41 pub mod RW {}
42 }
43}
44
45/// interrupt line 2 status register
46pub mod ITLINE2 {
47
48 /// TAMP
49 pub mod TAMP {
50 /// Offset (0 bits)
51 pub const offset: u32 = 0;
52 /// Mask (1 bit: 1 << 0)
53 pub const mask: u32 = 1 << offset;
54 /// Read-only values (empty)
55 pub mod R {}
56 /// Write-only values (empty)
57 pub mod W {}
58 /// Read-write values (empty)
59 pub mod RW {}
60 }
61
62 /// RTC
63 pub mod RTC {
64 /// Offset (1 bits)
65 pub const offset: u32 = 1;
66 /// Mask (1 bit: 1 << 1)
67 pub const mask: u32 = 1 << offset;
68 /// Read-only values (empty)
69 pub mod R {}
70 /// Write-only values (empty)
71 pub mod W {}
72 /// Read-write values (empty)
73 pub mod RW {}
74 }
75}
76
77/// interrupt line 3 status register
78pub mod ITLINE3 {
79
80 /// FLASH_ITF
81 pub mod FLASH_ITF {
82 /// Offset (0 bits)
83 pub const offset: u32 = 0;
84 /// Mask (1 bit: 1 << 0)
85 pub const mask: u32 = 1 << offset;
86 /// Read-only values (empty)
87 pub mod R {}
88 /// Write-only values (empty)
89 pub mod W {}
90 /// Read-write values (empty)
91 pub mod RW {}
92 }
93
94 /// FLASH_ECC
95 pub mod FLASH_ECC {
96 /// Offset (1 bits)
97 pub const offset: u32 = 1;
98 /// Mask (1 bit: 1 << 1)
99 pub const mask: u32 = 1 << offset;
100 /// Read-only values (empty)
101 pub mod R {}
102 /// Write-only values (empty)
103 pub mod W {}
104 /// Read-write values (empty)
105 pub mod RW {}
106 }
107}
108
109/// interrupt line 4 status register
110pub mod ITLINE4 {
111
112 /// RCC
113 pub mod RCC {
114 /// Offset (0 bits)
115 pub const offset: u32 = 0;
116 /// Mask (1 bit: 1 << 0)
117 pub const mask: u32 = 1 << offset;
118 /// Read-only values (empty)
119 pub mod R {}
120 /// Write-only values (empty)
121 pub mod W {}
122 /// Read-write values (empty)
123 pub mod RW {}
124 }
125}
126
127/// interrupt line 5 status register
128pub mod ITLINE5 {
129
130 /// EXTI0
131 pub mod EXTI0 {
132 /// Offset (0 bits)
133 pub const offset: u32 = 0;
134 /// Mask (1 bit: 1 << 0)
135 pub const mask: u32 = 1 << offset;
136 /// Read-only values (empty)
137 pub mod R {}
138 /// Write-only values (empty)
139 pub mod W {}
140 /// Read-write values (empty)
141 pub mod RW {}
142 }
143
144 /// EXTI1
145 pub mod EXTI1 {
146 /// Offset (1 bits)
147 pub const offset: u32 = 1;
148 /// Mask (1 bit: 1 << 1)
149 pub const mask: u32 = 1 << offset;
150 /// Read-only values (empty)
151 pub mod R {}
152 /// Write-only values (empty)
153 pub mod W {}
154 /// Read-write values (empty)
155 pub mod RW {}
156 }
157}
158
159/// interrupt line 6 status register
160pub mod ITLINE6 {
161
162 /// EXTI2
163 pub mod EXTI2 {
164 /// Offset (0 bits)
165 pub const offset: u32 = 0;
166 /// Mask (1 bit: 1 << 0)
167 pub const mask: u32 = 1 << offset;
168 /// Read-only values (empty)
169 pub mod R {}
170 /// Write-only values (empty)
171 pub mod W {}
172 /// Read-write values (empty)
173 pub mod RW {}
174 }
175
176 /// EXTI3
177 pub mod EXTI3 {
178 /// Offset (1 bits)
179 pub const offset: u32 = 1;
180 /// Mask (1 bit: 1 << 1)
181 pub const mask: u32 = 1 << offset;
182 /// Read-only values (empty)
183 pub mod R {}
184 /// Write-only values (empty)
185 pub mod W {}
186 /// Read-write values (empty)
187 pub mod RW {}
188 }
189}
190
191/// interrupt line 7 status register
192pub mod ITLINE7 {
193
194 /// EXTI4
195 pub mod EXTI4 {
196 /// Offset (0 bits)
197 pub const offset: u32 = 0;
198 /// Mask (1 bit: 1 << 0)
199 pub const mask: u32 = 1 << offset;
200 /// Read-only values (empty)
201 pub mod R {}
202 /// Write-only values (empty)
203 pub mod W {}
204 /// Read-write values (empty)
205 pub mod RW {}
206 }
207
208 /// EXTI5
209 pub mod EXTI5 {
210 /// Offset (1 bits)
211 pub const offset: u32 = 1;
212 /// Mask (1 bit: 1 << 1)
213 pub const mask: u32 = 1 << offset;
214 /// Read-only values (empty)
215 pub mod R {}
216 /// Write-only values (empty)
217 pub mod W {}
218 /// Read-write values (empty)
219 pub mod RW {}
220 }
221
222 /// EXTI6
223 pub mod EXTI6 {
224 /// Offset (2 bits)
225 pub const offset: u32 = 2;
226 /// Mask (1 bit: 1 << 2)
227 pub const mask: u32 = 1 << offset;
228 /// Read-only values (empty)
229 pub mod R {}
230 /// Write-only values (empty)
231 pub mod W {}
232 /// Read-write values (empty)
233 pub mod RW {}
234 }
235
236 /// EXTI7
237 pub mod EXTI7 {
238 /// Offset (3 bits)
239 pub const offset: u32 = 3;
240 /// Mask (1 bit: 1 << 3)
241 pub const mask: u32 = 1 << offset;
242 /// Read-only values (empty)
243 pub mod R {}
244 /// Write-only values (empty)
245 pub mod W {}
246 /// Read-write values (empty)
247 pub mod RW {}
248 }
249
250 /// EXTI8
251 pub mod EXTI8 {
252 /// Offset (4 bits)
253 pub const offset: u32 = 4;
254 /// Mask (1 bit: 1 << 4)
255 pub const mask: u32 = 1 << offset;
256 /// Read-only values (empty)
257 pub mod R {}
258 /// Write-only values (empty)
259 pub mod W {}
260 /// Read-write values (empty)
261 pub mod RW {}
262 }
263
264 /// EXTI9
265 pub mod EXTI9 {
266 /// Offset (5 bits)
267 pub const offset: u32 = 5;
268 /// Mask (1 bit: 1 << 5)
269 pub const mask: u32 = 1 << offset;
270 /// Read-only values (empty)
271 pub mod R {}
272 /// Write-only values (empty)
273 pub mod W {}
274 /// Read-write values (empty)
275 pub mod RW {}
276 }
277
278 /// EXTI10
279 pub mod EXTI10 {
280 /// Offset (6 bits)
281 pub const offset: u32 = 6;
282 /// Mask (1 bit: 1 << 6)
283 pub const mask: u32 = 1 << offset;
284 /// Read-only values (empty)
285 pub mod R {}
286 /// Write-only values (empty)
287 pub mod W {}
288 /// Read-write values (empty)
289 pub mod RW {}
290 }
291
292 /// EXTI11
293 pub mod EXTI11 {
294 /// Offset (7 bits)
295 pub const offset: u32 = 7;
296 /// Mask (1 bit: 1 << 7)
297 pub const mask: u32 = 1 << offset;
298 /// Read-only values (empty)
299 pub mod R {}
300 /// Write-only values (empty)
301 pub mod W {}
302 /// Read-write values (empty)
303 pub mod RW {}
304 }
305
306 /// EXTI12
307 pub mod EXTI12 {
308 /// Offset (8 bits)
309 pub const offset: u32 = 8;
310 /// Mask (1 bit: 1 << 8)
311 pub const mask: u32 = 1 << offset;
312 /// Read-only values (empty)
313 pub mod R {}
314 /// Write-only values (empty)
315 pub mod W {}
316 /// Read-write values (empty)
317 pub mod RW {}
318 }
319
320 /// EXTI13
321 pub mod EXTI13 {
322 /// Offset (9 bits)
323 pub const offset: u32 = 9;
324 /// Mask (1 bit: 1 << 9)
325 pub const mask: u32 = 1 << offset;
326 /// Read-only values (empty)
327 pub mod R {}
328 /// Write-only values (empty)
329 pub mod W {}
330 /// Read-write values (empty)
331 pub mod RW {}
332 }
333
334 /// EXTI14
335 pub mod EXTI14 {
336 /// Offset (10 bits)
337 pub const offset: u32 = 10;
338 /// Mask (1 bit: 1 << 10)
339 pub const mask: u32 = 1 << offset;
340 /// Read-only values (empty)
341 pub mod R {}
342 /// Write-only values (empty)
343 pub mod W {}
344 /// Read-write values (empty)
345 pub mod RW {}
346 }
347
348 /// EXTI15
349 pub mod EXTI15 {
350 /// Offset (11 bits)
351 pub const offset: u32 = 11;
352 /// Mask (1 bit: 1 << 11)
353 pub const mask: u32 = 1 << offset;
354 /// Read-only values (empty)
355 pub mod R {}
356 /// Write-only values (empty)
357 pub mod W {}
358 /// Read-write values (empty)
359 pub mod RW {}
360 }
361}
362
363/// interrupt line 9 status register
364pub mod ITLINE9 {
365
366 /// DMA1_CH1
367 pub mod DMA1_CH1 {
368 /// Offset (0 bits)
369 pub const offset: u32 = 0;
370 /// Mask (1 bit: 1 << 0)
371 pub const mask: u32 = 1 << offset;
372 /// Read-only values (empty)
373 pub mod R {}
374 /// Write-only values (empty)
375 pub mod W {}
376 /// Read-write values (empty)
377 pub mod RW {}
378 }
379}
380
381/// interrupt line 10 status register
382pub mod ITLINE10 {
383
384 /// DMA1_CH1
385 pub mod DMA1_CH2 {
386 /// Offset (0 bits)
387 pub const offset: u32 = 0;
388 /// Mask (1 bit: 1 << 0)
389 pub const mask: u32 = 1 << offset;
390 /// Read-only values (empty)
391 pub mod R {}
392 /// Write-only values (empty)
393 pub mod W {}
394 /// Read-write values (empty)
395 pub mod RW {}
396 }
397
398 /// DMA1_CH3
399 pub mod DMA1_CH3 {
400 /// Offset (1 bits)
401 pub const offset: u32 = 1;
402 /// Mask (1 bit: 1 << 1)
403 pub const mask: u32 = 1 << offset;
404 /// Read-only values (empty)
405 pub mod R {}
406 /// Write-only values (empty)
407 pub mod W {}
408 /// Read-write values (empty)
409 pub mod RW {}
410 }
411}
412
413/// interrupt line 11 status register
414pub mod ITLINE11 {
415
416 /// DMAMUX
417 pub mod DMAMUX {
418 /// Offset (0 bits)
419 pub const offset: u32 = 0;
420 /// Mask (1 bit: 1 << 0)
421 pub const mask: u32 = 1 << offset;
422 /// Read-only values (empty)
423 pub mod R {}
424 /// Write-only values (empty)
425 pub mod W {}
426 /// Read-write values (empty)
427 pub mod RW {}
428 }
429
430 /// DMA1_CH4
431 pub mod DMA1_CH4 {
432 /// Offset (1 bits)
433 pub const offset: u32 = 1;
434 /// Mask (1 bit: 1 << 1)
435 pub const mask: u32 = 1 << offset;
436 /// Read-only values (empty)
437 pub mod R {}
438 /// Write-only values (empty)
439 pub mod W {}
440 /// Read-write values (empty)
441 pub mod RW {}
442 }
443
444 /// DMA1_CH5
445 pub mod DMA1_CH5 {
446 /// Offset (2 bits)
447 pub const offset: u32 = 2;
448 /// Mask (1 bit: 1 << 2)
449 pub const mask: u32 = 1 << offset;
450 /// Read-only values (empty)
451 pub mod R {}
452 /// Write-only values (empty)
453 pub mod W {}
454 /// Read-write values (empty)
455 pub mod RW {}
456 }
457}
458
459/// interrupt line 12 status register
460pub mod ITLINE12 {
461
462 /// ADC
463 pub mod ADC {
464 /// Offset (0 bits)
465 pub const offset: u32 = 0;
466 /// Mask (1 bit: 1 << 0)
467 pub const mask: u32 = 1 << offset;
468 /// Read-only values (empty)
469 pub mod R {}
470 /// Write-only values (empty)
471 pub mod W {}
472 /// Read-write values (empty)
473 pub mod RW {}
474 }
475}
476
477/// interrupt line 13 status register
478pub mod ITLINE13 {
479
480 /// TIM1_CCU
481 pub mod TIM1_CCU {
482 /// Offset (0 bits)
483 pub const offset: u32 = 0;
484 /// Mask (1 bit: 1 << 0)
485 pub const mask: u32 = 1 << offset;
486 /// Read-only values (empty)
487 pub mod R {}
488 /// Write-only values (empty)
489 pub mod W {}
490 /// Read-write values (empty)
491 pub mod RW {}
492 }
493
494 /// TIM1_TRG
495 pub mod TIM1_TRG {
496 /// Offset (1 bits)
497 pub const offset: u32 = 1;
498 /// Mask (1 bit: 1 << 1)
499 pub const mask: u32 = 1 << offset;
500 /// Read-only values (empty)
501 pub mod R {}
502 /// Write-only values (empty)
503 pub mod W {}
504 /// Read-write values (empty)
505 pub mod RW {}
506 }
507
508 /// TIM1_UPD
509 pub mod TIM1_UPD {
510 /// Offset (2 bits)
511 pub const offset: u32 = 2;
512 /// Mask (1 bit: 1 << 2)
513 pub const mask: u32 = 1 << offset;
514 /// Read-only values (empty)
515 pub mod R {}
516 /// Write-only values (empty)
517 pub mod W {}
518 /// Read-write values (empty)
519 pub mod RW {}
520 }
521
522 /// TIM1_BRK
523 pub mod TIM1_BRK {
524 /// Offset (3 bits)
525 pub const offset: u32 = 3;
526 /// Mask (1 bit: 1 << 3)
527 pub const mask: u32 = 1 << offset;
528 /// Read-only values (empty)
529 pub mod R {}
530 /// Write-only values (empty)
531 pub mod W {}
532 /// Read-write values (empty)
533 pub mod RW {}
534 }
535}
536
537/// interrupt line 14 status register
538pub mod ITLINE14 {
539
540 /// TIM1_CC
541 pub mod TIM1_CC {
542 /// Offset (0 bits)
543 pub const offset: u32 = 0;
544 /// Mask (1 bit: 1 << 0)
545 pub const mask: u32 = 1 << offset;
546 /// Read-only values (empty)
547 pub mod R {}
548 /// Write-only values (empty)
549 pub mod W {}
550 /// Read-write values (empty)
551 pub mod RW {}
552 }
553}
554
555/// interrupt line 15 status register
556pub mod ITLINE15 {
557
558 /// TIM2
559 pub mod TIM2 {
560 /// Offset (0 bits)
561 pub const offset: u32 = 0;
562 /// Mask (1 bit: 1 << 0)
563 pub const mask: u32 = 1 << offset;
564 /// Read-only values (empty)
565 pub mod R {}
566 /// Write-only values (empty)
567 pub mod W {}
568 /// Read-write values (empty)
569 pub mod RW {}
570 }
571}
572
573/// interrupt line 16 status register
574pub mod ITLINE16 {
575
576 /// TIM3
577 pub mod TIM3 {
578 /// Offset (0 bits)
579 pub const offset: u32 = 0;
580 /// Mask (1 bit: 1 << 0)
581 pub const mask: u32 = 1 << offset;
582 /// Read-only values (empty)
583 pub mod R {}
584 /// Write-only values (empty)
585 pub mod W {}
586 /// Read-write values (empty)
587 pub mod RW {}
588 }
589}
590
591/// interrupt line 19 status register
592pub mod ITLINE19 {
593
594 /// TIM14
595 pub mod TIM14 {
596 /// Offset (0 bits)
597 pub const offset: u32 = 0;
598 /// Mask (1 bit: 1 << 0)
599 pub const mask: u32 = 1 << offset;
600 /// Read-only values (empty)
601 pub mod R {}
602 /// Write-only values (empty)
603 pub mod W {}
604 /// Read-write values (empty)
605 pub mod RW {}
606 }
607}
608
609/// interrupt line 21 status register
610pub mod ITLINE21 {
611
612 /// TIM16
613 pub mod TIM16 {
614 /// Offset (0 bits)
615 pub const offset: u32 = 0;
616 /// Mask (1 bit: 1 << 0)
617 pub const mask: u32 = 1 << offset;
618 /// Read-only values (empty)
619 pub mod R {}
620 /// Write-only values (empty)
621 pub mod W {}
622 /// Read-write values (empty)
623 pub mod RW {}
624 }
625}
626
627/// interrupt line 22 status register
628pub mod ITLINE22 {
629
630 /// TIM17
631 pub mod TIM17 {
632 /// Offset (0 bits)
633 pub const offset: u32 = 0;
634 /// Mask (1 bit: 1 << 0)
635 pub const mask: u32 = 1 << offset;
636 /// Read-only values (empty)
637 pub mod R {}
638 /// Write-only values (empty)
639 pub mod W {}
640 /// Read-write values (empty)
641 pub mod RW {}
642 }
643}
644
645/// interrupt line 23 status register
646pub mod ITLINE23 {
647
648 /// I2C1
649 pub mod I2C1 {
650 /// Offset (0 bits)
651 pub const offset: u32 = 0;
652 /// Mask (1 bit: 1 << 0)
653 pub const mask: u32 = 1 << offset;
654 /// Read-only values (empty)
655 pub mod R {}
656 /// Write-only values (empty)
657 pub mod W {}
658 /// Read-write values (empty)
659 pub mod RW {}
660 }
661}
662
663/// interrupt line 24 status register
664pub mod ITLINE24 {
665
666 /// I2C2
667 pub mod I2C2 {
668 /// Offset (0 bits)
669 pub const offset: u32 = 0;
670 /// Mask (1 bit: 1 << 0)
671 pub const mask: u32 = 1 << offset;
672 /// Read-only values (empty)
673 pub mod R {}
674 /// Write-only values (empty)
675 pub mod W {}
676 /// Read-write values (empty)
677 pub mod RW {}
678 }
679}
680
681/// interrupt line 25 status register
682pub mod ITLINE25 {
683
684 /// SPI1
685 pub mod SPI1 {
686 /// Offset (0 bits)
687 pub const offset: u32 = 0;
688 /// Mask (1 bit: 1 << 0)
689 pub const mask: u32 = 1 << offset;
690 /// Read-only values (empty)
691 pub mod R {}
692 /// Write-only values (empty)
693 pub mod W {}
694 /// Read-write values (empty)
695 pub mod RW {}
696 }
697}
698
699/// interrupt line 26 status register
700pub mod ITLINE26 {
701
702 /// SPI2
703 pub mod SPI2 {
704 /// Offset (0 bits)
705 pub const offset: u32 = 0;
706 /// Mask (1 bit: 1 << 0)
707 pub const mask: u32 = 1 << offset;
708 /// Read-only values (empty)
709 pub mod R {}
710 /// Write-only values (empty)
711 pub mod W {}
712 /// Read-write values (empty)
713 pub mod RW {}
714 }
715}
716
717/// interrupt line 27 status register
718pub mod ITLINE27 {
719
720 /// USART1
721 pub mod USART1 {
722 /// Offset (0 bits)
723 pub const offset: u32 = 0;
724 /// Mask (1 bit: 1 << 0)
725 pub const mask: u32 = 1 << offset;
726 /// Read-only values (empty)
727 pub mod R {}
728 /// Write-only values (empty)
729 pub mod W {}
730 /// Read-write values (empty)
731 pub mod RW {}
732 }
733}
734
735/// interrupt line 28 status register
736pub mod ITLINE28 {
737
738 /// USART2
739 pub mod USART2 {
740 /// Offset (0 bits)
741 pub const offset: u32 = 0;
742 /// Mask (1 bit: 1 << 0)
743 pub const mask: u32 = 1 << offset;
744 /// Read-only values (empty)
745 pub mod R {}
746 /// Write-only values (empty)
747 pub mod W {}
748 /// Read-write values (empty)
749 pub mod RW {}
750 }
751}
752
753/// interrupt line 29 status register
754pub mod ITLINE29 {
755
756 /// USART5
757 pub mod USART5 {
758 /// Offset (2 bits)
759 pub const offset: u32 = 2;
760 /// Mask (1 bit: 1 << 2)
761 pub const mask: u32 = 1 << offset;
762 /// Read-only values (empty)
763 pub mod R {}
764 /// Write-only values (empty)
765 pub mod W {}
766 /// Read-write values (empty)
767 pub mod RW {}
768 }
769}
770#[repr(C)]
771pub struct RegisterBlock {
772 _reserved1: [u8; 128],
773
774 /// interrupt line 0 status register
775 pub ITLINE0: RORegister<u32>,
776
777 /// interrupt line 1 status register
778 pub ITLINE1: RORegister<u32>,
779
780 /// interrupt line 2 status register
781 pub ITLINE2: RORegister<u32>,
782
783 /// interrupt line 3 status register
784 pub ITLINE3: RORegister<u32>,
785
786 /// interrupt line 4 status register
787 pub ITLINE4: RORegister<u32>,
788
789 /// interrupt line 5 status register
790 pub ITLINE5: RORegister<u32>,
791
792 /// interrupt line 6 status register
793 pub ITLINE6: RORegister<u32>,
794
795 /// interrupt line 7 status register
796 pub ITLINE7: RORegister<u32>,
797
798 _reserved2: [u8; 4],
799
800 /// interrupt line 9 status register
801 pub ITLINE9: RORegister<u32>,
802
803 /// interrupt line 10 status register
804 pub ITLINE10: RORegister<u32>,
805
806 /// interrupt line 11 status register
807 pub ITLINE11: RORegister<u32>,
808
809 /// interrupt line 12 status register
810 pub ITLINE12: RORegister<u32>,
811
812 /// interrupt line 13 status register
813 pub ITLINE13: RORegister<u32>,
814
815 /// interrupt line 14 status register
816 pub ITLINE14: RORegister<u32>,
817
818 /// interrupt line 15 status register
819 pub ITLINE15: RORegister<u32>,
820
821 /// interrupt line 16 status register
822 pub ITLINE16: RORegister<u32>,
823
824 _reserved3: [u8; 8],
825
826 /// interrupt line 19 status register
827 pub ITLINE19: RORegister<u32>,
828
829 _reserved4: [u8; 4],
830
831 /// interrupt line 21 status register
832 pub ITLINE21: RORegister<u32>,
833
834 /// interrupt line 22 status register
835 pub ITLINE22: RORegister<u32>,
836
837 /// interrupt line 23 status register
838 pub ITLINE23: RORegister<u32>,
839
840 /// interrupt line 24 status register
841 pub ITLINE24: RORegister<u32>,
842
843 /// interrupt line 25 status register
844 pub ITLINE25: RORegister<u32>,
845
846 /// interrupt line 26 status register
847 pub ITLINE26: RORegister<u32>,
848
849 /// interrupt line 27 status register
850 pub ITLINE27: RORegister<u32>,
851
852 /// interrupt line 28 status register
853 pub ITLINE28: RORegister<u32>,
854
855 /// interrupt line 29 status register
856 pub ITLINE29: RORegister<u32>,
857}
858pub struct ResetValues {
859 pub ITLINE0: u32,
860 pub ITLINE1: u32,
861 pub ITLINE2: u32,
862 pub ITLINE3: u32,
863 pub ITLINE4: u32,
864 pub ITLINE5: u32,
865 pub ITLINE6: u32,
866 pub ITLINE7: u32,
867 pub ITLINE9: u32,
868 pub ITLINE10: u32,
869 pub ITLINE11: u32,
870 pub ITLINE12: u32,
871 pub ITLINE13: u32,
872 pub ITLINE14: u32,
873 pub ITLINE15: u32,
874 pub ITLINE16: u32,
875 pub ITLINE19: u32,
876 pub ITLINE21: u32,
877 pub ITLINE22: u32,
878 pub ITLINE23: u32,
879 pub ITLINE24: u32,
880 pub ITLINE25: u32,
881 pub ITLINE26: u32,
882 pub ITLINE27: u32,
883 pub ITLINE28: u32,
884 pub ITLINE29: u32,
885}
886#[cfg(not(feature = "nosync"))]
887pub struct Instance {
888 pub(crate) addr: u32,
889 pub(crate) _marker: PhantomData<*const RegisterBlock>,
890}
891#[cfg(not(feature = "nosync"))]
892impl ::core::ops::Deref for Instance {
893 type Target = RegisterBlock;
894 #[inline(always)]
895 fn deref(&self) -> &RegisterBlock {
896 unsafe { &*(self.addr as *const _) }
897 }
898}
899#[cfg(feature = "rtic")]
900unsafe impl Send for Instance {}
901
902/// Access functions for the SYSCFG_ITLINE peripheral instance
903pub mod SYSCFG_ITLINE {
904 use super::ResetValues;
905
906 #[cfg(not(feature = "nosync"))]
907 use super::Instance;
908
909 #[cfg(not(feature = "nosync"))]
910 const INSTANCE: Instance = Instance {
911 addr: 0x40010080,
912 _marker: ::core::marker::PhantomData,
913 };
914
915 /// Reset values for each field in SYSCFG_ITLINE
916 pub const reset: ResetValues = ResetValues {
917 ITLINE0: 0x00000000,
918 ITLINE1: 0x00000000,
919 ITLINE2: 0x00000000,
920 ITLINE3: 0x00000000,
921 ITLINE4: 0x00000000,
922 ITLINE5: 0x00000000,
923 ITLINE6: 0x00000000,
924 ITLINE7: 0x00000000,
925 ITLINE9: 0x00000000,
926 ITLINE10: 0x00000000,
927 ITLINE11: 0x00000000,
928 ITLINE12: 0x00000000,
929 ITLINE13: 0x00000000,
930 ITLINE14: 0x00000000,
931 ITLINE15: 0x00000000,
932 ITLINE16: 0x00000000,
933 ITLINE19: 0x00000000,
934 ITLINE21: 0x00000000,
935 ITLINE22: 0x00000000,
936 ITLINE23: 0x00000000,
937 ITLINE24: 0x00000000,
938 ITLINE25: 0x00000000,
939 ITLINE26: 0x00000000,
940 ITLINE27: 0x00000000,
941 ITLINE28: 0x00000000,
942 ITLINE29: 0x00000000,
943 };
944
945 #[cfg(not(feature = "nosync"))]
946 #[allow(renamed_and_removed_lints)]
947 #[allow(private_no_mangle_statics)]
948 #[no_mangle]
949 static mut SYSCFG_ITLINE_TAKEN: bool = false;
950
951 /// Safe access to SYSCFG_ITLINE
952 ///
953 /// This function returns `Some(Instance)` if this instance is not
954 /// currently taken, and `None` if it is. This ensures that if you
955 /// do get `Some(Instance)`, you are ensured unique access to
956 /// the peripheral and there cannot be data races (unless other
957 /// code uses `unsafe`, of course). You can then pass the
958 /// `Instance` around to other functions as required. When you're
959 /// done with it, you can call `release(instance)` to return it.
960 ///
961 /// `Instance` itself dereferences to a `RegisterBlock`, which
962 /// provides access to the peripheral's registers.
963 #[cfg(not(feature = "nosync"))]
964 #[inline]
965 pub fn take() -> Option<Instance> {
966 external_cortex_m::interrupt::free(|_| unsafe {
967 if SYSCFG_ITLINE_TAKEN {
968 None
969 } else {
970 SYSCFG_ITLINE_TAKEN = true;
971 Some(INSTANCE)
972 }
973 })
974 }
975
976 /// Release exclusive access to SYSCFG_ITLINE
977 ///
978 /// This function allows you to return an `Instance` so that it
979 /// is available to `take()` again. This function will panic if
980 /// you return a different `Instance` or if this instance is not
981 /// already taken.
982 #[cfg(not(feature = "nosync"))]
983 #[inline]
984 pub fn release(inst: Instance) {
985 external_cortex_m::interrupt::free(|_| unsafe {
986 if SYSCFG_ITLINE_TAKEN && inst.addr == INSTANCE.addr {
987 SYSCFG_ITLINE_TAKEN = false;
988 } else {
989 panic!("Released a peripheral which was not taken");
990 }
991 });
992 }
993
994 /// Unsafely steal SYSCFG_ITLINE
995 ///
996 /// This function is similar to take() but forcibly takes the
997 /// Instance, marking it as taken irregardless of its previous
998 /// state.
999 #[cfg(not(feature = "nosync"))]
1000 #[inline]
1001 pub unsafe fn steal() -> Instance {
1002 SYSCFG_ITLINE_TAKEN = true;
1003 INSTANCE
1004 }
1005}
1006
1007/// Raw pointer to SYSCFG_ITLINE
1008///
1009/// Dereferencing this is unsafe because you are not ensured unique
1010/// access to the peripheral, so you may encounter data races with
1011/// other users of this peripheral. It is up to you to ensure you
1012/// will not cause data races.
1013///
1014/// This constant is provided for ease of use in unsafe code: you can
1015/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
1016pub const SYSCFG_ITLINE: *const RegisterBlock = 0x40010080 as *const _;