stm32ral/stm32l1/peripherals/spi.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Serial peripheral interface
4//!
5//! Used by: stm32l151, stm32l162
6
7use crate::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Bidirectional data mode enable
15 pub mod BIDIMODE {
16 /// Offset (15 bits)
17 pub const offset: u32 = 15;
18 /// Mask (1 bit: 1 << 15)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Output enable in bidirectional mode
29 pub mod BIDIOE {
30 /// Offset (14 bits)
31 pub const offset: u32 = 14;
32 /// Mask (1 bit: 1 << 14)
33 pub const mask: u32 = 1 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// Hardware CRC calculation enable
43 pub mod CRCEN {
44 /// Offset (13 bits)
45 pub const offset: u32 = 13;
46 /// Mask (1 bit: 1 << 13)
47 pub const mask: u32 = 1 << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// CRC transfer next
57 pub mod CRCNEXT {
58 /// Offset (12 bits)
59 pub const offset: u32 = 12;
60 /// Mask (1 bit: 1 << 12)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// Data frame format
71 pub mod DFF {
72 /// Offset (11 bits)
73 pub const offset: u32 = 11;
74 /// Mask (1 bit: 1 << 11)
75 pub const mask: u32 = 1 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83
84 /// Receive only
85 pub mod RXONLY {
86 /// Offset (10 bits)
87 pub const offset: u32 = 10;
88 /// Mask (1 bit: 1 << 10)
89 pub const mask: u32 = 1 << offset;
90 /// Read-only values (empty)
91 pub mod R {}
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values (empty)
95 pub mod RW {}
96 }
97
98 /// Software slave management
99 pub mod SSM {
100 /// Offset (9 bits)
101 pub const offset: u32 = 9;
102 /// Mask (1 bit: 1 << 9)
103 pub const mask: u32 = 1 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values (empty)
109 pub mod RW {}
110 }
111
112 /// Internal slave select
113 pub mod SSI {
114 /// Offset (8 bits)
115 pub const offset: u32 = 8;
116 /// Mask (1 bit: 1 << 8)
117 pub const mask: u32 = 1 << offset;
118 /// Read-only values (empty)
119 pub mod R {}
120 /// Write-only values (empty)
121 pub mod W {}
122 /// Read-write values (empty)
123 pub mod RW {}
124 }
125
126 /// Frame format
127 pub mod LSBFIRST {
128 /// Offset (7 bits)
129 pub const offset: u32 = 7;
130 /// Mask (1 bit: 1 << 7)
131 pub const mask: u32 = 1 << offset;
132 /// Read-only values (empty)
133 pub mod R {}
134 /// Write-only values (empty)
135 pub mod W {}
136 /// Read-write values (empty)
137 pub mod RW {}
138 }
139
140 /// SPI enable
141 pub mod SPE {
142 /// Offset (6 bits)
143 pub const offset: u32 = 6;
144 /// Mask (1 bit: 1 << 6)
145 pub const mask: u32 = 1 << offset;
146 /// Read-only values (empty)
147 pub mod R {}
148 /// Write-only values (empty)
149 pub mod W {}
150 /// Read-write values (empty)
151 pub mod RW {}
152 }
153
154 /// Baud rate control
155 pub mod BR {
156 /// Offset (3 bits)
157 pub const offset: u32 = 3;
158 /// Mask (3 bits: 0b111 << 3)
159 pub const mask: u32 = 0b111 << offset;
160 /// Read-only values (empty)
161 pub mod R {}
162 /// Write-only values (empty)
163 pub mod W {}
164 /// Read-write values (empty)
165 pub mod RW {}
166 }
167
168 /// Master selection
169 pub mod MSTR {
170 /// Offset (2 bits)
171 pub const offset: u32 = 2;
172 /// Mask (1 bit: 1 << 2)
173 pub const mask: u32 = 1 << offset;
174 /// Read-only values (empty)
175 pub mod R {}
176 /// Write-only values (empty)
177 pub mod W {}
178 /// Read-write values (empty)
179 pub mod RW {}
180 }
181
182 /// Clock polarity
183 pub mod CPOL {
184 /// Offset (1 bits)
185 pub const offset: u32 = 1;
186 /// Mask (1 bit: 1 << 1)
187 pub const mask: u32 = 1 << offset;
188 /// Read-only values (empty)
189 pub mod R {}
190 /// Write-only values (empty)
191 pub mod W {}
192 /// Read-write values (empty)
193 pub mod RW {}
194 }
195
196 /// Clock phase
197 pub mod CPHA {
198 /// Offset (0 bits)
199 pub const offset: u32 = 0;
200 /// Mask (1 bit: 1 << 0)
201 pub const mask: u32 = 1 << offset;
202 /// Read-only values (empty)
203 pub mod R {}
204 /// Write-only values (empty)
205 pub mod W {}
206 /// Read-write values (empty)
207 pub mod RW {}
208 }
209}
210
211/// control register 2
212pub mod CR2 {
213
214 /// Tx buffer empty interrupt enable
215 pub mod TXEIE {
216 /// Offset (7 bits)
217 pub const offset: u32 = 7;
218 /// Mask (1 bit: 1 << 7)
219 pub const mask: u32 = 1 << offset;
220 /// Read-only values (empty)
221 pub mod R {}
222 /// Write-only values (empty)
223 pub mod W {}
224 /// Read-write values (empty)
225 pub mod RW {}
226 }
227
228 /// RX buffer not empty interrupt enable
229 pub mod RXNEIE {
230 /// Offset (6 bits)
231 pub const offset: u32 = 6;
232 /// Mask (1 bit: 1 << 6)
233 pub const mask: u32 = 1 << offset;
234 /// Read-only values (empty)
235 pub mod R {}
236 /// Write-only values (empty)
237 pub mod W {}
238 /// Read-write values (empty)
239 pub mod RW {}
240 }
241
242 /// Error interrupt enable
243 pub mod ERRIE {
244 /// Offset (5 bits)
245 pub const offset: u32 = 5;
246 /// Mask (1 bit: 1 << 5)
247 pub const mask: u32 = 1 << offset;
248 /// Read-only values (empty)
249 pub mod R {}
250 /// Write-only values (empty)
251 pub mod W {}
252 /// Read-write values (empty)
253 pub mod RW {}
254 }
255
256 /// Frame format
257 pub mod FRF {
258 /// Offset (4 bits)
259 pub const offset: u32 = 4;
260 /// Mask (1 bit: 1 << 4)
261 pub const mask: u32 = 1 << offset;
262 /// Read-only values (empty)
263 pub mod R {}
264 /// Write-only values (empty)
265 pub mod W {}
266 /// Read-write values (empty)
267 pub mod RW {}
268 }
269
270 /// SS output enable
271 pub mod SSOE {
272 /// Offset (2 bits)
273 pub const offset: u32 = 2;
274 /// Mask (1 bit: 1 << 2)
275 pub const mask: u32 = 1 << offset;
276 /// Read-only values (empty)
277 pub mod R {}
278 /// Write-only values (empty)
279 pub mod W {}
280 /// Read-write values (empty)
281 pub mod RW {}
282 }
283
284 /// Tx buffer DMA enable
285 pub mod TXDMAEN {
286 /// Offset (1 bits)
287 pub const offset: u32 = 1;
288 /// Mask (1 bit: 1 << 1)
289 pub const mask: u32 = 1 << offset;
290 /// Read-only values (empty)
291 pub mod R {}
292 /// Write-only values (empty)
293 pub mod W {}
294 /// Read-write values (empty)
295 pub mod RW {}
296 }
297
298 /// Rx buffer DMA enable
299 pub mod RXDMAEN {
300 /// Offset (0 bits)
301 pub const offset: u32 = 0;
302 /// Mask (1 bit: 1 << 0)
303 pub const mask: u32 = 1 << offset;
304 /// Read-only values (empty)
305 pub mod R {}
306 /// Write-only values (empty)
307 pub mod W {}
308 /// Read-write values (empty)
309 pub mod RW {}
310 }
311}
312
313/// status register
314pub mod SR {
315
316 /// TI frame format error
317 pub mod TIFRFE {
318 /// Offset (8 bits)
319 pub const offset: u32 = 8;
320 /// Mask (1 bit: 1 << 8)
321 pub const mask: u32 = 1 << offset;
322 /// Read-only values (empty)
323 pub mod R {}
324 /// Write-only values (empty)
325 pub mod W {}
326 /// Read-write values (empty)
327 pub mod RW {}
328 }
329
330 /// Busy flag
331 pub mod BSY {
332 /// Offset (7 bits)
333 pub const offset: u32 = 7;
334 /// Mask (1 bit: 1 << 7)
335 pub const mask: u32 = 1 << offset;
336 /// Read-only values (empty)
337 pub mod R {}
338 /// Write-only values (empty)
339 pub mod W {}
340 /// Read-write values (empty)
341 pub mod RW {}
342 }
343
344 /// Overrun flag
345 pub mod OVR {
346 /// Offset (6 bits)
347 pub const offset: u32 = 6;
348 /// Mask (1 bit: 1 << 6)
349 pub const mask: u32 = 1 << offset;
350 /// Read-only values (empty)
351 pub mod R {}
352 /// Write-only values (empty)
353 pub mod W {}
354 /// Read-write values (empty)
355 pub mod RW {}
356 }
357
358 /// Mode fault
359 pub mod MODF {
360 /// Offset (5 bits)
361 pub const offset: u32 = 5;
362 /// Mask (1 bit: 1 << 5)
363 pub const mask: u32 = 1 << offset;
364 /// Read-only values (empty)
365 pub mod R {}
366 /// Write-only values (empty)
367 pub mod W {}
368 /// Read-write values (empty)
369 pub mod RW {}
370 }
371
372 /// CRC error flag
373 pub mod CRCERR {
374 /// Offset (4 bits)
375 pub const offset: u32 = 4;
376 /// Mask (1 bit: 1 << 4)
377 pub const mask: u32 = 1 << offset;
378 /// Read-only values (empty)
379 pub mod R {}
380 /// Write-only values (empty)
381 pub mod W {}
382 /// Read-write values (empty)
383 pub mod RW {}
384 }
385
386 /// Underrun flag
387 pub mod UDR {
388 /// Offset (3 bits)
389 pub const offset: u32 = 3;
390 /// Mask (1 bit: 1 << 3)
391 pub const mask: u32 = 1 << offset;
392 /// Read-only values (empty)
393 pub mod R {}
394 /// Write-only values (empty)
395 pub mod W {}
396 /// Read-write values (empty)
397 pub mod RW {}
398 }
399
400 /// Channel side
401 pub mod CHSIDE {
402 /// Offset (2 bits)
403 pub const offset: u32 = 2;
404 /// Mask (1 bit: 1 << 2)
405 pub const mask: u32 = 1 << offset;
406 /// Read-only values (empty)
407 pub mod R {}
408 /// Write-only values (empty)
409 pub mod W {}
410 /// Read-write values (empty)
411 pub mod RW {}
412 }
413
414 /// Transmit buffer empty
415 pub mod TXE {
416 /// Offset (1 bits)
417 pub const offset: u32 = 1;
418 /// Mask (1 bit: 1 << 1)
419 pub const mask: u32 = 1 << offset;
420 /// Read-only values (empty)
421 pub mod R {}
422 /// Write-only values (empty)
423 pub mod W {}
424 /// Read-write values (empty)
425 pub mod RW {}
426 }
427
428 /// Receive buffer not empty
429 pub mod RXNE {
430 /// Offset (0 bits)
431 pub const offset: u32 = 0;
432 /// Mask (1 bit: 1 << 0)
433 pub const mask: u32 = 1 << offset;
434 /// Read-only values (empty)
435 pub mod R {}
436 /// Write-only values (empty)
437 pub mod W {}
438 /// Read-write values (empty)
439 pub mod RW {}
440 }
441}
442
443/// data register
444pub mod DR {
445
446 /// Data register
447 pub mod DR {
448 /// Offset (0 bits)
449 pub const offset: u32 = 0;
450 /// Mask (16 bits: 0xffff << 0)
451 pub const mask: u32 = 0xffff << offset;
452 /// Read-only values (empty)
453 pub mod R {}
454 /// Write-only values (empty)
455 pub mod W {}
456 /// Read-write values (empty)
457 pub mod RW {}
458 }
459}
460
461/// CRC polynomial register
462pub mod CRCPR {
463
464 /// CRC polynomial register
465 pub mod CRCPOLY {
466 /// Offset (0 bits)
467 pub const offset: u32 = 0;
468 /// Mask (16 bits: 0xffff << 0)
469 pub const mask: u32 = 0xffff << offset;
470 /// Read-only values (empty)
471 pub mod R {}
472 /// Write-only values (empty)
473 pub mod W {}
474 /// Read-write values (empty)
475 pub mod RW {}
476 }
477}
478
479/// RX CRC register
480pub mod RXCRCR {
481
482 /// Rx CRC register
483 pub mod RxCRC {
484 /// Offset (0 bits)
485 pub const offset: u32 = 0;
486 /// Mask (16 bits: 0xffff << 0)
487 pub const mask: u32 = 0xffff << offset;
488 /// Read-only values (empty)
489 pub mod R {}
490 /// Write-only values (empty)
491 pub mod W {}
492 /// Read-write values (empty)
493 pub mod RW {}
494 }
495}
496
497/// TX CRC register
498pub mod TXCRCR {
499
500 /// Tx CRC register
501 pub mod TxCRC {
502 /// Offset (0 bits)
503 pub const offset: u32 = 0;
504 /// Mask (16 bits: 0xffff << 0)
505 pub const mask: u32 = 0xffff << offset;
506 /// Read-only values (empty)
507 pub mod R {}
508 /// Write-only values (empty)
509 pub mod W {}
510 /// Read-write values (empty)
511 pub mod RW {}
512 }
513}
514
515/// I2S configuration register
516pub mod I2SCFGR {
517
518 /// I2S mode selection
519 pub mod I2SMOD {
520 /// Offset (11 bits)
521 pub const offset: u32 = 11;
522 /// Mask (1 bit: 1 << 11)
523 pub const mask: u32 = 1 << offset;
524 /// Read-only values (empty)
525 pub mod R {}
526 /// Write-only values (empty)
527 pub mod W {}
528 /// Read-write values (empty)
529 pub mod RW {}
530 }
531
532 /// I2S Enable
533 pub mod I2SE {
534 /// Offset (10 bits)
535 pub const offset: u32 = 10;
536 /// Mask (1 bit: 1 << 10)
537 pub const mask: u32 = 1 << offset;
538 /// Read-only values (empty)
539 pub mod R {}
540 /// Write-only values (empty)
541 pub mod W {}
542 /// Read-write values (empty)
543 pub mod RW {}
544 }
545
546 /// I2S configuration mode
547 pub mod I2SCFG {
548 /// Offset (8 bits)
549 pub const offset: u32 = 8;
550 /// Mask (2 bits: 0b11 << 8)
551 pub const mask: u32 = 0b11 << offset;
552 /// Read-only values (empty)
553 pub mod R {}
554 /// Write-only values (empty)
555 pub mod W {}
556 /// Read-write values (empty)
557 pub mod RW {}
558 }
559
560 /// PCM frame synchronization
561 pub mod PCMSYNC {
562 /// Offset (7 bits)
563 pub const offset: u32 = 7;
564 /// Mask (1 bit: 1 << 7)
565 pub const mask: u32 = 1 << offset;
566 /// Read-only values (empty)
567 pub mod R {}
568 /// Write-only values (empty)
569 pub mod W {}
570 /// Read-write values (empty)
571 pub mod RW {}
572 }
573
574 /// I2S standard selection
575 pub mod I2SSTD {
576 /// Offset (4 bits)
577 pub const offset: u32 = 4;
578 /// Mask (2 bits: 0b11 << 4)
579 pub const mask: u32 = 0b11 << offset;
580 /// Read-only values (empty)
581 pub mod R {}
582 /// Write-only values (empty)
583 pub mod W {}
584 /// Read-write values (empty)
585 pub mod RW {}
586 }
587
588 /// Steady state clock polarity
589 pub mod CKPOL {
590 /// Offset (3 bits)
591 pub const offset: u32 = 3;
592 /// Mask (1 bit: 1 << 3)
593 pub const mask: u32 = 1 << offset;
594 /// Read-only values (empty)
595 pub mod R {}
596 /// Write-only values (empty)
597 pub mod W {}
598 /// Read-write values (empty)
599 pub mod RW {}
600 }
601
602 /// Data length to be transferred
603 pub mod DATLEN {
604 /// Offset (1 bits)
605 pub const offset: u32 = 1;
606 /// Mask (2 bits: 0b11 << 1)
607 pub const mask: u32 = 0b11 << offset;
608 /// Read-only values (empty)
609 pub mod R {}
610 /// Write-only values (empty)
611 pub mod W {}
612 /// Read-write values (empty)
613 pub mod RW {}
614 }
615
616 /// Channel length (number of bits per audio channel)
617 pub mod CHLEN {
618 /// Offset (0 bits)
619 pub const offset: u32 = 0;
620 /// Mask (1 bit: 1 << 0)
621 pub const mask: u32 = 1 << offset;
622 /// Read-only values (empty)
623 pub mod R {}
624 /// Write-only values (empty)
625 pub mod W {}
626 /// Read-write values (empty)
627 pub mod RW {}
628 }
629}
630
631/// I2S prescaler register
632pub mod I2SPR {
633
634 /// Master clock output enable
635 pub mod MCKOE {
636 /// Offset (9 bits)
637 pub const offset: u32 = 9;
638 /// Mask (1 bit: 1 << 9)
639 pub const mask: u32 = 1 << offset;
640 /// Read-only values (empty)
641 pub mod R {}
642 /// Write-only values (empty)
643 pub mod W {}
644 /// Read-write values (empty)
645 pub mod RW {}
646 }
647
648 /// Odd factor for the prescaler
649 pub mod ODD {
650 /// Offset (8 bits)
651 pub const offset: u32 = 8;
652 /// Mask (1 bit: 1 << 8)
653 pub const mask: u32 = 1 << offset;
654 /// Read-only values (empty)
655 pub mod R {}
656 /// Write-only values (empty)
657 pub mod W {}
658 /// Read-write values (empty)
659 pub mod RW {}
660 }
661
662 /// I2S Linear prescaler
663 pub mod I2SDIV {
664 /// Offset (0 bits)
665 pub const offset: u32 = 0;
666 /// Mask (8 bits: 0xff << 0)
667 pub const mask: u32 = 0xff << offset;
668 /// Read-only values (empty)
669 pub mod R {}
670 /// Write-only values (empty)
671 pub mod W {}
672 /// Read-write values (empty)
673 pub mod RW {}
674 }
675}
676#[repr(C)]
677pub struct RegisterBlock {
678 /// control register 1
679 pub CR1: RWRegister<u32>,
680
681 /// control register 2
682 pub CR2: RWRegister<u32>,
683
684 /// status register
685 pub SR: RWRegister<u32>,
686
687 /// data register
688 pub DR: RWRegister<u32>,
689
690 /// CRC polynomial register
691 pub CRCPR: RWRegister<u32>,
692
693 /// RX CRC register
694 pub RXCRCR: RORegister<u32>,
695
696 /// TX CRC register
697 pub TXCRCR: RORegister<u32>,
698
699 /// I2S configuration register
700 pub I2SCFGR: RWRegister<u32>,
701
702 /// I2S prescaler register
703 pub I2SPR: RWRegister<u32>,
704}
705pub struct ResetValues {
706 pub CR1: u32,
707 pub CR2: u32,
708 pub SR: u32,
709 pub DR: u32,
710 pub CRCPR: u32,
711 pub RXCRCR: u32,
712 pub TXCRCR: u32,
713 pub I2SCFGR: u32,
714 pub I2SPR: u32,
715}
716#[cfg(not(feature = "nosync"))]
717pub struct Instance {
718 pub(crate) addr: u32,
719 pub(crate) _marker: PhantomData<*const RegisterBlock>,
720}
721#[cfg(not(feature = "nosync"))]
722impl ::core::ops::Deref for Instance {
723 type Target = RegisterBlock;
724 #[inline(always)]
725 fn deref(&self) -> &RegisterBlock {
726 unsafe { &*(self.addr as *const _) }
727 }
728}
729#[cfg(feature = "rtic")]
730unsafe impl Send for Instance {}