stm32ral/stm32f7/stm32f750/
can.rs

1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Controller area network
4
5use crate::{RORegister, RWRegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// master control register
10pub mod MCR {
11
12    /// DBF
13    pub mod DBF {
14        /// Offset (16 bits)
15        pub const offset: u32 = 16;
16        /// Mask (1 bit: 1 << 16)
17        pub const mask: u32 = 1 << offset;
18        /// Read-only values (empty)
19        pub mod R {}
20        /// Write-only values (empty)
21        pub mod W {}
22        /// Read-write values (empty)
23        pub mod RW {}
24    }
25
26    /// RESET
27    pub mod RESET {
28        /// Offset (15 bits)
29        pub const offset: u32 = 15;
30        /// Mask (1 bit: 1 << 15)
31        pub const mask: u32 = 1 << offset;
32        /// Read-only values (empty)
33        pub mod R {}
34        /// Write-only values (empty)
35        pub mod W {}
36        /// Read-write values (empty)
37        pub mod RW {}
38    }
39
40    /// TTCM
41    pub mod TTCM {
42        /// Offset (7 bits)
43        pub const offset: u32 = 7;
44        /// Mask (1 bit: 1 << 7)
45        pub const mask: u32 = 1 << offset;
46        /// Read-only values (empty)
47        pub mod R {}
48        /// Write-only values (empty)
49        pub mod W {}
50        /// Read-write values (empty)
51        pub mod RW {}
52    }
53
54    /// ABOM
55    pub mod ABOM {
56        /// Offset (6 bits)
57        pub const offset: u32 = 6;
58        /// Mask (1 bit: 1 << 6)
59        pub const mask: u32 = 1 << offset;
60        /// Read-only values (empty)
61        pub mod R {}
62        /// Write-only values (empty)
63        pub mod W {}
64        /// Read-write values (empty)
65        pub mod RW {}
66    }
67
68    /// AWUM
69    pub mod AWUM {
70        /// Offset (5 bits)
71        pub const offset: u32 = 5;
72        /// Mask (1 bit: 1 << 5)
73        pub const mask: u32 = 1 << offset;
74        /// Read-only values (empty)
75        pub mod R {}
76        /// Write-only values (empty)
77        pub mod W {}
78        /// Read-write values (empty)
79        pub mod RW {}
80    }
81
82    /// NART
83    pub mod NART {
84        /// Offset (4 bits)
85        pub const offset: u32 = 4;
86        /// Mask (1 bit: 1 << 4)
87        pub const mask: u32 = 1 << offset;
88        /// Read-only values (empty)
89        pub mod R {}
90        /// Write-only values (empty)
91        pub mod W {}
92        /// Read-write values (empty)
93        pub mod RW {}
94    }
95
96    /// RFLM
97    pub mod RFLM {
98        /// Offset (3 bits)
99        pub const offset: u32 = 3;
100        /// Mask (1 bit: 1 << 3)
101        pub const mask: u32 = 1 << offset;
102        /// Read-only values (empty)
103        pub mod R {}
104        /// Write-only values (empty)
105        pub mod W {}
106        /// Read-write values (empty)
107        pub mod RW {}
108    }
109
110    /// TXFP
111    pub mod TXFP {
112        /// Offset (2 bits)
113        pub const offset: u32 = 2;
114        /// Mask (1 bit: 1 << 2)
115        pub const mask: u32 = 1 << offset;
116        /// Read-only values (empty)
117        pub mod R {}
118        /// Write-only values (empty)
119        pub mod W {}
120        /// Read-write values (empty)
121        pub mod RW {}
122    }
123
124    /// SLEEP
125    pub mod SLEEP {
126        /// Offset (1 bits)
127        pub const offset: u32 = 1;
128        /// Mask (1 bit: 1 << 1)
129        pub const mask: u32 = 1 << offset;
130        /// Read-only values (empty)
131        pub mod R {}
132        /// Write-only values (empty)
133        pub mod W {}
134        /// Read-write values (empty)
135        pub mod RW {}
136    }
137
138    /// INRQ
139    pub mod INRQ {
140        /// Offset (0 bits)
141        pub const offset: u32 = 0;
142        /// Mask (1 bit: 1 << 0)
143        pub const mask: u32 = 1 << offset;
144        /// Read-only values (empty)
145        pub mod R {}
146        /// Write-only values (empty)
147        pub mod W {}
148        /// Read-write values (empty)
149        pub mod RW {}
150    }
151}
152
153/// master status register
154pub mod MSR {
155
156    /// RX
157    pub mod RX {
158        /// Offset (11 bits)
159        pub const offset: u32 = 11;
160        /// Mask (1 bit: 1 << 11)
161        pub const mask: u32 = 1 << offset;
162        /// Read-only values (empty)
163        pub mod R {}
164        /// Write-only values (empty)
165        pub mod W {}
166        /// Read-write values (empty)
167        pub mod RW {}
168    }
169
170    /// SAMP
171    pub mod SAMP {
172        /// Offset (10 bits)
173        pub const offset: u32 = 10;
174        /// Mask (1 bit: 1 << 10)
175        pub const mask: u32 = 1 << offset;
176        /// Read-only values (empty)
177        pub mod R {}
178        /// Write-only values (empty)
179        pub mod W {}
180        /// Read-write values (empty)
181        pub mod RW {}
182    }
183
184    /// RXM
185    pub mod RXM {
186        /// Offset (9 bits)
187        pub const offset: u32 = 9;
188        /// Mask (1 bit: 1 << 9)
189        pub const mask: u32 = 1 << offset;
190        /// Read-only values (empty)
191        pub mod R {}
192        /// Write-only values (empty)
193        pub mod W {}
194        /// Read-write values (empty)
195        pub mod RW {}
196    }
197
198    /// TXM
199    pub mod TXM {
200        /// Offset (8 bits)
201        pub const offset: u32 = 8;
202        /// Mask (1 bit: 1 << 8)
203        pub const mask: u32 = 1 << offset;
204        /// Read-only values (empty)
205        pub mod R {}
206        /// Write-only values (empty)
207        pub mod W {}
208        /// Read-write values (empty)
209        pub mod RW {}
210    }
211
212    /// SLAKI
213    pub mod SLAKI {
214        /// Offset (4 bits)
215        pub const offset: u32 = 4;
216        /// Mask (1 bit: 1 << 4)
217        pub const mask: u32 = 1 << offset;
218        /// Read-only values (empty)
219        pub mod R {}
220        /// Write-only values (empty)
221        pub mod W {}
222        /// Read-write values (empty)
223        pub mod RW {}
224    }
225
226    /// WKUI
227    pub mod WKUI {
228        /// Offset (3 bits)
229        pub const offset: u32 = 3;
230        /// Mask (1 bit: 1 << 3)
231        pub const mask: u32 = 1 << offset;
232        /// Read-only values (empty)
233        pub mod R {}
234        /// Write-only values (empty)
235        pub mod W {}
236        /// Read-write values (empty)
237        pub mod RW {}
238    }
239
240    /// ERRI
241    pub mod ERRI {
242        /// Offset (2 bits)
243        pub const offset: u32 = 2;
244        /// Mask (1 bit: 1 << 2)
245        pub const mask: u32 = 1 << offset;
246        /// Read-only values (empty)
247        pub mod R {}
248        /// Write-only values (empty)
249        pub mod W {}
250        /// Read-write values (empty)
251        pub mod RW {}
252    }
253
254    /// SLAK
255    pub mod SLAK {
256        /// Offset (1 bits)
257        pub const offset: u32 = 1;
258        /// Mask (1 bit: 1 << 1)
259        pub const mask: u32 = 1 << offset;
260        /// Read-only values (empty)
261        pub mod R {}
262        /// Write-only values (empty)
263        pub mod W {}
264        /// Read-write values (empty)
265        pub mod RW {}
266    }
267
268    /// INAK
269    pub mod INAK {
270        /// Offset (0 bits)
271        pub const offset: u32 = 0;
272        /// Mask (1 bit: 1 << 0)
273        pub const mask: u32 = 1 << offset;
274        /// Read-only values (empty)
275        pub mod R {}
276        /// Write-only values (empty)
277        pub mod W {}
278        /// Read-write values (empty)
279        pub mod RW {}
280    }
281}
282
283/// transmit status register
284pub mod TSR {
285
286    /// Lowest priority flag for mailbox 2
287    pub mod LOW2 {
288        /// Offset (31 bits)
289        pub const offset: u32 = 31;
290        /// Mask (1 bit: 1 << 31)
291        pub const mask: u32 = 1 << offset;
292        /// Read-only values (empty)
293        pub mod R {}
294        /// Write-only values (empty)
295        pub mod W {}
296        /// Read-write values (empty)
297        pub mod RW {}
298    }
299
300    /// Lowest priority flag for mailbox 1
301    pub mod LOW1 {
302        /// Offset (30 bits)
303        pub const offset: u32 = 30;
304        /// Mask (1 bit: 1 << 30)
305        pub const mask: u32 = 1 << offset;
306        /// Read-only values (empty)
307        pub mod R {}
308        /// Write-only values (empty)
309        pub mod W {}
310        /// Read-write values (empty)
311        pub mod RW {}
312    }
313
314    /// Lowest priority flag for mailbox 0
315    pub mod LOW0 {
316        /// Offset (29 bits)
317        pub const offset: u32 = 29;
318        /// Mask (1 bit: 1 << 29)
319        pub const mask: u32 = 1 << offset;
320        /// Read-only values (empty)
321        pub mod R {}
322        /// Write-only values (empty)
323        pub mod W {}
324        /// Read-write values (empty)
325        pub mod RW {}
326    }
327
328    /// Lowest priority flag for mailbox 2
329    pub mod TME2 {
330        /// Offset (28 bits)
331        pub const offset: u32 = 28;
332        /// Mask (1 bit: 1 << 28)
333        pub const mask: u32 = 1 << offset;
334        /// Read-only values (empty)
335        pub mod R {}
336        /// Write-only values (empty)
337        pub mod W {}
338        /// Read-write values (empty)
339        pub mod RW {}
340    }
341
342    /// Lowest priority flag for mailbox 1
343    pub mod TME1 {
344        /// Offset (27 bits)
345        pub const offset: u32 = 27;
346        /// Mask (1 bit: 1 << 27)
347        pub const mask: u32 = 1 << offset;
348        /// Read-only values (empty)
349        pub mod R {}
350        /// Write-only values (empty)
351        pub mod W {}
352        /// Read-write values (empty)
353        pub mod RW {}
354    }
355
356    /// Lowest priority flag for mailbox 0
357    pub mod TME0 {
358        /// Offset (26 bits)
359        pub const offset: u32 = 26;
360        /// Mask (1 bit: 1 << 26)
361        pub const mask: u32 = 1 << offset;
362        /// Read-only values (empty)
363        pub mod R {}
364        /// Write-only values (empty)
365        pub mod W {}
366        /// Read-write values (empty)
367        pub mod RW {}
368    }
369
370    /// CODE
371    pub mod CODE {
372        /// Offset (24 bits)
373        pub const offset: u32 = 24;
374        /// Mask (2 bits: 0b11 << 24)
375        pub const mask: u32 = 0b11 << offset;
376        /// Read-only values (empty)
377        pub mod R {}
378        /// Write-only values (empty)
379        pub mod W {}
380        /// Read-write values (empty)
381        pub mod RW {}
382    }
383
384    /// ABRQ2
385    pub mod ABRQ2 {
386        /// Offset (23 bits)
387        pub const offset: u32 = 23;
388        /// Mask (1 bit: 1 << 23)
389        pub const mask: u32 = 1 << offset;
390        /// Read-only values (empty)
391        pub mod R {}
392        /// Write-only values (empty)
393        pub mod W {}
394        /// Read-write values (empty)
395        pub mod RW {}
396    }
397
398    /// TERR2
399    pub mod TERR2 {
400        /// Offset (19 bits)
401        pub const offset: u32 = 19;
402        /// Mask (1 bit: 1 << 19)
403        pub const mask: u32 = 1 << offset;
404        /// Read-only values (empty)
405        pub mod R {}
406        /// Write-only values (empty)
407        pub mod W {}
408        /// Read-write values (empty)
409        pub mod RW {}
410    }
411
412    /// ALST2
413    pub mod ALST2 {
414        /// Offset (18 bits)
415        pub const offset: u32 = 18;
416        /// Mask (1 bit: 1 << 18)
417        pub const mask: u32 = 1 << offset;
418        /// Read-only values (empty)
419        pub mod R {}
420        /// Write-only values (empty)
421        pub mod W {}
422        /// Read-write values (empty)
423        pub mod RW {}
424    }
425
426    /// TXOK2
427    pub mod TXOK2 {
428        /// Offset (17 bits)
429        pub const offset: u32 = 17;
430        /// Mask (1 bit: 1 << 17)
431        pub const mask: u32 = 1 << offset;
432        /// Read-only values (empty)
433        pub mod R {}
434        /// Write-only values (empty)
435        pub mod W {}
436        /// Read-write values (empty)
437        pub mod RW {}
438    }
439
440    /// RQCP2
441    pub mod RQCP2 {
442        /// Offset (16 bits)
443        pub const offset: u32 = 16;
444        /// Mask (1 bit: 1 << 16)
445        pub const mask: u32 = 1 << offset;
446        /// Read-only values (empty)
447        pub mod R {}
448        /// Write-only values (empty)
449        pub mod W {}
450        /// Read-write values (empty)
451        pub mod RW {}
452    }
453
454    /// ABRQ1
455    pub mod ABRQ1 {
456        /// Offset (15 bits)
457        pub const offset: u32 = 15;
458        /// Mask (1 bit: 1 << 15)
459        pub const mask: u32 = 1 << offset;
460        /// Read-only values (empty)
461        pub mod R {}
462        /// Write-only values (empty)
463        pub mod W {}
464        /// Read-write values (empty)
465        pub mod RW {}
466    }
467
468    /// TERR1
469    pub mod TERR1 {
470        /// Offset (11 bits)
471        pub const offset: u32 = 11;
472        /// Mask (1 bit: 1 << 11)
473        pub const mask: u32 = 1 << offset;
474        /// Read-only values (empty)
475        pub mod R {}
476        /// Write-only values (empty)
477        pub mod W {}
478        /// Read-write values (empty)
479        pub mod RW {}
480    }
481
482    /// ALST1
483    pub mod ALST1 {
484        /// Offset (10 bits)
485        pub const offset: u32 = 10;
486        /// Mask (1 bit: 1 << 10)
487        pub const mask: u32 = 1 << offset;
488        /// Read-only values (empty)
489        pub mod R {}
490        /// Write-only values (empty)
491        pub mod W {}
492        /// Read-write values (empty)
493        pub mod RW {}
494    }
495
496    /// TXOK1
497    pub mod TXOK1 {
498        /// Offset (9 bits)
499        pub const offset: u32 = 9;
500        /// Mask (1 bit: 1 << 9)
501        pub const mask: u32 = 1 << offset;
502        /// Read-only values (empty)
503        pub mod R {}
504        /// Write-only values (empty)
505        pub mod W {}
506        /// Read-write values (empty)
507        pub mod RW {}
508    }
509
510    /// RQCP1
511    pub mod RQCP1 {
512        /// Offset (8 bits)
513        pub const offset: u32 = 8;
514        /// Mask (1 bit: 1 << 8)
515        pub const mask: u32 = 1 << offset;
516        /// Read-only values (empty)
517        pub mod R {}
518        /// Write-only values (empty)
519        pub mod W {}
520        /// Read-write values (empty)
521        pub mod RW {}
522    }
523
524    /// ABRQ0
525    pub mod ABRQ0 {
526        /// Offset (7 bits)
527        pub const offset: u32 = 7;
528        /// Mask (1 bit: 1 << 7)
529        pub const mask: u32 = 1 << offset;
530        /// Read-only values (empty)
531        pub mod R {}
532        /// Write-only values (empty)
533        pub mod W {}
534        /// Read-write values (empty)
535        pub mod RW {}
536    }
537
538    /// TERR0
539    pub mod TERR0 {
540        /// Offset (3 bits)
541        pub const offset: u32 = 3;
542        /// Mask (1 bit: 1 << 3)
543        pub const mask: u32 = 1 << offset;
544        /// Read-only values (empty)
545        pub mod R {}
546        /// Write-only values (empty)
547        pub mod W {}
548        /// Read-write values (empty)
549        pub mod RW {}
550    }
551
552    /// ALST0
553    pub mod ALST0 {
554        /// Offset (2 bits)
555        pub const offset: u32 = 2;
556        /// Mask (1 bit: 1 << 2)
557        pub const mask: u32 = 1 << offset;
558        /// Read-only values (empty)
559        pub mod R {}
560        /// Write-only values (empty)
561        pub mod W {}
562        /// Read-write values (empty)
563        pub mod RW {}
564    }
565
566    /// TXOK0
567    pub mod TXOK0 {
568        /// Offset (1 bits)
569        pub const offset: u32 = 1;
570        /// Mask (1 bit: 1 << 1)
571        pub const mask: u32 = 1 << offset;
572        /// Read-only values (empty)
573        pub mod R {}
574        /// Write-only values (empty)
575        pub mod W {}
576        /// Read-write values (empty)
577        pub mod RW {}
578    }
579
580    /// RQCP0
581    pub mod RQCP0 {
582        /// Offset (0 bits)
583        pub const offset: u32 = 0;
584        /// Mask (1 bit: 1 << 0)
585        pub const mask: u32 = 1 << offset;
586        /// Read-only values (empty)
587        pub mod R {}
588        /// Write-only values (empty)
589        pub mod W {}
590        /// Read-write values (empty)
591        pub mod RW {}
592    }
593}
594
595/// receive FIFO %s register
596pub mod RF0R {
597
598    /// RFOM0
599    pub mod RFOM {
600        /// Offset (5 bits)
601        pub const offset: u32 = 5;
602        /// Mask (1 bit: 1 << 5)
603        pub const mask: u32 = 1 << offset;
604        /// Read-only values (empty)
605        pub mod R {}
606        /// Write-only values
607        pub mod W {
608
609            /// 0b1: Set by software to release the output mailbox of the FIFO
610            pub const Release: u32 = 0b1;
611        }
612        /// Read-write values (empty)
613        pub mod RW {}
614    }
615
616    /// FOVR0
617    pub mod FOVR {
618        /// Offset (4 bits)
619        pub const offset: u32 = 4;
620        /// Mask (1 bit: 1 << 4)
621        pub const mask: u32 = 1 << offset;
622        /// Read-only values
623        pub mod R {
624
625            /// 0b0: No FIFO x overrun
626            pub const NoOverrun: u32 = 0b0;
627
628            /// 0b1: FIFO x overrun
629            pub const Overrun: u32 = 0b1;
630        }
631        /// Write-only values
632        pub mod W {
633
634            /// 0b1: Clear flag
635            pub const Clear: u32 = 0b1;
636        }
637        /// Read-write values (empty)
638        pub mod RW {}
639    }
640
641    /// FULL0
642    pub mod FULL {
643        /// Offset (3 bits)
644        pub const offset: u32 = 3;
645        /// Mask (1 bit: 1 << 3)
646        pub const mask: u32 = 1 << offset;
647        /// Read-only values
648        pub mod R {
649
650            /// 0b0: FIFO x is not full
651            pub const NotFull: u32 = 0b0;
652
653            /// 0b1: FIFO x is full
654            pub const Full: u32 = 0b1;
655        }
656        pub use super::FOVR::W;
657        /// Read-write values (empty)
658        pub mod RW {}
659    }
660
661    /// FMP0
662    pub mod FMP {
663        /// Offset (0 bits)
664        pub const offset: u32 = 0;
665        /// Mask (2 bits: 0b11 << 0)
666        pub const mask: u32 = 0b11 << offset;
667        /// Read-only values (empty)
668        pub mod R {}
669        /// Write-only values (empty)
670        pub mod W {}
671        /// Read-write values (empty)
672        pub mod RW {}
673    }
674}
675
676/// receive FIFO %s register
677pub mod RF1R {
678    pub use super::RF0R::FMP;
679    pub use super::RF0R::FOVR;
680    pub use super::RF0R::FULL;
681    pub use super::RF0R::RFOM;
682}
683
684/// interrupt enable register
685pub mod IER {
686
687    /// SLKIE
688    pub mod SLKIE {
689        /// Offset (17 bits)
690        pub const offset: u32 = 17;
691        /// Mask (1 bit: 1 << 17)
692        pub const mask: u32 = 1 << offset;
693        /// Read-only values (empty)
694        pub mod R {}
695        /// Write-only values (empty)
696        pub mod W {}
697        /// Read-write values
698        pub mod RW {
699
700            /// 0b0: No interrupt when SLAKI bit is set
701            pub const Disabled: u32 = 0b0;
702
703            /// 0b1: Interrupt generated when SLAKI bit is set
704            pub const Enabled: u32 = 0b1;
705        }
706    }
707
708    /// WKUIE
709    pub mod WKUIE {
710        /// Offset (16 bits)
711        pub const offset: u32 = 16;
712        /// Mask (1 bit: 1 << 16)
713        pub const mask: u32 = 1 << offset;
714        /// Read-only values (empty)
715        pub mod R {}
716        /// Write-only values (empty)
717        pub mod W {}
718        /// Read-write values
719        pub mod RW {
720
721            /// 0b0: No interrupt when WKUI is set
722            pub const Disabled: u32 = 0b0;
723
724            /// 0b1: Interrupt generated when WKUI bit is set
725            pub const Enabled: u32 = 0b1;
726        }
727    }
728
729    /// ERRIE
730    pub mod ERRIE {
731        /// Offset (15 bits)
732        pub const offset: u32 = 15;
733        /// Mask (1 bit: 1 << 15)
734        pub const mask: u32 = 1 << offset;
735        /// Read-only values (empty)
736        pub mod R {}
737        /// Write-only values (empty)
738        pub mod W {}
739        /// Read-write values
740        pub mod RW {
741
742            /// 0b0: No interrupt will be generated when an error condition is pending in the CAN_ESR
743            pub const Disabled: u32 = 0b0;
744
745            /// 0b1: An interrupt will be generation when an error condition is pending in the CAN_ESR
746            pub const Enabled: u32 = 0b1;
747        }
748    }
749
750    /// LECIE
751    pub mod LECIE {
752        /// Offset (11 bits)
753        pub const offset: u32 = 11;
754        /// Mask (1 bit: 1 << 11)
755        pub const mask: u32 = 1 << offset;
756        /// Read-only values (empty)
757        pub mod R {}
758        /// Write-only values (empty)
759        pub mod W {}
760        /// Read-write values
761        pub mod RW {
762
763            /// 0b0: ERRI bit will not be set when the error code in LEC\[2:0\] is set by hardware on error detection
764            pub const Disabled: u32 = 0b0;
765
766            /// 0b1: ERRI bit will be set when the error code in LEC\[2:0\] is set by hardware on error detection
767            pub const Enabled: u32 = 0b1;
768        }
769    }
770
771    /// BOFIE
772    pub mod BOFIE {
773        /// Offset (10 bits)
774        pub const offset: u32 = 10;
775        /// Mask (1 bit: 1 << 10)
776        pub const mask: u32 = 1 << offset;
777        /// Read-only values (empty)
778        pub mod R {}
779        /// Write-only values (empty)
780        pub mod W {}
781        /// Read-write values
782        pub mod RW {
783
784            /// 0b0: ERRI bit will not be set when BOFF is set
785            pub const Disabled: u32 = 0b0;
786
787            /// 0b1: ERRI bit will be set when BOFF is set
788            pub const Enabled: u32 = 0b1;
789        }
790    }
791
792    /// EPVIE
793    pub mod EPVIE {
794        /// Offset (9 bits)
795        pub const offset: u32 = 9;
796        /// Mask (1 bit: 1 << 9)
797        pub const mask: u32 = 1 << offset;
798        /// Read-only values (empty)
799        pub mod R {}
800        /// Write-only values (empty)
801        pub mod W {}
802        /// Read-write values
803        pub mod RW {
804
805            /// 0b0: ERRI bit will not be set when EPVF is set
806            pub const Disabled: u32 = 0b0;
807
808            /// 0b1: ERRI bit will be set when EPVF is set
809            pub const Enabled: u32 = 0b1;
810        }
811    }
812
813    /// EWGIE
814    pub mod EWGIE {
815        /// Offset (8 bits)
816        pub const offset: u32 = 8;
817        /// Mask (1 bit: 1 << 8)
818        pub const mask: u32 = 1 << offset;
819        /// Read-only values (empty)
820        pub mod R {}
821        /// Write-only values (empty)
822        pub mod W {}
823        /// Read-write values
824        pub mod RW {
825
826            /// 0b0: ERRI bit will not be set when EWGF is set
827            pub const Disabled: u32 = 0b0;
828
829            /// 0b1: ERRI bit will be set when EWGF is set
830            pub const Enabled: u32 = 0b1;
831        }
832    }
833
834    /// FOVIE1
835    pub mod FOVIE1 {
836        /// Offset (6 bits)
837        pub const offset: u32 = 6;
838        /// Mask (1 bit: 1 << 6)
839        pub const mask: u32 = 1 << offset;
840        /// Read-only values (empty)
841        pub mod R {}
842        /// Write-only values (empty)
843        pub mod W {}
844        /// Read-write values
845        pub mod RW {
846
847            /// 0b0: No interrupt when FOVR is set
848            pub const Disabled: u32 = 0b0;
849
850            /// 0b1: Interrupt generation when FOVR is set
851            pub const Enabled: u32 = 0b1;
852        }
853    }
854
855    /// FFIE1
856    pub mod FFIE1 {
857        /// Offset (5 bits)
858        pub const offset: u32 = 5;
859        /// Mask (1 bit: 1 << 5)
860        pub const mask: u32 = 1 << offset;
861        /// Read-only values (empty)
862        pub mod R {}
863        /// Write-only values (empty)
864        pub mod W {}
865        /// Read-write values
866        pub mod RW {
867
868            /// 0b0: No interrupt when FULL bit is set
869            pub const Disabled: u32 = 0b0;
870
871            /// 0b1: Interrupt generated when FULL bit is set
872            pub const Enabled: u32 = 0b1;
873        }
874    }
875
876    /// FMPIE1
877    pub mod FMPIE1 {
878        /// Offset (4 bits)
879        pub const offset: u32 = 4;
880        /// Mask (1 bit: 1 << 4)
881        pub const mask: u32 = 1 << offset;
882        /// Read-only values (empty)
883        pub mod R {}
884        /// Write-only values (empty)
885        pub mod W {}
886        /// Read-write values
887        pub mod RW {
888
889            /// 0b0: No interrupt generated when state of FMP\[1:0\] bits are not 00b
890            pub const Disabled: u32 = 0b0;
891
892            /// 0b1: Interrupt generated when state of FMP\[1:0\] bits are not 00b
893            pub const Enabled: u32 = 0b1;
894        }
895    }
896
897    /// FOVIE0
898    pub mod FOVIE0 {
899        /// Offset (3 bits)
900        pub const offset: u32 = 3;
901        /// Mask (1 bit: 1 << 3)
902        pub const mask: u32 = 1 << offset;
903        /// Read-only values (empty)
904        pub mod R {}
905        /// Write-only values (empty)
906        pub mod W {}
907        /// Read-write values
908        pub mod RW {
909
910            /// 0b0: No interrupt when FOVR bit is set
911            pub const Disabled: u32 = 0b0;
912
913            /// 0b1: Interrupt generated when FOVR bit is set
914            pub const Enabled: u32 = 0b1;
915        }
916    }
917
918    /// FFIE0
919    pub mod FFIE0 {
920        /// Offset (2 bits)
921        pub const offset: u32 = 2;
922        /// Mask (1 bit: 1 << 2)
923        pub const mask: u32 = 1 << offset;
924        /// Read-only values (empty)
925        pub mod R {}
926        /// Write-only values (empty)
927        pub mod W {}
928        pub use super::FFIE1::RW;
929    }
930
931    /// FMPIE0
932    pub mod FMPIE0 {
933        /// Offset (1 bits)
934        pub const offset: u32 = 1;
935        /// Mask (1 bit: 1 << 1)
936        pub const mask: u32 = 1 << offset;
937        /// Read-only values (empty)
938        pub mod R {}
939        /// Write-only values (empty)
940        pub mod W {}
941        /// Read-write values
942        pub mod RW {
943
944            /// 0b0: No interrupt generated when state of FMP\[1:0\] bits are not 00
945            pub const Disabled: u32 = 0b0;
946
947            /// 0b1: Interrupt generated when state of FMP\[1:0\] bits are not 00b
948            pub const Enabled: u32 = 0b1;
949        }
950    }
951
952    /// TMEIE
953    pub mod TMEIE {
954        /// Offset (0 bits)
955        pub const offset: u32 = 0;
956        /// Mask (1 bit: 1 << 0)
957        pub const mask: u32 = 1 << offset;
958        /// Read-only values (empty)
959        pub mod R {}
960        /// Write-only values (empty)
961        pub mod W {}
962        /// Read-write values
963        pub mod RW {
964
965            /// 0b0: No interrupt when RQCPx bit is set
966            pub const Disabled: u32 = 0b0;
967
968            /// 0b1: Interrupt generated when RQCPx bit is set
969            pub const Enabled: u32 = 0b1;
970        }
971    }
972}
973
974/// interrupt enable register
975pub mod ESR {
976
977    /// REC
978    pub mod REC {
979        /// Offset (24 bits)
980        pub const offset: u32 = 24;
981        /// Mask (8 bits: 0xff << 24)
982        pub const mask: u32 = 0xff << offset;
983        /// Read-only values (empty)
984        pub mod R {}
985        /// Write-only values (empty)
986        pub mod W {}
987        /// Read-write values (empty)
988        pub mod RW {}
989    }
990
991    /// TEC
992    pub mod TEC {
993        /// Offset (16 bits)
994        pub const offset: u32 = 16;
995        /// Mask (8 bits: 0xff << 16)
996        pub const mask: u32 = 0xff << offset;
997        /// Read-only values (empty)
998        pub mod R {}
999        /// Write-only values (empty)
1000        pub mod W {}
1001        /// Read-write values (empty)
1002        pub mod RW {}
1003    }
1004
1005    /// LEC
1006    pub mod LEC {
1007        /// Offset (4 bits)
1008        pub const offset: u32 = 4;
1009        /// Mask (3 bits: 0b111 << 4)
1010        pub const mask: u32 = 0b111 << offset;
1011        /// Read-only values (empty)
1012        pub mod R {}
1013        /// Write-only values (empty)
1014        pub mod W {}
1015        /// Read-write values
1016        pub mod RW {
1017
1018            /// 0b000: No Error
1019            pub const NoError: u32 = 0b000;
1020
1021            /// 0b001: Stuff Error
1022            pub const Stuff: u32 = 0b001;
1023
1024            /// 0b010: Form Error
1025            pub const Form: u32 = 0b010;
1026
1027            /// 0b011: Acknowledgment Error
1028            pub const Ack: u32 = 0b011;
1029
1030            /// 0b100: Bit recessive Error
1031            pub const BitRecessive: u32 = 0b100;
1032
1033            /// 0b101: Bit dominant Error
1034            pub const BitDominant: u32 = 0b101;
1035
1036            /// 0b110: CRC Error
1037            pub const Crc: u32 = 0b110;
1038
1039            /// 0b111: Set by software
1040            pub const Custom: u32 = 0b111;
1041        }
1042    }
1043
1044    /// BOFF
1045    pub mod BOFF {
1046        /// Offset (2 bits)
1047        pub const offset: u32 = 2;
1048        /// Mask (1 bit: 1 << 2)
1049        pub const mask: u32 = 1 << offset;
1050        /// Read-only values (empty)
1051        pub mod R {}
1052        /// Write-only values (empty)
1053        pub mod W {}
1054        /// Read-write values (empty)
1055        pub mod RW {}
1056    }
1057
1058    /// EPVF
1059    pub mod EPVF {
1060        /// Offset (1 bits)
1061        pub const offset: u32 = 1;
1062        /// Mask (1 bit: 1 << 1)
1063        pub const mask: u32 = 1 << offset;
1064        /// Read-only values (empty)
1065        pub mod R {}
1066        /// Write-only values (empty)
1067        pub mod W {}
1068        /// Read-write values (empty)
1069        pub mod RW {}
1070    }
1071
1072    /// EWGF
1073    pub mod EWGF {
1074        /// Offset (0 bits)
1075        pub const offset: u32 = 0;
1076        /// Mask (1 bit: 1 << 0)
1077        pub const mask: u32 = 1 << offset;
1078        /// Read-only values (empty)
1079        pub mod R {}
1080        /// Write-only values (empty)
1081        pub mod W {}
1082        /// Read-write values (empty)
1083        pub mod RW {}
1084    }
1085}
1086
1087/// bit timing register
1088pub mod BTR {
1089
1090    /// SILM
1091    pub mod SILM {
1092        /// Offset (31 bits)
1093        pub const offset: u32 = 31;
1094        /// Mask (1 bit: 1 << 31)
1095        pub const mask: u32 = 1 << offset;
1096        /// Read-only values (empty)
1097        pub mod R {}
1098        /// Write-only values (empty)
1099        pub mod W {}
1100        /// Read-write values
1101        pub mod RW {
1102
1103            /// 0b0: Normal operation
1104            pub const Normal: u32 = 0b0;
1105
1106            /// 0b1: Silent Mode
1107            pub const Silent: u32 = 0b1;
1108        }
1109    }
1110
1111    /// LBKM
1112    pub mod LBKM {
1113        /// Offset (30 bits)
1114        pub const offset: u32 = 30;
1115        /// Mask (1 bit: 1 << 30)
1116        pub const mask: u32 = 1 << offset;
1117        /// Read-only values (empty)
1118        pub mod R {}
1119        /// Write-only values (empty)
1120        pub mod W {}
1121        /// Read-write values
1122        pub mod RW {
1123
1124            /// 0b0: Loop Back Mode disabled
1125            pub const Disabled: u32 = 0b0;
1126
1127            /// 0b1: Loop Back Mode enabled
1128            pub const Enabled: u32 = 0b1;
1129        }
1130    }
1131
1132    /// SJW
1133    pub mod SJW {
1134        /// Offset (24 bits)
1135        pub const offset: u32 = 24;
1136        /// Mask (2 bits: 0b11 << 24)
1137        pub const mask: u32 = 0b11 << offset;
1138        /// Read-only values (empty)
1139        pub mod R {}
1140        /// Write-only values (empty)
1141        pub mod W {}
1142        /// Read-write values (empty)
1143        pub mod RW {}
1144    }
1145
1146    /// TS2
1147    pub mod TS2 {
1148        /// Offset (20 bits)
1149        pub const offset: u32 = 20;
1150        /// Mask (3 bits: 0b111 << 20)
1151        pub const mask: u32 = 0b111 << offset;
1152        /// Read-only values (empty)
1153        pub mod R {}
1154        /// Write-only values (empty)
1155        pub mod W {}
1156        /// Read-write values (empty)
1157        pub mod RW {}
1158    }
1159
1160    /// TS1
1161    pub mod TS1 {
1162        /// Offset (16 bits)
1163        pub const offset: u32 = 16;
1164        /// Mask (4 bits: 0b1111 << 16)
1165        pub const mask: u32 = 0b1111 << offset;
1166        /// Read-only values (empty)
1167        pub mod R {}
1168        /// Write-only values (empty)
1169        pub mod W {}
1170        /// Read-write values (empty)
1171        pub mod RW {}
1172    }
1173
1174    /// BRP
1175    pub mod BRP {
1176        /// Offset (0 bits)
1177        pub const offset: u32 = 0;
1178        /// Mask (10 bits: 0x3ff << 0)
1179        pub const mask: u32 = 0x3ff << offset;
1180        /// Read-only values (empty)
1181        pub mod R {}
1182        /// Write-only values (empty)
1183        pub mod W {}
1184        /// Read-write values (empty)
1185        pub mod RW {}
1186    }
1187}
1188
1189/// filter master register
1190pub mod FMR {
1191
1192    /// CAN2SB
1193    pub mod CAN2SB {
1194        /// Offset (8 bits)
1195        pub const offset: u32 = 8;
1196        /// Mask (6 bits: 0x3f << 8)
1197        pub const mask: u32 = 0x3f << offset;
1198        /// Read-only values (empty)
1199        pub mod R {}
1200        /// Write-only values (empty)
1201        pub mod W {}
1202        /// Read-write values (empty)
1203        pub mod RW {}
1204    }
1205
1206    /// FINIT
1207    pub mod FINIT {
1208        /// Offset (0 bits)
1209        pub const offset: u32 = 0;
1210        /// Mask (1 bit: 1 << 0)
1211        pub const mask: u32 = 1 << offset;
1212        /// Read-only values (empty)
1213        pub mod R {}
1214        /// Write-only values (empty)
1215        pub mod W {}
1216        /// Read-write values (empty)
1217        pub mod RW {}
1218    }
1219}
1220
1221/// filter mode register
1222pub mod FM1R {
1223
1224    /// Filter mode
1225    pub mod FBM0 {
1226        /// Offset (0 bits)
1227        pub const offset: u32 = 0;
1228        /// Mask (1 bit: 1 << 0)
1229        pub const mask: u32 = 1 << offset;
1230        /// Read-only values (empty)
1231        pub mod R {}
1232        /// Write-only values (empty)
1233        pub mod W {}
1234        /// Read-write values (empty)
1235        pub mod RW {}
1236    }
1237
1238    /// Filter mode
1239    pub mod FBM1 {
1240        /// Offset (1 bits)
1241        pub const offset: u32 = 1;
1242        /// Mask (1 bit: 1 << 1)
1243        pub const mask: u32 = 1 << offset;
1244        /// Read-only values (empty)
1245        pub mod R {}
1246        /// Write-only values (empty)
1247        pub mod W {}
1248        /// Read-write values (empty)
1249        pub mod RW {}
1250    }
1251
1252    /// Filter mode
1253    pub mod FBM2 {
1254        /// Offset (2 bits)
1255        pub const offset: u32 = 2;
1256        /// Mask (1 bit: 1 << 2)
1257        pub const mask: u32 = 1 << offset;
1258        /// Read-only values (empty)
1259        pub mod R {}
1260        /// Write-only values (empty)
1261        pub mod W {}
1262        /// Read-write values (empty)
1263        pub mod RW {}
1264    }
1265
1266    /// Filter mode
1267    pub mod FBM3 {
1268        /// Offset (3 bits)
1269        pub const offset: u32 = 3;
1270        /// Mask (1 bit: 1 << 3)
1271        pub const mask: u32 = 1 << offset;
1272        /// Read-only values (empty)
1273        pub mod R {}
1274        /// Write-only values (empty)
1275        pub mod W {}
1276        /// Read-write values (empty)
1277        pub mod RW {}
1278    }
1279
1280    /// Filter mode
1281    pub mod FBM4 {
1282        /// Offset (4 bits)
1283        pub const offset: u32 = 4;
1284        /// Mask (1 bit: 1 << 4)
1285        pub const mask: u32 = 1 << offset;
1286        /// Read-only values (empty)
1287        pub mod R {}
1288        /// Write-only values (empty)
1289        pub mod W {}
1290        /// Read-write values (empty)
1291        pub mod RW {}
1292    }
1293
1294    /// Filter mode
1295    pub mod FBM5 {
1296        /// Offset (5 bits)
1297        pub const offset: u32 = 5;
1298        /// Mask (1 bit: 1 << 5)
1299        pub const mask: u32 = 1 << offset;
1300        /// Read-only values (empty)
1301        pub mod R {}
1302        /// Write-only values (empty)
1303        pub mod W {}
1304        /// Read-write values (empty)
1305        pub mod RW {}
1306    }
1307
1308    /// Filter mode
1309    pub mod FBM6 {
1310        /// Offset (6 bits)
1311        pub const offset: u32 = 6;
1312        /// Mask (1 bit: 1 << 6)
1313        pub const mask: u32 = 1 << offset;
1314        /// Read-only values (empty)
1315        pub mod R {}
1316        /// Write-only values (empty)
1317        pub mod W {}
1318        /// Read-write values (empty)
1319        pub mod RW {}
1320    }
1321
1322    /// Filter mode
1323    pub mod FBM7 {
1324        /// Offset (7 bits)
1325        pub const offset: u32 = 7;
1326        /// Mask (1 bit: 1 << 7)
1327        pub const mask: u32 = 1 << offset;
1328        /// Read-only values (empty)
1329        pub mod R {}
1330        /// Write-only values (empty)
1331        pub mod W {}
1332        /// Read-write values (empty)
1333        pub mod RW {}
1334    }
1335
1336    /// Filter mode
1337    pub mod FBM8 {
1338        /// Offset (8 bits)
1339        pub const offset: u32 = 8;
1340        /// Mask (1 bit: 1 << 8)
1341        pub const mask: u32 = 1 << offset;
1342        /// Read-only values (empty)
1343        pub mod R {}
1344        /// Write-only values (empty)
1345        pub mod W {}
1346        /// Read-write values (empty)
1347        pub mod RW {}
1348    }
1349
1350    /// Filter mode
1351    pub mod FBM9 {
1352        /// Offset (9 bits)
1353        pub const offset: u32 = 9;
1354        /// Mask (1 bit: 1 << 9)
1355        pub const mask: u32 = 1 << offset;
1356        /// Read-only values (empty)
1357        pub mod R {}
1358        /// Write-only values (empty)
1359        pub mod W {}
1360        /// Read-write values (empty)
1361        pub mod RW {}
1362    }
1363
1364    /// Filter mode
1365    pub mod FBM10 {
1366        /// Offset (10 bits)
1367        pub const offset: u32 = 10;
1368        /// Mask (1 bit: 1 << 10)
1369        pub const mask: u32 = 1 << offset;
1370        /// Read-only values (empty)
1371        pub mod R {}
1372        /// Write-only values (empty)
1373        pub mod W {}
1374        /// Read-write values (empty)
1375        pub mod RW {}
1376    }
1377
1378    /// Filter mode
1379    pub mod FBM11 {
1380        /// Offset (11 bits)
1381        pub const offset: u32 = 11;
1382        /// Mask (1 bit: 1 << 11)
1383        pub const mask: u32 = 1 << offset;
1384        /// Read-only values (empty)
1385        pub mod R {}
1386        /// Write-only values (empty)
1387        pub mod W {}
1388        /// Read-write values (empty)
1389        pub mod RW {}
1390    }
1391
1392    /// Filter mode
1393    pub mod FBM12 {
1394        /// Offset (12 bits)
1395        pub const offset: u32 = 12;
1396        /// Mask (1 bit: 1 << 12)
1397        pub const mask: u32 = 1 << offset;
1398        /// Read-only values (empty)
1399        pub mod R {}
1400        /// Write-only values (empty)
1401        pub mod W {}
1402        /// Read-write values (empty)
1403        pub mod RW {}
1404    }
1405
1406    /// Filter mode
1407    pub mod FBM13 {
1408        /// Offset (13 bits)
1409        pub const offset: u32 = 13;
1410        /// Mask (1 bit: 1 << 13)
1411        pub const mask: u32 = 1 << offset;
1412        /// Read-only values (empty)
1413        pub mod R {}
1414        /// Write-only values (empty)
1415        pub mod W {}
1416        /// Read-write values (empty)
1417        pub mod RW {}
1418    }
1419
1420    /// Filter mode
1421    pub mod FBM14 {
1422        /// Offset (14 bits)
1423        pub const offset: u32 = 14;
1424        /// Mask (1 bit: 1 << 14)
1425        pub const mask: u32 = 1 << offset;
1426        /// Read-only values (empty)
1427        pub mod R {}
1428        /// Write-only values (empty)
1429        pub mod W {}
1430        /// Read-write values (empty)
1431        pub mod RW {}
1432    }
1433
1434    /// Filter mode
1435    pub mod FBM15 {
1436        /// Offset (15 bits)
1437        pub const offset: u32 = 15;
1438        /// Mask (1 bit: 1 << 15)
1439        pub const mask: u32 = 1 << offset;
1440        /// Read-only values (empty)
1441        pub mod R {}
1442        /// Write-only values (empty)
1443        pub mod W {}
1444        /// Read-write values (empty)
1445        pub mod RW {}
1446    }
1447
1448    /// Filter mode
1449    pub mod FBM16 {
1450        /// Offset (16 bits)
1451        pub const offset: u32 = 16;
1452        /// Mask (1 bit: 1 << 16)
1453        pub const mask: u32 = 1 << offset;
1454        /// Read-only values (empty)
1455        pub mod R {}
1456        /// Write-only values (empty)
1457        pub mod W {}
1458        /// Read-write values (empty)
1459        pub mod RW {}
1460    }
1461
1462    /// Filter mode
1463    pub mod FBM17 {
1464        /// Offset (17 bits)
1465        pub const offset: u32 = 17;
1466        /// Mask (1 bit: 1 << 17)
1467        pub const mask: u32 = 1 << offset;
1468        /// Read-only values (empty)
1469        pub mod R {}
1470        /// Write-only values (empty)
1471        pub mod W {}
1472        /// Read-write values (empty)
1473        pub mod RW {}
1474    }
1475
1476    /// Filter mode
1477    pub mod FBM18 {
1478        /// Offset (18 bits)
1479        pub const offset: u32 = 18;
1480        /// Mask (1 bit: 1 << 18)
1481        pub const mask: u32 = 1 << offset;
1482        /// Read-only values (empty)
1483        pub mod R {}
1484        /// Write-only values (empty)
1485        pub mod W {}
1486        /// Read-write values (empty)
1487        pub mod RW {}
1488    }
1489
1490    /// Filter mode
1491    pub mod FBM19 {
1492        /// Offset (19 bits)
1493        pub const offset: u32 = 19;
1494        /// Mask (1 bit: 1 << 19)
1495        pub const mask: u32 = 1 << offset;
1496        /// Read-only values (empty)
1497        pub mod R {}
1498        /// Write-only values (empty)
1499        pub mod W {}
1500        /// Read-write values (empty)
1501        pub mod RW {}
1502    }
1503
1504    /// Filter mode
1505    pub mod FBM20 {
1506        /// Offset (20 bits)
1507        pub const offset: u32 = 20;
1508        /// Mask (1 bit: 1 << 20)
1509        pub const mask: u32 = 1 << offset;
1510        /// Read-only values (empty)
1511        pub mod R {}
1512        /// Write-only values (empty)
1513        pub mod W {}
1514        /// Read-write values (empty)
1515        pub mod RW {}
1516    }
1517
1518    /// Filter mode
1519    pub mod FBM21 {
1520        /// Offset (21 bits)
1521        pub const offset: u32 = 21;
1522        /// Mask (1 bit: 1 << 21)
1523        pub const mask: u32 = 1 << offset;
1524        /// Read-only values (empty)
1525        pub mod R {}
1526        /// Write-only values (empty)
1527        pub mod W {}
1528        /// Read-write values (empty)
1529        pub mod RW {}
1530    }
1531
1532    /// Filter mode
1533    pub mod FBM22 {
1534        /// Offset (22 bits)
1535        pub const offset: u32 = 22;
1536        /// Mask (1 bit: 1 << 22)
1537        pub const mask: u32 = 1 << offset;
1538        /// Read-only values (empty)
1539        pub mod R {}
1540        /// Write-only values (empty)
1541        pub mod W {}
1542        /// Read-write values (empty)
1543        pub mod RW {}
1544    }
1545
1546    /// Filter mode
1547    pub mod FBM23 {
1548        /// Offset (23 bits)
1549        pub const offset: u32 = 23;
1550        /// Mask (1 bit: 1 << 23)
1551        pub const mask: u32 = 1 << offset;
1552        /// Read-only values (empty)
1553        pub mod R {}
1554        /// Write-only values (empty)
1555        pub mod W {}
1556        /// Read-write values (empty)
1557        pub mod RW {}
1558    }
1559
1560    /// Filter mode
1561    pub mod FBM24 {
1562        /// Offset (24 bits)
1563        pub const offset: u32 = 24;
1564        /// Mask (1 bit: 1 << 24)
1565        pub const mask: u32 = 1 << offset;
1566        /// Read-only values (empty)
1567        pub mod R {}
1568        /// Write-only values (empty)
1569        pub mod W {}
1570        /// Read-write values (empty)
1571        pub mod RW {}
1572    }
1573
1574    /// Filter mode
1575    pub mod FBM25 {
1576        /// Offset (25 bits)
1577        pub const offset: u32 = 25;
1578        /// Mask (1 bit: 1 << 25)
1579        pub const mask: u32 = 1 << offset;
1580        /// Read-only values (empty)
1581        pub mod R {}
1582        /// Write-only values (empty)
1583        pub mod W {}
1584        /// Read-write values (empty)
1585        pub mod RW {}
1586    }
1587
1588    /// Filter mode
1589    pub mod FBM26 {
1590        /// Offset (26 bits)
1591        pub const offset: u32 = 26;
1592        /// Mask (1 bit: 1 << 26)
1593        pub const mask: u32 = 1 << offset;
1594        /// Read-only values (empty)
1595        pub mod R {}
1596        /// Write-only values (empty)
1597        pub mod W {}
1598        /// Read-write values (empty)
1599        pub mod RW {}
1600    }
1601
1602    /// Filter mode
1603    pub mod FBM27 {
1604        /// Offset (27 bits)
1605        pub const offset: u32 = 27;
1606        /// Mask (1 bit: 1 << 27)
1607        pub const mask: u32 = 1 << offset;
1608        /// Read-only values (empty)
1609        pub mod R {}
1610        /// Write-only values (empty)
1611        pub mod W {}
1612        /// Read-write values (empty)
1613        pub mod RW {}
1614    }
1615}
1616
1617/// filter scale register
1618pub mod FS1R {
1619
1620    /// Filter scale configuration
1621    pub mod FSC0 {
1622        /// Offset (0 bits)
1623        pub const offset: u32 = 0;
1624        /// Mask (1 bit: 1 << 0)
1625        pub const mask: u32 = 1 << offset;
1626        /// Read-only values (empty)
1627        pub mod R {}
1628        /// Write-only values (empty)
1629        pub mod W {}
1630        /// Read-write values (empty)
1631        pub mod RW {}
1632    }
1633
1634    /// Filter scale configuration
1635    pub mod FSC1 {
1636        /// Offset (1 bits)
1637        pub const offset: u32 = 1;
1638        /// Mask (1 bit: 1 << 1)
1639        pub const mask: u32 = 1 << offset;
1640        /// Read-only values (empty)
1641        pub mod R {}
1642        /// Write-only values (empty)
1643        pub mod W {}
1644        /// Read-write values (empty)
1645        pub mod RW {}
1646    }
1647
1648    /// Filter scale configuration
1649    pub mod FSC2 {
1650        /// Offset (2 bits)
1651        pub const offset: u32 = 2;
1652        /// Mask (1 bit: 1 << 2)
1653        pub const mask: u32 = 1 << offset;
1654        /// Read-only values (empty)
1655        pub mod R {}
1656        /// Write-only values (empty)
1657        pub mod W {}
1658        /// Read-write values (empty)
1659        pub mod RW {}
1660    }
1661
1662    /// Filter scale configuration
1663    pub mod FSC3 {
1664        /// Offset (3 bits)
1665        pub const offset: u32 = 3;
1666        /// Mask (1 bit: 1 << 3)
1667        pub const mask: u32 = 1 << offset;
1668        /// Read-only values (empty)
1669        pub mod R {}
1670        /// Write-only values (empty)
1671        pub mod W {}
1672        /// Read-write values (empty)
1673        pub mod RW {}
1674    }
1675
1676    /// Filter scale configuration
1677    pub mod FSC4 {
1678        /// Offset (4 bits)
1679        pub const offset: u32 = 4;
1680        /// Mask (1 bit: 1 << 4)
1681        pub const mask: u32 = 1 << offset;
1682        /// Read-only values (empty)
1683        pub mod R {}
1684        /// Write-only values (empty)
1685        pub mod W {}
1686        /// Read-write values (empty)
1687        pub mod RW {}
1688    }
1689
1690    /// Filter scale configuration
1691    pub mod FSC5 {
1692        /// Offset (5 bits)
1693        pub const offset: u32 = 5;
1694        /// Mask (1 bit: 1 << 5)
1695        pub const mask: u32 = 1 << offset;
1696        /// Read-only values (empty)
1697        pub mod R {}
1698        /// Write-only values (empty)
1699        pub mod W {}
1700        /// Read-write values (empty)
1701        pub mod RW {}
1702    }
1703
1704    /// Filter scale configuration
1705    pub mod FSC6 {
1706        /// Offset (6 bits)
1707        pub const offset: u32 = 6;
1708        /// Mask (1 bit: 1 << 6)
1709        pub const mask: u32 = 1 << offset;
1710        /// Read-only values (empty)
1711        pub mod R {}
1712        /// Write-only values (empty)
1713        pub mod W {}
1714        /// Read-write values (empty)
1715        pub mod RW {}
1716    }
1717
1718    /// Filter scale configuration
1719    pub mod FSC7 {
1720        /// Offset (7 bits)
1721        pub const offset: u32 = 7;
1722        /// Mask (1 bit: 1 << 7)
1723        pub const mask: u32 = 1 << offset;
1724        /// Read-only values (empty)
1725        pub mod R {}
1726        /// Write-only values (empty)
1727        pub mod W {}
1728        /// Read-write values (empty)
1729        pub mod RW {}
1730    }
1731
1732    /// Filter scale configuration
1733    pub mod FSC8 {
1734        /// Offset (8 bits)
1735        pub const offset: u32 = 8;
1736        /// Mask (1 bit: 1 << 8)
1737        pub const mask: u32 = 1 << offset;
1738        /// Read-only values (empty)
1739        pub mod R {}
1740        /// Write-only values (empty)
1741        pub mod W {}
1742        /// Read-write values (empty)
1743        pub mod RW {}
1744    }
1745
1746    /// Filter scale configuration
1747    pub mod FSC9 {
1748        /// Offset (9 bits)
1749        pub const offset: u32 = 9;
1750        /// Mask (1 bit: 1 << 9)
1751        pub const mask: u32 = 1 << offset;
1752        /// Read-only values (empty)
1753        pub mod R {}
1754        /// Write-only values (empty)
1755        pub mod W {}
1756        /// Read-write values (empty)
1757        pub mod RW {}
1758    }
1759
1760    /// Filter scale configuration
1761    pub mod FSC10 {
1762        /// Offset (10 bits)
1763        pub const offset: u32 = 10;
1764        /// Mask (1 bit: 1 << 10)
1765        pub const mask: u32 = 1 << offset;
1766        /// Read-only values (empty)
1767        pub mod R {}
1768        /// Write-only values (empty)
1769        pub mod W {}
1770        /// Read-write values (empty)
1771        pub mod RW {}
1772    }
1773
1774    /// Filter scale configuration
1775    pub mod FSC11 {
1776        /// Offset (11 bits)
1777        pub const offset: u32 = 11;
1778        /// Mask (1 bit: 1 << 11)
1779        pub const mask: u32 = 1 << offset;
1780        /// Read-only values (empty)
1781        pub mod R {}
1782        /// Write-only values (empty)
1783        pub mod W {}
1784        /// Read-write values (empty)
1785        pub mod RW {}
1786    }
1787
1788    /// Filter scale configuration
1789    pub mod FSC12 {
1790        /// Offset (12 bits)
1791        pub const offset: u32 = 12;
1792        /// Mask (1 bit: 1 << 12)
1793        pub const mask: u32 = 1 << offset;
1794        /// Read-only values (empty)
1795        pub mod R {}
1796        /// Write-only values (empty)
1797        pub mod W {}
1798        /// Read-write values (empty)
1799        pub mod RW {}
1800    }
1801
1802    /// Filter scale configuration
1803    pub mod FSC13 {
1804        /// Offset (13 bits)
1805        pub const offset: u32 = 13;
1806        /// Mask (1 bit: 1 << 13)
1807        pub const mask: u32 = 1 << offset;
1808        /// Read-only values (empty)
1809        pub mod R {}
1810        /// Write-only values (empty)
1811        pub mod W {}
1812        /// Read-write values (empty)
1813        pub mod RW {}
1814    }
1815
1816    /// Filter scale configuration
1817    pub mod FSC14 {
1818        /// Offset (14 bits)
1819        pub const offset: u32 = 14;
1820        /// Mask (1 bit: 1 << 14)
1821        pub const mask: u32 = 1 << offset;
1822        /// Read-only values (empty)
1823        pub mod R {}
1824        /// Write-only values (empty)
1825        pub mod W {}
1826        /// Read-write values (empty)
1827        pub mod RW {}
1828    }
1829
1830    /// Filter scale configuration
1831    pub mod FSC15 {
1832        /// Offset (15 bits)
1833        pub const offset: u32 = 15;
1834        /// Mask (1 bit: 1 << 15)
1835        pub const mask: u32 = 1 << offset;
1836        /// Read-only values (empty)
1837        pub mod R {}
1838        /// Write-only values (empty)
1839        pub mod W {}
1840        /// Read-write values (empty)
1841        pub mod RW {}
1842    }
1843
1844    /// Filter scale configuration
1845    pub mod FSC16 {
1846        /// Offset (16 bits)
1847        pub const offset: u32 = 16;
1848        /// Mask (1 bit: 1 << 16)
1849        pub const mask: u32 = 1 << offset;
1850        /// Read-only values (empty)
1851        pub mod R {}
1852        /// Write-only values (empty)
1853        pub mod W {}
1854        /// Read-write values (empty)
1855        pub mod RW {}
1856    }
1857
1858    /// Filter scale configuration
1859    pub mod FSC17 {
1860        /// Offset (17 bits)
1861        pub const offset: u32 = 17;
1862        /// Mask (1 bit: 1 << 17)
1863        pub const mask: u32 = 1 << offset;
1864        /// Read-only values (empty)
1865        pub mod R {}
1866        /// Write-only values (empty)
1867        pub mod W {}
1868        /// Read-write values (empty)
1869        pub mod RW {}
1870    }
1871
1872    /// Filter scale configuration
1873    pub mod FSC18 {
1874        /// Offset (18 bits)
1875        pub const offset: u32 = 18;
1876        /// Mask (1 bit: 1 << 18)
1877        pub const mask: u32 = 1 << offset;
1878        /// Read-only values (empty)
1879        pub mod R {}
1880        /// Write-only values (empty)
1881        pub mod W {}
1882        /// Read-write values (empty)
1883        pub mod RW {}
1884    }
1885
1886    /// Filter scale configuration
1887    pub mod FSC19 {
1888        /// Offset (19 bits)
1889        pub const offset: u32 = 19;
1890        /// Mask (1 bit: 1 << 19)
1891        pub const mask: u32 = 1 << offset;
1892        /// Read-only values (empty)
1893        pub mod R {}
1894        /// Write-only values (empty)
1895        pub mod W {}
1896        /// Read-write values (empty)
1897        pub mod RW {}
1898    }
1899
1900    /// Filter scale configuration
1901    pub mod FSC20 {
1902        /// Offset (20 bits)
1903        pub const offset: u32 = 20;
1904        /// Mask (1 bit: 1 << 20)
1905        pub const mask: u32 = 1 << offset;
1906        /// Read-only values (empty)
1907        pub mod R {}
1908        /// Write-only values (empty)
1909        pub mod W {}
1910        /// Read-write values (empty)
1911        pub mod RW {}
1912    }
1913
1914    /// Filter scale configuration
1915    pub mod FSC21 {
1916        /// Offset (21 bits)
1917        pub const offset: u32 = 21;
1918        /// Mask (1 bit: 1 << 21)
1919        pub const mask: u32 = 1 << offset;
1920        /// Read-only values (empty)
1921        pub mod R {}
1922        /// Write-only values (empty)
1923        pub mod W {}
1924        /// Read-write values (empty)
1925        pub mod RW {}
1926    }
1927
1928    /// Filter scale configuration
1929    pub mod FSC22 {
1930        /// Offset (22 bits)
1931        pub const offset: u32 = 22;
1932        /// Mask (1 bit: 1 << 22)
1933        pub const mask: u32 = 1 << offset;
1934        /// Read-only values (empty)
1935        pub mod R {}
1936        /// Write-only values (empty)
1937        pub mod W {}
1938        /// Read-write values (empty)
1939        pub mod RW {}
1940    }
1941
1942    /// Filter scale configuration
1943    pub mod FSC23 {
1944        /// Offset (23 bits)
1945        pub const offset: u32 = 23;
1946        /// Mask (1 bit: 1 << 23)
1947        pub const mask: u32 = 1 << offset;
1948        /// Read-only values (empty)
1949        pub mod R {}
1950        /// Write-only values (empty)
1951        pub mod W {}
1952        /// Read-write values (empty)
1953        pub mod RW {}
1954    }
1955
1956    /// Filter scale configuration
1957    pub mod FSC24 {
1958        /// Offset (24 bits)
1959        pub const offset: u32 = 24;
1960        /// Mask (1 bit: 1 << 24)
1961        pub const mask: u32 = 1 << offset;
1962        /// Read-only values (empty)
1963        pub mod R {}
1964        /// Write-only values (empty)
1965        pub mod W {}
1966        /// Read-write values (empty)
1967        pub mod RW {}
1968    }
1969
1970    /// Filter scale configuration
1971    pub mod FSC25 {
1972        /// Offset (25 bits)
1973        pub const offset: u32 = 25;
1974        /// Mask (1 bit: 1 << 25)
1975        pub const mask: u32 = 1 << offset;
1976        /// Read-only values (empty)
1977        pub mod R {}
1978        /// Write-only values (empty)
1979        pub mod W {}
1980        /// Read-write values (empty)
1981        pub mod RW {}
1982    }
1983
1984    /// Filter scale configuration
1985    pub mod FSC26 {
1986        /// Offset (26 bits)
1987        pub const offset: u32 = 26;
1988        /// Mask (1 bit: 1 << 26)
1989        pub const mask: u32 = 1 << offset;
1990        /// Read-only values (empty)
1991        pub mod R {}
1992        /// Write-only values (empty)
1993        pub mod W {}
1994        /// Read-write values (empty)
1995        pub mod RW {}
1996    }
1997
1998    /// Filter scale configuration
1999    pub mod FSC27 {
2000        /// Offset (27 bits)
2001        pub const offset: u32 = 27;
2002        /// Mask (1 bit: 1 << 27)
2003        pub const mask: u32 = 1 << offset;
2004        /// Read-only values (empty)
2005        pub mod R {}
2006        /// Write-only values (empty)
2007        pub mod W {}
2008        /// Read-write values (empty)
2009        pub mod RW {}
2010    }
2011}
2012
2013/// filter FIFO assignment register
2014pub mod FFA1R {
2015
2016    /// Filter FIFO assignment for filter 0
2017    pub mod FFA0 {
2018        /// Offset (0 bits)
2019        pub const offset: u32 = 0;
2020        /// Mask (1 bit: 1 << 0)
2021        pub const mask: u32 = 1 << offset;
2022        /// Read-only values (empty)
2023        pub mod R {}
2024        /// Write-only values (empty)
2025        pub mod W {}
2026        /// Read-write values (empty)
2027        pub mod RW {}
2028    }
2029
2030    /// Filter FIFO assignment for filter 1
2031    pub mod FFA1 {
2032        /// Offset (1 bits)
2033        pub const offset: u32 = 1;
2034        /// Mask (1 bit: 1 << 1)
2035        pub const mask: u32 = 1 << offset;
2036        /// Read-only values (empty)
2037        pub mod R {}
2038        /// Write-only values (empty)
2039        pub mod W {}
2040        /// Read-write values (empty)
2041        pub mod RW {}
2042    }
2043
2044    /// Filter FIFO assignment for filter 2
2045    pub mod FFA2 {
2046        /// Offset (2 bits)
2047        pub const offset: u32 = 2;
2048        /// Mask (1 bit: 1 << 2)
2049        pub const mask: u32 = 1 << offset;
2050        /// Read-only values (empty)
2051        pub mod R {}
2052        /// Write-only values (empty)
2053        pub mod W {}
2054        /// Read-write values (empty)
2055        pub mod RW {}
2056    }
2057
2058    /// Filter FIFO assignment for filter 3
2059    pub mod FFA3 {
2060        /// Offset (3 bits)
2061        pub const offset: u32 = 3;
2062        /// Mask (1 bit: 1 << 3)
2063        pub const mask: u32 = 1 << offset;
2064        /// Read-only values (empty)
2065        pub mod R {}
2066        /// Write-only values (empty)
2067        pub mod W {}
2068        /// Read-write values (empty)
2069        pub mod RW {}
2070    }
2071
2072    /// Filter FIFO assignment for filter 4
2073    pub mod FFA4 {
2074        /// Offset (4 bits)
2075        pub const offset: u32 = 4;
2076        /// Mask (1 bit: 1 << 4)
2077        pub const mask: u32 = 1 << offset;
2078        /// Read-only values (empty)
2079        pub mod R {}
2080        /// Write-only values (empty)
2081        pub mod W {}
2082        /// Read-write values (empty)
2083        pub mod RW {}
2084    }
2085
2086    /// Filter FIFO assignment for filter 5
2087    pub mod FFA5 {
2088        /// Offset (5 bits)
2089        pub const offset: u32 = 5;
2090        /// Mask (1 bit: 1 << 5)
2091        pub const mask: u32 = 1 << offset;
2092        /// Read-only values (empty)
2093        pub mod R {}
2094        /// Write-only values (empty)
2095        pub mod W {}
2096        /// Read-write values (empty)
2097        pub mod RW {}
2098    }
2099
2100    /// Filter FIFO assignment for filter 6
2101    pub mod FFA6 {
2102        /// Offset (6 bits)
2103        pub const offset: u32 = 6;
2104        /// Mask (1 bit: 1 << 6)
2105        pub const mask: u32 = 1 << offset;
2106        /// Read-only values (empty)
2107        pub mod R {}
2108        /// Write-only values (empty)
2109        pub mod W {}
2110        /// Read-write values (empty)
2111        pub mod RW {}
2112    }
2113
2114    /// Filter FIFO assignment for filter 7
2115    pub mod FFA7 {
2116        /// Offset (7 bits)
2117        pub const offset: u32 = 7;
2118        /// Mask (1 bit: 1 << 7)
2119        pub const mask: u32 = 1 << offset;
2120        /// Read-only values (empty)
2121        pub mod R {}
2122        /// Write-only values (empty)
2123        pub mod W {}
2124        /// Read-write values (empty)
2125        pub mod RW {}
2126    }
2127
2128    /// Filter FIFO assignment for filter 8
2129    pub mod FFA8 {
2130        /// Offset (8 bits)
2131        pub const offset: u32 = 8;
2132        /// Mask (1 bit: 1 << 8)
2133        pub const mask: u32 = 1 << offset;
2134        /// Read-only values (empty)
2135        pub mod R {}
2136        /// Write-only values (empty)
2137        pub mod W {}
2138        /// Read-write values (empty)
2139        pub mod RW {}
2140    }
2141
2142    /// Filter FIFO assignment for filter 9
2143    pub mod FFA9 {
2144        /// Offset (9 bits)
2145        pub const offset: u32 = 9;
2146        /// Mask (1 bit: 1 << 9)
2147        pub const mask: u32 = 1 << offset;
2148        /// Read-only values (empty)
2149        pub mod R {}
2150        /// Write-only values (empty)
2151        pub mod W {}
2152        /// Read-write values (empty)
2153        pub mod RW {}
2154    }
2155
2156    /// Filter FIFO assignment for filter 10
2157    pub mod FFA10 {
2158        /// Offset (10 bits)
2159        pub const offset: u32 = 10;
2160        /// Mask (1 bit: 1 << 10)
2161        pub const mask: u32 = 1 << offset;
2162        /// Read-only values (empty)
2163        pub mod R {}
2164        /// Write-only values (empty)
2165        pub mod W {}
2166        /// Read-write values (empty)
2167        pub mod RW {}
2168    }
2169
2170    /// Filter FIFO assignment for filter 11
2171    pub mod FFA11 {
2172        /// Offset (11 bits)
2173        pub const offset: u32 = 11;
2174        /// Mask (1 bit: 1 << 11)
2175        pub const mask: u32 = 1 << offset;
2176        /// Read-only values (empty)
2177        pub mod R {}
2178        /// Write-only values (empty)
2179        pub mod W {}
2180        /// Read-write values (empty)
2181        pub mod RW {}
2182    }
2183
2184    /// Filter FIFO assignment for filter 12
2185    pub mod FFA12 {
2186        /// Offset (12 bits)
2187        pub const offset: u32 = 12;
2188        /// Mask (1 bit: 1 << 12)
2189        pub const mask: u32 = 1 << offset;
2190        /// Read-only values (empty)
2191        pub mod R {}
2192        /// Write-only values (empty)
2193        pub mod W {}
2194        /// Read-write values (empty)
2195        pub mod RW {}
2196    }
2197
2198    /// Filter FIFO assignment for filter 13
2199    pub mod FFA13 {
2200        /// Offset (13 bits)
2201        pub const offset: u32 = 13;
2202        /// Mask (1 bit: 1 << 13)
2203        pub const mask: u32 = 1 << offset;
2204        /// Read-only values (empty)
2205        pub mod R {}
2206        /// Write-only values (empty)
2207        pub mod W {}
2208        /// Read-write values (empty)
2209        pub mod RW {}
2210    }
2211
2212    /// Filter FIFO assignment for filter 14
2213    pub mod FFA14 {
2214        /// Offset (14 bits)
2215        pub const offset: u32 = 14;
2216        /// Mask (1 bit: 1 << 14)
2217        pub const mask: u32 = 1 << offset;
2218        /// Read-only values (empty)
2219        pub mod R {}
2220        /// Write-only values (empty)
2221        pub mod W {}
2222        /// Read-write values (empty)
2223        pub mod RW {}
2224    }
2225
2226    /// Filter FIFO assignment for filter 15
2227    pub mod FFA15 {
2228        /// Offset (15 bits)
2229        pub const offset: u32 = 15;
2230        /// Mask (1 bit: 1 << 15)
2231        pub const mask: u32 = 1 << offset;
2232        /// Read-only values (empty)
2233        pub mod R {}
2234        /// Write-only values (empty)
2235        pub mod W {}
2236        /// Read-write values (empty)
2237        pub mod RW {}
2238    }
2239
2240    /// Filter FIFO assignment for filter 16
2241    pub mod FFA16 {
2242        /// Offset (16 bits)
2243        pub const offset: u32 = 16;
2244        /// Mask (1 bit: 1 << 16)
2245        pub const mask: u32 = 1 << offset;
2246        /// Read-only values (empty)
2247        pub mod R {}
2248        /// Write-only values (empty)
2249        pub mod W {}
2250        /// Read-write values (empty)
2251        pub mod RW {}
2252    }
2253
2254    /// Filter FIFO assignment for filter 17
2255    pub mod FFA17 {
2256        /// Offset (17 bits)
2257        pub const offset: u32 = 17;
2258        /// Mask (1 bit: 1 << 17)
2259        pub const mask: u32 = 1 << offset;
2260        /// Read-only values (empty)
2261        pub mod R {}
2262        /// Write-only values (empty)
2263        pub mod W {}
2264        /// Read-write values (empty)
2265        pub mod RW {}
2266    }
2267
2268    /// Filter FIFO assignment for filter 18
2269    pub mod FFA18 {
2270        /// Offset (18 bits)
2271        pub const offset: u32 = 18;
2272        /// Mask (1 bit: 1 << 18)
2273        pub const mask: u32 = 1 << offset;
2274        /// Read-only values (empty)
2275        pub mod R {}
2276        /// Write-only values (empty)
2277        pub mod W {}
2278        /// Read-write values (empty)
2279        pub mod RW {}
2280    }
2281
2282    /// Filter FIFO assignment for filter 19
2283    pub mod FFA19 {
2284        /// Offset (19 bits)
2285        pub const offset: u32 = 19;
2286        /// Mask (1 bit: 1 << 19)
2287        pub const mask: u32 = 1 << offset;
2288        /// Read-only values (empty)
2289        pub mod R {}
2290        /// Write-only values (empty)
2291        pub mod W {}
2292        /// Read-write values (empty)
2293        pub mod RW {}
2294    }
2295
2296    /// Filter FIFO assignment for filter 20
2297    pub mod FFA20 {
2298        /// Offset (20 bits)
2299        pub const offset: u32 = 20;
2300        /// Mask (1 bit: 1 << 20)
2301        pub const mask: u32 = 1 << offset;
2302        /// Read-only values (empty)
2303        pub mod R {}
2304        /// Write-only values (empty)
2305        pub mod W {}
2306        /// Read-write values (empty)
2307        pub mod RW {}
2308    }
2309
2310    /// Filter FIFO assignment for filter 21
2311    pub mod FFA21 {
2312        /// Offset (21 bits)
2313        pub const offset: u32 = 21;
2314        /// Mask (1 bit: 1 << 21)
2315        pub const mask: u32 = 1 << offset;
2316        /// Read-only values (empty)
2317        pub mod R {}
2318        /// Write-only values (empty)
2319        pub mod W {}
2320        /// Read-write values (empty)
2321        pub mod RW {}
2322    }
2323
2324    /// Filter FIFO assignment for filter 22
2325    pub mod FFA22 {
2326        /// Offset (22 bits)
2327        pub const offset: u32 = 22;
2328        /// Mask (1 bit: 1 << 22)
2329        pub const mask: u32 = 1 << offset;
2330        /// Read-only values (empty)
2331        pub mod R {}
2332        /// Write-only values (empty)
2333        pub mod W {}
2334        /// Read-write values (empty)
2335        pub mod RW {}
2336    }
2337
2338    /// Filter FIFO assignment for filter 23
2339    pub mod FFA23 {
2340        /// Offset (23 bits)
2341        pub const offset: u32 = 23;
2342        /// Mask (1 bit: 1 << 23)
2343        pub const mask: u32 = 1 << offset;
2344        /// Read-only values (empty)
2345        pub mod R {}
2346        /// Write-only values (empty)
2347        pub mod W {}
2348        /// Read-write values (empty)
2349        pub mod RW {}
2350    }
2351
2352    /// Filter FIFO assignment for filter 24
2353    pub mod FFA24 {
2354        /// Offset (24 bits)
2355        pub const offset: u32 = 24;
2356        /// Mask (1 bit: 1 << 24)
2357        pub const mask: u32 = 1 << offset;
2358        /// Read-only values (empty)
2359        pub mod R {}
2360        /// Write-only values (empty)
2361        pub mod W {}
2362        /// Read-write values (empty)
2363        pub mod RW {}
2364    }
2365
2366    /// Filter FIFO assignment for filter 25
2367    pub mod FFA25 {
2368        /// Offset (25 bits)
2369        pub const offset: u32 = 25;
2370        /// Mask (1 bit: 1 << 25)
2371        pub const mask: u32 = 1 << offset;
2372        /// Read-only values (empty)
2373        pub mod R {}
2374        /// Write-only values (empty)
2375        pub mod W {}
2376        /// Read-write values (empty)
2377        pub mod RW {}
2378    }
2379
2380    /// Filter FIFO assignment for filter 26
2381    pub mod FFA26 {
2382        /// Offset (26 bits)
2383        pub const offset: u32 = 26;
2384        /// Mask (1 bit: 1 << 26)
2385        pub const mask: u32 = 1 << offset;
2386        /// Read-only values (empty)
2387        pub mod R {}
2388        /// Write-only values (empty)
2389        pub mod W {}
2390        /// Read-write values (empty)
2391        pub mod RW {}
2392    }
2393
2394    /// Filter FIFO assignment for filter 27
2395    pub mod FFA27 {
2396        /// Offset (27 bits)
2397        pub const offset: u32 = 27;
2398        /// Mask (1 bit: 1 << 27)
2399        pub const mask: u32 = 1 << offset;
2400        /// Read-only values (empty)
2401        pub mod R {}
2402        /// Write-only values (empty)
2403        pub mod W {}
2404        /// Read-write values (empty)
2405        pub mod RW {}
2406    }
2407}
2408
2409/// filter activation register
2410pub mod FA1R {
2411
2412    /// Filter active
2413    pub mod FACT0 {
2414        /// Offset (0 bits)
2415        pub const offset: u32 = 0;
2416        /// Mask (1 bit: 1 << 0)
2417        pub const mask: u32 = 1 << offset;
2418        /// Read-only values (empty)
2419        pub mod R {}
2420        /// Write-only values (empty)
2421        pub mod W {}
2422        /// Read-write values (empty)
2423        pub mod RW {}
2424    }
2425
2426    /// Filter active
2427    pub mod FACT1 {
2428        /// Offset (1 bits)
2429        pub const offset: u32 = 1;
2430        /// Mask (1 bit: 1 << 1)
2431        pub const mask: u32 = 1 << offset;
2432        /// Read-only values (empty)
2433        pub mod R {}
2434        /// Write-only values (empty)
2435        pub mod W {}
2436        /// Read-write values (empty)
2437        pub mod RW {}
2438    }
2439
2440    /// Filter active
2441    pub mod FACT2 {
2442        /// Offset (2 bits)
2443        pub const offset: u32 = 2;
2444        /// Mask (1 bit: 1 << 2)
2445        pub const mask: u32 = 1 << offset;
2446        /// Read-only values (empty)
2447        pub mod R {}
2448        /// Write-only values (empty)
2449        pub mod W {}
2450        /// Read-write values (empty)
2451        pub mod RW {}
2452    }
2453
2454    /// Filter active
2455    pub mod FACT3 {
2456        /// Offset (3 bits)
2457        pub const offset: u32 = 3;
2458        /// Mask (1 bit: 1 << 3)
2459        pub const mask: u32 = 1 << offset;
2460        /// Read-only values (empty)
2461        pub mod R {}
2462        /// Write-only values (empty)
2463        pub mod W {}
2464        /// Read-write values (empty)
2465        pub mod RW {}
2466    }
2467
2468    /// Filter active
2469    pub mod FACT4 {
2470        /// Offset (4 bits)
2471        pub const offset: u32 = 4;
2472        /// Mask (1 bit: 1 << 4)
2473        pub const mask: u32 = 1 << offset;
2474        /// Read-only values (empty)
2475        pub mod R {}
2476        /// Write-only values (empty)
2477        pub mod W {}
2478        /// Read-write values (empty)
2479        pub mod RW {}
2480    }
2481
2482    /// Filter active
2483    pub mod FACT5 {
2484        /// Offset (5 bits)
2485        pub const offset: u32 = 5;
2486        /// Mask (1 bit: 1 << 5)
2487        pub const mask: u32 = 1 << offset;
2488        /// Read-only values (empty)
2489        pub mod R {}
2490        /// Write-only values (empty)
2491        pub mod W {}
2492        /// Read-write values (empty)
2493        pub mod RW {}
2494    }
2495
2496    /// Filter active
2497    pub mod FACT6 {
2498        /// Offset (6 bits)
2499        pub const offset: u32 = 6;
2500        /// Mask (1 bit: 1 << 6)
2501        pub const mask: u32 = 1 << offset;
2502        /// Read-only values (empty)
2503        pub mod R {}
2504        /// Write-only values (empty)
2505        pub mod W {}
2506        /// Read-write values (empty)
2507        pub mod RW {}
2508    }
2509
2510    /// Filter active
2511    pub mod FACT7 {
2512        /// Offset (7 bits)
2513        pub const offset: u32 = 7;
2514        /// Mask (1 bit: 1 << 7)
2515        pub const mask: u32 = 1 << offset;
2516        /// Read-only values (empty)
2517        pub mod R {}
2518        /// Write-only values (empty)
2519        pub mod W {}
2520        /// Read-write values (empty)
2521        pub mod RW {}
2522    }
2523
2524    /// Filter active
2525    pub mod FACT8 {
2526        /// Offset (8 bits)
2527        pub const offset: u32 = 8;
2528        /// Mask (1 bit: 1 << 8)
2529        pub const mask: u32 = 1 << offset;
2530        /// Read-only values (empty)
2531        pub mod R {}
2532        /// Write-only values (empty)
2533        pub mod W {}
2534        /// Read-write values (empty)
2535        pub mod RW {}
2536    }
2537
2538    /// Filter active
2539    pub mod FACT9 {
2540        /// Offset (9 bits)
2541        pub const offset: u32 = 9;
2542        /// Mask (1 bit: 1 << 9)
2543        pub const mask: u32 = 1 << offset;
2544        /// Read-only values (empty)
2545        pub mod R {}
2546        /// Write-only values (empty)
2547        pub mod W {}
2548        /// Read-write values (empty)
2549        pub mod RW {}
2550    }
2551
2552    /// Filter active
2553    pub mod FACT10 {
2554        /// Offset (10 bits)
2555        pub const offset: u32 = 10;
2556        /// Mask (1 bit: 1 << 10)
2557        pub const mask: u32 = 1 << offset;
2558        /// Read-only values (empty)
2559        pub mod R {}
2560        /// Write-only values (empty)
2561        pub mod W {}
2562        /// Read-write values (empty)
2563        pub mod RW {}
2564    }
2565
2566    /// Filter active
2567    pub mod FACT11 {
2568        /// Offset (11 bits)
2569        pub const offset: u32 = 11;
2570        /// Mask (1 bit: 1 << 11)
2571        pub const mask: u32 = 1 << offset;
2572        /// Read-only values (empty)
2573        pub mod R {}
2574        /// Write-only values (empty)
2575        pub mod W {}
2576        /// Read-write values (empty)
2577        pub mod RW {}
2578    }
2579
2580    /// Filter active
2581    pub mod FACT12 {
2582        /// Offset (12 bits)
2583        pub const offset: u32 = 12;
2584        /// Mask (1 bit: 1 << 12)
2585        pub const mask: u32 = 1 << offset;
2586        /// Read-only values (empty)
2587        pub mod R {}
2588        /// Write-only values (empty)
2589        pub mod W {}
2590        /// Read-write values (empty)
2591        pub mod RW {}
2592    }
2593
2594    /// Filter active
2595    pub mod FACT13 {
2596        /// Offset (13 bits)
2597        pub const offset: u32 = 13;
2598        /// Mask (1 bit: 1 << 13)
2599        pub const mask: u32 = 1 << offset;
2600        /// Read-only values (empty)
2601        pub mod R {}
2602        /// Write-only values (empty)
2603        pub mod W {}
2604        /// Read-write values (empty)
2605        pub mod RW {}
2606    }
2607
2608    /// Filter active
2609    pub mod FACT14 {
2610        /// Offset (14 bits)
2611        pub const offset: u32 = 14;
2612        /// Mask (1 bit: 1 << 14)
2613        pub const mask: u32 = 1 << offset;
2614        /// Read-only values (empty)
2615        pub mod R {}
2616        /// Write-only values (empty)
2617        pub mod W {}
2618        /// Read-write values (empty)
2619        pub mod RW {}
2620    }
2621
2622    /// Filter active
2623    pub mod FACT15 {
2624        /// Offset (15 bits)
2625        pub const offset: u32 = 15;
2626        /// Mask (1 bit: 1 << 15)
2627        pub const mask: u32 = 1 << offset;
2628        /// Read-only values (empty)
2629        pub mod R {}
2630        /// Write-only values (empty)
2631        pub mod W {}
2632        /// Read-write values (empty)
2633        pub mod RW {}
2634    }
2635
2636    /// Filter active
2637    pub mod FACT16 {
2638        /// Offset (16 bits)
2639        pub const offset: u32 = 16;
2640        /// Mask (1 bit: 1 << 16)
2641        pub const mask: u32 = 1 << offset;
2642        /// Read-only values (empty)
2643        pub mod R {}
2644        /// Write-only values (empty)
2645        pub mod W {}
2646        /// Read-write values (empty)
2647        pub mod RW {}
2648    }
2649
2650    /// Filter active
2651    pub mod FACT17 {
2652        /// Offset (17 bits)
2653        pub const offset: u32 = 17;
2654        /// Mask (1 bit: 1 << 17)
2655        pub const mask: u32 = 1 << offset;
2656        /// Read-only values (empty)
2657        pub mod R {}
2658        /// Write-only values (empty)
2659        pub mod W {}
2660        /// Read-write values (empty)
2661        pub mod RW {}
2662    }
2663
2664    /// Filter active
2665    pub mod FACT18 {
2666        /// Offset (18 bits)
2667        pub const offset: u32 = 18;
2668        /// Mask (1 bit: 1 << 18)
2669        pub const mask: u32 = 1 << offset;
2670        /// Read-only values (empty)
2671        pub mod R {}
2672        /// Write-only values (empty)
2673        pub mod W {}
2674        /// Read-write values (empty)
2675        pub mod RW {}
2676    }
2677
2678    /// Filter active
2679    pub mod FACT19 {
2680        /// Offset (19 bits)
2681        pub const offset: u32 = 19;
2682        /// Mask (1 bit: 1 << 19)
2683        pub const mask: u32 = 1 << offset;
2684        /// Read-only values (empty)
2685        pub mod R {}
2686        /// Write-only values (empty)
2687        pub mod W {}
2688        /// Read-write values (empty)
2689        pub mod RW {}
2690    }
2691
2692    /// Filter active
2693    pub mod FACT20 {
2694        /// Offset (20 bits)
2695        pub const offset: u32 = 20;
2696        /// Mask (1 bit: 1 << 20)
2697        pub const mask: u32 = 1 << offset;
2698        /// Read-only values (empty)
2699        pub mod R {}
2700        /// Write-only values (empty)
2701        pub mod W {}
2702        /// Read-write values (empty)
2703        pub mod RW {}
2704    }
2705
2706    /// Filter active
2707    pub mod FACT21 {
2708        /// Offset (21 bits)
2709        pub const offset: u32 = 21;
2710        /// Mask (1 bit: 1 << 21)
2711        pub const mask: u32 = 1 << offset;
2712        /// Read-only values (empty)
2713        pub mod R {}
2714        /// Write-only values (empty)
2715        pub mod W {}
2716        /// Read-write values (empty)
2717        pub mod RW {}
2718    }
2719
2720    /// Filter active
2721    pub mod FACT22 {
2722        /// Offset (22 bits)
2723        pub const offset: u32 = 22;
2724        /// Mask (1 bit: 1 << 22)
2725        pub const mask: u32 = 1 << offset;
2726        /// Read-only values (empty)
2727        pub mod R {}
2728        /// Write-only values (empty)
2729        pub mod W {}
2730        /// Read-write values (empty)
2731        pub mod RW {}
2732    }
2733
2734    /// Filter active
2735    pub mod FACT23 {
2736        /// Offset (23 bits)
2737        pub const offset: u32 = 23;
2738        /// Mask (1 bit: 1 << 23)
2739        pub const mask: u32 = 1 << offset;
2740        /// Read-only values (empty)
2741        pub mod R {}
2742        /// Write-only values (empty)
2743        pub mod W {}
2744        /// Read-write values (empty)
2745        pub mod RW {}
2746    }
2747
2748    /// Filter active
2749    pub mod FACT24 {
2750        /// Offset (24 bits)
2751        pub const offset: u32 = 24;
2752        /// Mask (1 bit: 1 << 24)
2753        pub const mask: u32 = 1 << offset;
2754        /// Read-only values (empty)
2755        pub mod R {}
2756        /// Write-only values (empty)
2757        pub mod W {}
2758        /// Read-write values (empty)
2759        pub mod RW {}
2760    }
2761
2762    /// Filter active
2763    pub mod FACT25 {
2764        /// Offset (25 bits)
2765        pub const offset: u32 = 25;
2766        /// Mask (1 bit: 1 << 25)
2767        pub const mask: u32 = 1 << offset;
2768        /// Read-only values (empty)
2769        pub mod R {}
2770        /// Write-only values (empty)
2771        pub mod W {}
2772        /// Read-write values (empty)
2773        pub mod RW {}
2774    }
2775
2776    /// Filter active
2777    pub mod FACT26 {
2778        /// Offset (26 bits)
2779        pub const offset: u32 = 26;
2780        /// Mask (1 bit: 1 << 26)
2781        pub const mask: u32 = 1 << offset;
2782        /// Read-only values (empty)
2783        pub mod R {}
2784        /// Write-only values (empty)
2785        pub mod W {}
2786        /// Read-write values (empty)
2787        pub mod RW {}
2788    }
2789
2790    /// Filter active
2791    pub mod FACT27 {
2792        /// Offset (27 bits)
2793        pub const offset: u32 = 27;
2794        /// Mask (1 bit: 1 << 27)
2795        pub const mask: u32 = 1 << offset;
2796        /// Read-only values (empty)
2797        pub mod R {}
2798        /// Write-only values (empty)
2799        pub mod W {}
2800        /// Read-write values (empty)
2801        pub mod RW {}
2802    }
2803}
2804
2805/// TX mailbox identifier register
2806pub mod TIR0 {
2807
2808    /// STID
2809    pub mod STID {
2810        /// Offset (21 bits)
2811        pub const offset: u32 = 21;
2812        /// Mask (11 bits: 0x7ff << 21)
2813        pub const mask: u32 = 0x7ff << offset;
2814        /// Read-only values (empty)
2815        pub mod R {}
2816        /// Write-only values (empty)
2817        pub mod W {}
2818        /// Read-write values (empty)
2819        pub mod RW {}
2820    }
2821
2822    /// EXID
2823    pub mod EXID {
2824        /// Offset (3 bits)
2825        pub const offset: u32 = 3;
2826        /// Mask (18 bits: 0x3ffff << 3)
2827        pub const mask: u32 = 0x3ffff << offset;
2828        /// Read-only values (empty)
2829        pub mod R {}
2830        /// Write-only values (empty)
2831        pub mod W {}
2832        /// Read-write values (empty)
2833        pub mod RW {}
2834    }
2835
2836    /// IDE
2837    pub mod IDE {
2838        /// Offset (2 bits)
2839        pub const offset: u32 = 2;
2840        /// Mask (1 bit: 1 << 2)
2841        pub const mask: u32 = 1 << offset;
2842        /// Read-only values (empty)
2843        pub mod R {}
2844        /// Write-only values (empty)
2845        pub mod W {}
2846        /// Read-write values
2847        pub mod RW {
2848
2849            /// 0b0: Standard identifier
2850            pub const Standard: u32 = 0b0;
2851
2852            /// 0b1: Extended identifier
2853            pub const Extended: u32 = 0b1;
2854        }
2855    }
2856
2857    /// RTR
2858    pub mod RTR {
2859        /// Offset (1 bits)
2860        pub const offset: u32 = 1;
2861        /// Mask (1 bit: 1 << 1)
2862        pub const mask: u32 = 1 << offset;
2863        /// Read-only values (empty)
2864        pub mod R {}
2865        /// Write-only values (empty)
2866        pub mod W {}
2867        /// Read-write values
2868        pub mod RW {
2869
2870            /// 0b0: Data frame
2871            pub const Data: u32 = 0b0;
2872
2873            /// 0b1: Remote frame
2874            pub const Remote: u32 = 0b1;
2875        }
2876    }
2877
2878    /// TXRQ
2879    pub mod TXRQ {
2880        /// Offset (0 bits)
2881        pub const offset: u32 = 0;
2882        /// Mask (1 bit: 1 << 0)
2883        pub const mask: u32 = 1 << offset;
2884        /// Read-only values (empty)
2885        pub mod R {}
2886        /// Write-only values (empty)
2887        pub mod W {}
2888        /// Read-write values (empty)
2889        pub mod RW {}
2890    }
2891}
2892
2893/// mailbox data length control and time stamp register
2894pub mod TDTR0 {
2895
2896    /// TIME
2897    pub mod TIME {
2898        /// Offset (16 bits)
2899        pub const offset: u32 = 16;
2900        /// Mask (16 bits: 0xffff << 16)
2901        pub const mask: u32 = 0xffff << offset;
2902        /// Read-only values (empty)
2903        pub mod R {}
2904        /// Write-only values (empty)
2905        pub mod W {}
2906        /// Read-write values (empty)
2907        pub mod RW {}
2908    }
2909
2910    /// TGT
2911    pub mod TGT {
2912        /// Offset (8 bits)
2913        pub const offset: u32 = 8;
2914        /// Mask (1 bit: 1 << 8)
2915        pub const mask: u32 = 1 << offset;
2916        /// Read-only values (empty)
2917        pub mod R {}
2918        /// Write-only values (empty)
2919        pub mod W {}
2920        /// Read-write values (empty)
2921        pub mod RW {}
2922    }
2923
2924    /// DLC
2925    pub mod DLC {
2926        /// Offset (0 bits)
2927        pub const offset: u32 = 0;
2928        /// Mask (4 bits: 0b1111 << 0)
2929        pub const mask: u32 = 0b1111 << offset;
2930        /// Read-only values (empty)
2931        pub mod R {}
2932        /// Write-only values (empty)
2933        pub mod W {}
2934        /// Read-write values (empty)
2935        pub mod RW {}
2936    }
2937}
2938
2939/// mailbox data low register
2940pub mod TDLR0 {
2941
2942    /// DATA3
2943    pub mod DATA3 {
2944        /// Offset (24 bits)
2945        pub const offset: u32 = 24;
2946        /// Mask (8 bits: 0xff << 24)
2947        pub const mask: u32 = 0xff << offset;
2948        /// Read-only values (empty)
2949        pub mod R {}
2950        /// Write-only values (empty)
2951        pub mod W {}
2952        /// Read-write values (empty)
2953        pub mod RW {}
2954    }
2955
2956    /// DATA2
2957    pub mod DATA2 {
2958        /// Offset (16 bits)
2959        pub const offset: u32 = 16;
2960        /// Mask (8 bits: 0xff << 16)
2961        pub const mask: u32 = 0xff << offset;
2962        /// Read-only values (empty)
2963        pub mod R {}
2964        /// Write-only values (empty)
2965        pub mod W {}
2966        /// Read-write values (empty)
2967        pub mod RW {}
2968    }
2969
2970    /// DATA1
2971    pub mod DATA1 {
2972        /// Offset (8 bits)
2973        pub const offset: u32 = 8;
2974        /// Mask (8 bits: 0xff << 8)
2975        pub const mask: u32 = 0xff << offset;
2976        /// Read-only values (empty)
2977        pub mod R {}
2978        /// Write-only values (empty)
2979        pub mod W {}
2980        /// Read-write values (empty)
2981        pub mod RW {}
2982    }
2983
2984    /// DATA0
2985    pub mod DATA0 {
2986        /// Offset (0 bits)
2987        pub const offset: u32 = 0;
2988        /// Mask (8 bits: 0xff << 0)
2989        pub const mask: u32 = 0xff << offset;
2990        /// Read-only values (empty)
2991        pub mod R {}
2992        /// Write-only values (empty)
2993        pub mod W {}
2994        /// Read-write values (empty)
2995        pub mod RW {}
2996    }
2997}
2998
2999/// mailbox data high register
3000pub mod TDHR0 {
3001
3002    /// DATA7
3003    pub mod DATA7 {
3004        /// Offset (24 bits)
3005        pub const offset: u32 = 24;
3006        /// Mask (8 bits: 0xff << 24)
3007        pub const mask: u32 = 0xff << offset;
3008        /// Read-only values (empty)
3009        pub mod R {}
3010        /// Write-only values (empty)
3011        pub mod W {}
3012        /// Read-write values (empty)
3013        pub mod RW {}
3014    }
3015
3016    /// DATA6
3017    pub mod DATA6 {
3018        /// Offset (16 bits)
3019        pub const offset: u32 = 16;
3020        /// Mask (8 bits: 0xff << 16)
3021        pub const mask: u32 = 0xff << offset;
3022        /// Read-only values (empty)
3023        pub mod R {}
3024        /// Write-only values (empty)
3025        pub mod W {}
3026        /// Read-write values (empty)
3027        pub mod RW {}
3028    }
3029
3030    /// DATA5
3031    pub mod DATA5 {
3032        /// Offset (8 bits)
3033        pub const offset: u32 = 8;
3034        /// Mask (8 bits: 0xff << 8)
3035        pub const mask: u32 = 0xff << offset;
3036        /// Read-only values (empty)
3037        pub mod R {}
3038        /// Write-only values (empty)
3039        pub mod W {}
3040        /// Read-write values (empty)
3041        pub mod RW {}
3042    }
3043
3044    /// DATA4
3045    pub mod DATA4 {
3046        /// Offset (0 bits)
3047        pub const offset: u32 = 0;
3048        /// Mask (8 bits: 0xff << 0)
3049        pub const mask: u32 = 0xff << offset;
3050        /// Read-only values (empty)
3051        pub mod R {}
3052        /// Write-only values (empty)
3053        pub mod W {}
3054        /// Read-write values (empty)
3055        pub mod RW {}
3056    }
3057}
3058
3059/// TX mailbox identifier register
3060pub mod TIR1 {
3061    pub use super::TIR0::EXID;
3062    pub use super::TIR0::IDE;
3063    pub use super::TIR0::RTR;
3064    pub use super::TIR0::STID;
3065    pub use super::TIR0::TXRQ;
3066}
3067
3068/// mailbox data length control and time stamp register
3069pub mod TDTR1 {
3070    pub use super::TDTR0::DLC;
3071    pub use super::TDTR0::TGT;
3072    pub use super::TDTR0::TIME;
3073}
3074
3075/// mailbox data low register
3076pub mod TDLR1 {
3077    pub use super::TDLR0::DATA0;
3078    pub use super::TDLR0::DATA1;
3079    pub use super::TDLR0::DATA2;
3080    pub use super::TDLR0::DATA3;
3081}
3082
3083/// mailbox data high register
3084pub mod TDHR1 {
3085    pub use super::TDHR0::DATA4;
3086    pub use super::TDHR0::DATA5;
3087    pub use super::TDHR0::DATA6;
3088    pub use super::TDHR0::DATA7;
3089}
3090
3091/// TX mailbox identifier register
3092pub mod TIR2 {
3093    pub use super::TIR0::EXID;
3094    pub use super::TIR0::IDE;
3095    pub use super::TIR0::RTR;
3096    pub use super::TIR0::STID;
3097    pub use super::TIR0::TXRQ;
3098}
3099
3100/// mailbox data length control and time stamp register
3101pub mod TDTR2 {
3102    pub use super::TDTR0::DLC;
3103    pub use super::TDTR0::TGT;
3104    pub use super::TDTR0::TIME;
3105}
3106
3107/// mailbox data low register
3108pub mod TDLR2 {
3109    pub use super::TDLR0::DATA0;
3110    pub use super::TDLR0::DATA1;
3111    pub use super::TDLR0::DATA2;
3112    pub use super::TDLR0::DATA3;
3113}
3114
3115/// mailbox data high register
3116pub mod TDHR2 {
3117    pub use super::TDHR0::DATA4;
3118    pub use super::TDHR0::DATA5;
3119    pub use super::TDHR0::DATA6;
3120    pub use super::TDHR0::DATA7;
3121}
3122
3123/// receive FIFO mailbox identifier register
3124pub mod RIR0 {
3125
3126    /// STID
3127    pub mod STID {
3128        /// Offset (21 bits)
3129        pub const offset: u32 = 21;
3130        /// Mask (11 bits: 0x7ff << 21)
3131        pub const mask: u32 = 0x7ff << offset;
3132        /// Read-only values (empty)
3133        pub mod R {}
3134        /// Write-only values (empty)
3135        pub mod W {}
3136        /// Read-write values (empty)
3137        pub mod RW {}
3138    }
3139
3140    /// EXID
3141    pub mod EXID {
3142        /// Offset (3 bits)
3143        pub const offset: u32 = 3;
3144        /// Mask (18 bits: 0x3ffff << 3)
3145        pub const mask: u32 = 0x3ffff << offset;
3146        /// Read-only values (empty)
3147        pub mod R {}
3148        /// Write-only values (empty)
3149        pub mod W {}
3150        /// Read-write values (empty)
3151        pub mod RW {}
3152    }
3153
3154    /// IDE
3155    pub mod IDE {
3156        /// Offset (2 bits)
3157        pub const offset: u32 = 2;
3158        /// Mask (1 bit: 1 << 2)
3159        pub const mask: u32 = 1 << offset;
3160        /// Read-only values
3161        pub mod R {
3162
3163            /// 0b0: Standard identifier
3164            pub const Standard: u32 = 0b0;
3165
3166            /// 0b1: Extended identifier
3167            pub const Extended: u32 = 0b1;
3168        }
3169        /// Write-only values (empty)
3170        pub mod W {}
3171        /// Read-write values (empty)
3172        pub mod RW {}
3173    }
3174
3175    /// RTR
3176    pub mod RTR {
3177        /// Offset (1 bits)
3178        pub const offset: u32 = 1;
3179        /// Mask (1 bit: 1 << 1)
3180        pub const mask: u32 = 1 << offset;
3181        /// Read-only values
3182        pub mod R {
3183
3184            /// 0b0: Data frame
3185            pub const Data: u32 = 0b0;
3186
3187            /// 0b1: Remote frame
3188            pub const Remote: u32 = 0b1;
3189        }
3190        /// Write-only values (empty)
3191        pub mod W {}
3192        /// Read-write values (empty)
3193        pub mod RW {}
3194    }
3195}
3196
3197/// mailbox data high register
3198pub mod RDTR0 {
3199
3200    /// TIME
3201    pub mod TIME {
3202        /// Offset (16 bits)
3203        pub const offset: u32 = 16;
3204        /// Mask (16 bits: 0xffff << 16)
3205        pub const mask: u32 = 0xffff << offset;
3206        /// Read-only values (empty)
3207        pub mod R {}
3208        /// Write-only values (empty)
3209        pub mod W {}
3210        /// Read-write values (empty)
3211        pub mod RW {}
3212    }
3213
3214    /// FMI
3215    pub mod FMI {
3216        /// Offset (8 bits)
3217        pub const offset: u32 = 8;
3218        /// Mask (8 bits: 0xff << 8)
3219        pub const mask: u32 = 0xff << offset;
3220        /// Read-only values (empty)
3221        pub mod R {}
3222        /// Write-only values (empty)
3223        pub mod W {}
3224        /// Read-write values (empty)
3225        pub mod RW {}
3226    }
3227
3228    /// DLC
3229    pub mod DLC {
3230        /// Offset (0 bits)
3231        pub const offset: u32 = 0;
3232        /// Mask (4 bits: 0b1111 << 0)
3233        pub const mask: u32 = 0b1111 << offset;
3234        /// Read-only values (empty)
3235        pub mod R {}
3236        /// Write-only values (empty)
3237        pub mod W {}
3238        /// Read-write values (empty)
3239        pub mod RW {}
3240    }
3241}
3242
3243/// mailbox data high register
3244pub mod RDLR0 {
3245
3246    /// DATA3
3247    pub mod DATA3 {
3248        /// Offset (24 bits)
3249        pub const offset: u32 = 24;
3250        /// Mask (8 bits: 0xff << 24)
3251        pub const mask: u32 = 0xff << offset;
3252        /// Read-only values (empty)
3253        pub mod R {}
3254        /// Write-only values (empty)
3255        pub mod W {}
3256        /// Read-write values (empty)
3257        pub mod RW {}
3258    }
3259
3260    /// DATA2
3261    pub mod DATA2 {
3262        /// Offset (16 bits)
3263        pub const offset: u32 = 16;
3264        /// Mask (8 bits: 0xff << 16)
3265        pub const mask: u32 = 0xff << offset;
3266        /// Read-only values (empty)
3267        pub mod R {}
3268        /// Write-only values (empty)
3269        pub mod W {}
3270        /// Read-write values (empty)
3271        pub mod RW {}
3272    }
3273
3274    /// DATA1
3275    pub mod DATA1 {
3276        /// Offset (8 bits)
3277        pub const offset: u32 = 8;
3278        /// Mask (8 bits: 0xff << 8)
3279        pub const mask: u32 = 0xff << offset;
3280        /// Read-only values (empty)
3281        pub mod R {}
3282        /// Write-only values (empty)
3283        pub mod W {}
3284        /// Read-write values (empty)
3285        pub mod RW {}
3286    }
3287
3288    /// DATA0
3289    pub mod DATA0 {
3290        /// Offset (0 bits)
3291        pub const offset: u32 = 0;
3292        /// Mask (8 bits: 0xff << 0)
3293        pub const mask: u32 = 0xff << offset;
3294        /// Read-only values (empty)
3295        pub mod R {}
3296        /// Write-only values (empty)
3297        pub mod W {}
3298        /// Read-write values (empty)
3299        pub mod RW {}
3300    }
3301}
3302
3303/// receive FIFO mailbox data high register
3304pub mod RDHR0 {
3305
3306    /// DATA7
3307    pub mod DATA7 {
3308        /// Offset (24 bits)
3309        pub const offset: u32 = 24;
3310        /// Mask (8 bits: 0xff << 24)
3311        pub const mask: u32 = 0xff << offset;
3312        /// Read-only values (empty)
3313        pub mod R {}
3314        /// Write-only values (empty)
3315        pub mod W {}
3316        /// Read-write values (empty)
3317        pub mod RW {}
3318    }
3319
3320    /// DATA6
3321    pub mod DATA6 {
3322        /// Offset (16 bits)
3323        pub const offset: u32 = 16;
3324        /// Mask (8 bits: 0xff << 16)
3325        pub const mask: u32 = 0xff << offset;
3326        /// Read-only values (empty)
3327        pub mod R {}
3328        /// Write-only values (empty)
3329        pub mod W {}
3330        /// Read-write values (empty)
3331        pub mod RW {}
3332    }
3333
3334    /// DATA5
3335    pub mod DATA5 {
3336        /// Offset (8 bits)
3337        pub const offset: u32 = 8;
3338        /// Mask (8 bits: 0xff << 8)
3339        pub const mask: u32 = 0xff << offset;
3340        /// Read-only values (empty)
3341        pub mod R {}
3342        /// Write-only values (empty)
3343        pub mod W {}
3344        /// Read-write values (empty)
3345        pub mod RW {}
3346    }
3347
3348    /// DATA4
3349    pub mod DATA4 {
3350        /// Offset (0 bits)
3351        pub const offset: u32 = 0;
3352        /// Mask (8 bits: 0xff << 0)
3353        pub const mask: u32 = 0xff << offset;
3354        /// Read-only values (empty)
3355        pub mod R {}
3356        /// Write-only values (empty)
3357        pub mod W {}
3358        /// Read-write values (empty)
3359        pub mod RW {}
3360    }
3361}
3362
3363/// receive FIFO mailbox identifier register
3364pub mod RIR1 {
3365    pub use super::RIR0::EXID;
3366    pub use super::RIR0::IDE;
3367    pub use super::RIR0::RTR;
3368    pub use super::RIR0::STID;
3369}
3370
3371/// mailbox data high register
3372pub mod RDTR1 {
3373    pub use super::RDTR0::DLC;
3374    pub use super::RDTR0::FMI;
3375    pub use super::RDTR0::TIME;
3376}
3377
3378/// mailbox data high register
3379pub mod RDLR1 {
3380    pub use super::RDLR0::DATA0;
3381    pub use super::RDLR0::DATA1;
3382    pub use super::RDLR0::DATA2;
3383    pub use super::RDLR0::DATA3;
3384}
3385
3386/// receive FIFO mailbox data high register
3387pub mod RDHR1 {
3388    pub use super::RDHR0::DATA4;
3389    pub use super::RDHR0::DATA5;
3390    pub use super::RDHR0::DATA6;
3391    pub use super::RDHR0::DATA7;
3392}
3393
3394/// Filter bank 0 register 1
3395pub mod FR10 {
3396
3397    /// Filter bits
3398    pub mod FB0 {
3399        /// Offset (0 bits)
3400        pub const offset: u32 = 0;
3401        /// Mask (1 bit: 1 << 0)
3402        pub const mask: u32 = 1 << offset;
3403        /// Read-only values (empty)
3404        pub mod R {}
3405        /// Write-only values (empty)
3406        pub mod W {}
3407        /// Read-write values (empty)
3408        pub mod RW {}
3409    }
3410
3411    /// Filter bits
3412    pub mod FB1 {
3413        /// Offset (1 bits)
3414        pub const offset: u32 = 1;
3415        /// Mask (1 bit: 1 << 1)
3416        pub const mask: u32 = 1 << offset;
3417        /// Read-only values (empty)
3418        pub mod R {}
3419        /// Write-only values (empty)
3420        pub mod W {}
3421        /// Read-write values (empty)
3422        pub mod RW {}
3423    }
3424
3425    /// Filter bits
3426    pub mod FB2 {
3427        /// Offset (2 bits)
3428        pub const offset: u32 = 2;
3429        /// Mask (1 bit: 1 << 2)
3430        pub const mask: u32 = 1 << offset;
3431        /// Read-only values (empty)
3432        pub mod R {}
3433        /// Write-only values (empty)
3434        pub mod W {}
3435        /// Read-write values (empty)
3436        pub mod RW {}
3437    }
3438
3439    /// Filter bits
3440    pub mod FB3 {
3441        /// Offset (3 bits)
3442        pub const offset: u32 = 3;
3443        /// Mask (1 bit: 1 << 3)
3444        pub const mask: u32 = 1 << offset;
3445        /// Read-only values (empty)
3446        pub mod R {}
3447        /// Write-only values (empty)
3448        pub mod W {}
3449        /// Read-write values (empty)
3450        pub mod RW {}
3451    }
3452
3453    /// Filter bits
3454    pub mod FB4 {
3455        /// Offset (4 bits)
3456        pub const offset: u32 = 4;
3457        /// Mask (1 bit: 1 << 4)
3458        pub const mask: u32 = 1 << offset;
3459        /// Read-only values (empty)
3460        pub mod R {}
3461        /// Write-only values (empty)
3462        pub mod W {}
3463        /// Read-write values (empty)
3464        pub mod RW {}
3465    }
3466
3467    /// Filter bits
3468    pub mod FB5 {
3469        /// Offset (5 bits)
3470        pub const offset: u32 = 5;
3471        /// Mask (1 bit: 1 << 5)
3472        pub const mask: u32 = 1 << offset;
3473        /// Read-only values (empty)
3474        pub mod R {}
3475        /// Write-only values (empty)
3476        pub mod W {}
3477        /// Read-write values (empty)
3478        pub mod RW {}
3479    }
3480
3481    /// Filter bits
3482    pub mod FB6 {
3483        /// Offset (6 bits)
3484        pub const offset: u32 = 6;
3485        /// Mask (1 bit: 1 << 6)
3486        pub const mask: u32 = 1 << offset;
3487        /// Read-only values (empty)
3488        pub mod R {}
3489        /// Write-only values (empty)
3490        pub mod W {}
3491        /// Read-write values (empty)
3492        pub mod RW {}
3493    }
3494
3495    /// Filter bits
3496    pub mod FB7 {
3497        /// Offset (7 bits)
3498        pub const offset: u32 = 7;
3499        /// Mask (1 bit: 1 << 7)
3500        pub const mask: u32 = 1 << offset;
3501        /// Read-only values (empty)
3502        pub mod R {}
3503        /// Write-only values (empty)
3504        pub mod W {}
3505        /// Read-write values (empty)
3506        pub mod RW {}
3507    }
3508
3509    /// Filter bits
3510    pub mod FB8 {
3511        /// Offset (8 bits)
3512        pub const offset: u32 = 8;
3513        /// Mask (1 bit: 1 << 8)
3514        pub const mask: u32 = 1 << offset;
3515        /// Read-only values (empty)
3516        pub mod R {}
3517        /// Write-only values (empty)
3518        pub mod W {}
3519        /// Read-write values (empty)
3520        pub mod RW {}
3521    }
3522
3523    /// Filter bits
3524    pub mod FB9 {
3525        /// Offset (9 bits)
3526        pub const offset: u32 = 9;
3527        /// Mask (1 bit: 1 << 9)
3528        pub const mask: u32 = 1 << offset;
3529        /// Read-only values (empty)
3530        pub mod R {}
3531        /// Write-only values (empty)
3532        pub mod W {}
3533        /// Read-write values (empty)
3534        pub mod RW {}
3535    }
3536
3537    /// Filter bits
3538    pub mod FB10 {
3539        /// Offset (10 bits)
3540        pub const offset: u32 = 10;
3541        /// Mask (1 bit: 1 << 10)
3542        pub const mask: u32 = 1 << offset;
3543        /// Read-only values (empty)
3544        pub mod R {}
3545        /// Write-only values (empty)
3546        pub mod W {}
3547        /// Read-write values (empty)
3548        pub mod RW {}
3549    }
3550
3551    /// Filter bits
3552    pub mod FB11 {
3553        /// Offset (11 bits)
3554        pub const offset: u32 = 11;
3555        /// Mask (1 bit: 1 << 11)
3556        pub const mask: u32 = 1 << offset;
3557        /// Read-only values (empty)
3558        pub mod R {}
3559        /// Write-only values (empty)
3560        pub mod W {}
3561        /// Read-write values (empty)
3562        pub mod RW {}
3563    }
3564
3565    /// Filter bits
3566    pub mod FB12 {
3567        /// Offset (12 bits)
3568        pub const offset: u32 = 12;
3569        /// Mask (1 bit: 1 << 12)
3570        pub const mask: u32 = 1 << offset;
3571        /// Read-only values (empty)
3572        pub mod R {}
3573        /// Write-only values (empty)
3574        pub mod W {}
3575        /// Read-write values (empty)
3576        pub mod RW {}
3577    }
3578
3579    /// Filter bits
3580    pub mod FB13 {
3581        /// Offset (13 bits)
3582        pub const offset: u32 = 13;
3583        /// Mask (1 bit: 1 << 13)
3584        pub const mask: u32 = 1 << offset;
3585        /// Read-only values (empty)
3586        pub mod R {}
3587        /// Write-only values (empty)
3588        pub mod W {}
3589        /// Read-write values (empty)
3590        pub mod RW {}
3591    }
3592
3593    /// Filter bits
3594    pub mod FB14 {
3595        /// Offset (14 bits)
3596        pub const offset: u32 = 14;
3597        /// Mask (1 bit: 1 << 14)
3598        pub const mask: u32 = 1 << offset;
3599        /// Read-only values (empty)
3600        pub mod R {}
3601        /// Write-only values (empty)
3602        pub mod W {}
3603        /// Read-write values (empty)
3604        pub mod RW {}
3605    }
3606
3607    /// Filter bits
3608    pub mod FB15 {
3609        /// Offset (15 bits)
3610        pub const offset: u32 = 15;
3611        /// Mask (1 bit: 1 << 15)
3612        pub const mask: u32 = 1 << offset;
3613        /// Read-only values (empty)
3614        pub mod R {}
3615        /// Write-only values (empty)
3616        pub mod W {}
3617        /// Read-write values (empty)
3618        pub mod RW {}
3619    }
3620
3621    /// Filter bits
3622    pub mod FB16 {
3623        /// Offset (16 bits)
3624        pub const offset: u32 = 16;
3625        /// Mask (1 bit: 1 << 16)
3626        pub const mask: u32 = 1 << offset;
3627        /// Read-only values (empty)
3628        pub mod R {}
3629        /// Write-only values (empty)
3630        pub mod W {}
3631        /// Read-write values (empty)
3632        pub mod RW {}
3633    }
3634
3635    /// Filter bits
3636    pub mod FB17 {
3637        /// Offset (17 bits)
3638        pub const offset: u32 = 17;
3639        /// Mask (1 bit: 1 << 17)
3640        pub const mask: u32 = 1 << offset;
3641        /// Read-only values (empty)
3642        pub mod R {}
3643        /// Write-only values (empty)
3644        pub mod W {}
3645        /// Read-write values (empty)
3646        pub mod RW {}
3647    }
3648
3649    /// Filter bits
3650    pub mod FB18 {
3651        /// Offset (18 bits)
3652        pub const offset: u32 = 18;
3653        /// Mask (1 bit: 1 << 18)
3654        pub const mask: u32 = 1 << offset;
3655        /// Read-only values (empty)
3656        pub mod R {}
3657        /// Write-only values (empty)
3658        pub mod W {}
3659        /// Read-write values (empty)
3660        pub mod RW {}
3661    }
3662
3663    /// Filter bits
3664    pub mod FB19 {
3665        /// Offset (19 bits)
3666        pub const offset: u32 = 19;
3667        /// Mask (1 bit: 1 << 19)
3668        pub const mask: u32 = 1 << offset;
3669        /// Read-only values (empty)
3670        pub mod R {}
3671        /// Write-only values (empty)
3672        pub mod W {}
3673        /// Read-write values (empty)
3674        pub mod RW {}
3675    }
3676
3677    /// Filter bits
3678    pub mod FB20 {
3679        /// Offset (20 bits)
3680        pub const offset: u32 = 20;
3681        /// Mask (1 bit: 1 << 20)
3682        pub const mask: u32 = 1 << offset;
3683        /// Read-only values (empty)
3684        pub mod R {}
3685        /// Write-only values (empty)
3686        pub mod W {}
3687        /// Read-write values (empty)
3688        pub mod RW {}
3689    }
3690
3691    /// Filter bits
3692    pub mod FB21 {
3693        /// Offset (21 bits)
3694        pub const offset: u32 = 21;
3695        /// Mask (1 bit: 1 << 21)
3696        pub const mask: u32 = 1 << offset;
3697        /// Read-only values (empty)
3698        pub mod R {}
3699        /// Write-only values (empty)
3700        pub mod W {}
3701        /// Read-write values (empty)
3702        pub mod RW {}
3703    }
3704
3705    /// Filter bits
3706    pub mod FB22 {
3707        /// Offset (22 bits)
3708        pub const offset: u32 = 22;
3709        /// Mask (1 bit: 1 << 22)
3710        pub const mask: u32 = 1 << offset;
3711        /// Read-only values (empty)
3712        pub mod R {}
3713        /// Write-only values (empty)
3714        pub mod W {}
3715        /// Read-write values (empty)
3716        pub mod RW {}
3717    }
3718
3719    /// Filter bits
3720    pub mod FB23 {
3721        /// Offset (23 bits)
3722        pub const offset: u32 = 23;
3723        /// Mask (1 bit: 1 << 23)
3724        pub const mask: u32 = 1 << offset;
3725        /// Read-only values (empty)
3726        pub mod R {}
3727        /// Write-only values (empty)
3728        pub mod W {}
3729        /// Read-write values (empty)
3730        pub mod RW {}
3731    }
3732
3733    /// Filter bits
3734    pub mod FB24 {
3735        /// Offset (24 bits)
3736        pub const offset: u32 = 24;
3737        /// Mask (1 bit: 1 << 24)
3738        pub const mask: u32 = 1 << offset;
3739        /// Read-only values (empty)
3740        pub mod R {}
3741        /// Write-only values (empty)
3742        pub mod W {}
3743        /// Read-write values (empty)
3744        pub mod RW {}
3745    }
3746
3747    /// Filter bits
3748    pub mod FB25 {
3749        /// Offset (25 bits)
3750        pub const offset: u32 = 25;
3751        /// Mask (1 bit: 1 << 25)
3752        pub const mask: u32 = 1 << offset;
3753        /// Read-only values (empty)
3754        pub mod R {}
3755        /// Write-only values (empty)
3756        pub mod W {}
3757        /// Read-write values (empty)
3758        pub mod RW {}
3759    }
3760
3761    /// Filter bits
3762    pub mod FB26 {
3763        /// Offset (26 bits)
3764        pub const offset: u32 = 26;
3765        /// Mask (1 bit: 1 << 26)
3766        pub const mask: u32 = 1 << offset;
3767        /// Read-only values (empty)
3768        pub mod R {}
3769        /// Write-only values (empty)
3770        pub mod W {}
3771        /// Read-write values (empty)
3772        pub mod RW {}
3773    }
3774
3775    /// Filter bits
3776    pub mod FB27 {
3777        /// Offset (27 bits)
3778        pub const offset: u32 = 27;
3779        /// Mask (1 bit: 1 << 27)
3780        pub const mask: u32 = 1 << offset;
3781        /// Read-only values (empty)
3782        pub mod R {}
3783        /// Write-only values (empty)
3784        pub mod W {}
3785        /// Read-write values (empty)
3786        pub mod RW {}
3787    }
3788
3789    /// Filter bits
3790    pub mod FB28 {
3791        /// Offset (28 bits)
3792        pub const offset: u32 = 28;
3793        /// Mask (1 bit: 1 << 28)
3794        pub const mask: u32 = 1 << offset;
3795        /// Read-only values (empty)
3796        pub mod R {}
3797        /// Write-only values (empty)
3798        pub mod W {}
3799        /// Read-write values (empty)
3800        pub mod RW {}
3801    }
3802
3803    /// Filter bits
3804    pub mod FB29 {
3805        /// Offset (29 bits)
3806        pub const offset: u32 = 29;
3807        /// Mask (1 bit: 1 << 29)
3808        pub const mask: u32 = 1 << offset;
3809        /// Read-only values (empty)
3810        pub mod R {}
3811        /// Write-only values (empty)
3812        pub mod W {}
3813        /// Read-write values (empty)
3814        pub mod RW {}
3815    }
3816
3817    /// Filter bits
3818    pub mod FB30 {
3819        /// Offset (30 bits)
3820        pub const offset: u32 = 30;
3821        /// Mask (1 bit: 1 << 30)
3822        pub const mask: u32 = 1 << offset;
3823        /// Read-only values (empty)
3824        pub mod R {}
3825        /// Write-only values (empty)
3826        pub mod W {}
3827        /// Read-write values (empty)
3828        pub mod RW {}
3829    }
3830
3831    /// Filter bits
3832    pub mod FB31 {
3833        /// Offset (31 bits)
3834        pub const offset: u32 = 31;
3835        /// Mask (1 bit: 1 << 31)
3836        pub const mask: u32 = 1 << offset;
3837        /// Read-only values (empty)
3838        pub mod R {}
3839        /// Write-only values (empty)
3840        pub mod W {}
3841        /// Read-write values (empty)
3842        pub mod RW {}
3843    }
3844}
3845
3846/// Filter bank 0 register 2
3847pub mod FR20 {
3848    pub use super::FR10::FB0;
3849    pub use super::FR10::FB1;
3850    pub use super::FR10::FB10;
3851    pub use super::FR10::FB11;
3852    pub use super::FR10::FB12;
3853    pub use super::FR10::FB13;
3854    pub use super::FR10::FB14;
3855    pub use super::FR10::FB15;
3856    pub use super::FR10::FB16;
3857    pub use super::FR10::FB17;
3858    pub use super::FR10::FB18;
3859    pub use super::FR10::FB19;
3860    pub use super::FR10::FB2;
3861    pub use super::FR10::FB20;
3862    pub use super::FR10::FB21;
3863    pub use super::FR10::FB22;
3864    pub use super::FR10::FB23;
3865    pub use super::FR10::FB24;
3866    pub use super::FR10::FB25;
3867    pub use super::FR10::FB26;
3868    pub use super::FR10::FB27;
3869    pub use super::FR10::FB28;
3870    pub use super::FR10::FB29;
3871    pub use super::FR10::FB3;
3872    pub use super::FR10::FB30;
3873    pub use super::FR10::FB31;
3874    pub use super::FR10::FB4;
3875    pub use super::FR10::FB5;
3876    pub use super::FR10::FB6;
3877    pub use super::FR10::FB7;
3878    pub use super::FR10::FB8;
3879    pub use super::FR10::FB9;
3880}
3881
3882/// Filter bank 0 register 1
3883pub mod FR11 {
3884    pub use super::FR10::FB0;
3885    pub use super::FR10::FB1;
3886    pub use super::FR10::FB10;
3887    pub use super::FR10::FB11;
3888    pub use super::FR10::FB12;
3889    pub use super::FR10::FB13;
3890    pub use super::FR10::FB14;
3891    pub use super::FR10::FB15;
3892    pub use super::FR10::FB16;
3893    pub use super::FR10::FB17;
3894    pub use super::FR10::FB18;
3895    pub use super::FR10::FB19;
3896    pub use super::FR10::FB2;
3897    pub use super::FR10::FB20;
3898    pub use super::FR10::FB21;
3899    pub use super::FR10::FB22;
3900    pub use super::FR10::FB23;
3901    pub use super::FR10::FB24;
3902    pub use super::FR10::FB25;
3903    pub use super::FR10::FB26;
3904    pub use super::FR10::FB27;
3905    pub use super::FR10::FB28;
3906    pub use super::FR10::FB29;
3907    pub use super::FR10::FB3;
3908    pub use super::FR10::FB30;
3909    pub use super::FR10::FB31;
3910    pub use super::FR10::FB4;
3911    pub use super::FR10::FB5;
3912    pub use super::FR10::FB6;
3913    pub use super::FR10::FB7;
3914    pub use super::FR10::FB8;
3915    pub use super::FR10::FB9;
3916}
3917
3918/// Filter bank 0 register 2
3919pub mod FR21 {
3920    pub use super::FR10::FB0;
3921    pub use super::FR10::FB1;
3922    pub use super::FR10::FB10;
3923    pub use super::FR10::FB11;
3924    pub use super::FR10::FB12;
3925    pub use super::FR10::FB13;
3926    pub use super::FR10::FB14;
3927    pub use super::FR10::FB15;
3928    pub use super::FR10::FB16;
3929    pub use super::FR10::FB17;
3930    pub use super::FR10::FB18;
3931    pub use super::FR10::FB19;
3932    pub use super::FR10::FB2;
3933    pub use super::FR10::FB20;
3934    pub use super::FR10::FB21;
3935    pub use super::FR10::FB22;
3936    pub use super::FR10::FB23;
3937    pub use super::FR10::FB24;
3938    pub use super::FR10::FB25;
3939    pub use super::FR10::FB26;
3940    pub use super::FR10::FB27;
3941    pub use super::FR10::FB28;
3942    pub use super::FR10::FB29;
3943    pub use super::FR10::FB3;
3944    pub use super::FR10::FB30;
3945    pub use super::FR10::FB31;
3946    pub use super::FR10::FB4;
3947    pub use super::FR10::FB5;
3948    pub use super::FR10::FB6;
3949    pub use super::FR10::FB7;
3950    pub use super::FR10::FB8;
3951    pub use super::FR10::FB9;
3952}
3953
3954/// Filter bank 0 register 1
3955pub mod FR12 {
3956    pub use super::FR10::FB0;
3957    pub use super::FR10::FB1;
3958    pub use super::FR10::FB10;
3959    pub use super::FR10::FB11;
3960    pub use super::FR10::FB12;
3961    pub use super::FR10::FB13;
3962    pub use super::FR10::FB14;
3963    pub use super::FR10::FB15;
3964    pub use super::FR10::FB16;
3965    pub use super::FR10::FB17;
3966    pub use super::FR10::FB18;
3967    pub use super::FR10::FB19;
3968    pub use super::FR10::FB2;
3969    pub use super::FR10::FB20;
3970    pub use super::FR10::FB21;
3971    pub use super::FR10::FB22;
3972    pub use super::FR10::FB23;
3973    pub use super::FR10::FB24;
3974    pub use super::FR10::FB25;
3975    pub use super::FR10::FB26;
3976    pub use super::FR10::FB27;
3977    pub use super::FR10::FB28;
3978    pub use super::FR10::FB29;
3979    pub use super::FR10::FB3;
3980    pub use super::FR10::FB30;
3981    pub use super::FR10::FB31;
3982    pub use super::FR10::FB4;
3983    pub use super::FR10::FB5;
3984    pub use super::FR10::FB6;
3985    pub use super::FR10::FB7;
3986    pub use super::FR10::FB8;
3987    pub use super::FR10::FB9;
3988}
3989
3990/// Filter bank 0 register 2
3991pub mod FR22 {
3992    pub use super::FR10::FB0;
3993    pub use super::FR10::FB1;
3994    pub use super::FR10::FB10;
3995    pub use super::FR10::FB11;
3996    pub use super::FR10::FB12;
3997    pub use super::FR10::FB13;
3998    pub use super::FR10::FB14;
3999    pub use super::FR10::FB15;
4000    pub use super::FR10::FB16;
4001    pub use super::FR10::FB17;
4002    pub use super::FR10::FB18;
4003    pub use super::FR10::FB19;
4004    pub use super::FR10::FB2;
4005    pub use super::FR10::FB20;
4006    pub use super::FR10::FB21;
4007    pub use super::FR10::FB22;
4008    pub use super::FR10::FB23;
4009    pub use super::FR10::FB24;
4010    pub use super::FR10::FB25;
4011    pub use super::FR10::FB26;
4012    pub use super::FR10::FB27;
4013    pub use super::FR10::FB28;
4014    pub use super::FR10::FB29;
4015    pub use super::FR10::FB3;
4016    pub use super::FR10::FB30;
4017    pub use super::FR10::FB31;
4018    pub use super::FR10::FB4;
4019    pub use super::FR10::FB5;
4020    pub use super::FR10::FB6;
4021    pub use super::FR10::FB7;
4022    pub use super::FR10::FB8;
4023    pub use super::FR10::FB9;
4024}
4025
4026/// Filter bank 0 register 1
4027pub mod FR13 {
4028    pub use super::FR10::FB0;
4029    pub use super::FR10::FB1;
4030    pub use super::FR10::FB10;
4031    pub use super::FR10::FB11;
4032    pub use super::FR10::FB12;
4033    pub use super::FR10::FB13;
4034    pub use super::FR10::FB14;
4035    pub use super::FR10::FB15;
4036    pub use super::FR10::FB16;
4037    pub use super::FR10::FB17;
4038    pub use super::FR10::FB18;
4039    pub use super::FR10::FB19;
4040    pub use super::FR10::FB2;
4041    pub use super::FR10::FB20;
4042    pub use super::FR10::FB21;
4043    pub use super::FR10::FB22;
4044    pub use super::FR10::FB23;
4045    pub use super::FR10::FB24;
4046    pub use super::FR10::FB25;
4047    pub use super::FR10::FB26;
4048    pub use super::FR10::FB27;
4049    pub use super::FR10::FB28;
4050    pub use super::FR10::FB29;
4051    pub use super::FR10::FB3;
4052    pub use super::FR10::FB30;
4053    pub use super::FR10::FB31;
4054    pub use super::FR10::FB4;
4055    pub use super::FR10::FB5;
4056    pub use super::FR10::FB6;
4057    pub use super::FR10::FB7;
4058    pub use super::FR10::FB8;
4059    pub use super::FR10::FB9;
4060}
4061
4062/// Filter bank 0 register 2
4063pub mod FR23 {
4064    pub use super::FR10::FB0;
4065    pub use super::FR10::FB1;
4066    pub use super::FR10::FB10;
4067    pub use super::FR10::FB11;
4068    pub use super::FR10::FB12;
4069    pub use super::FR10::FB13;
4070    pub use super::FR10::FB14;
4071    pub use super::FR10::FB15;
4072    pub use super::FR10::FB16;
4073    pub use super::FR10::FB17;
4074    pub use super::FR10::FB18;
4075    pub use super::FR10::FB19;
4076    pub use super::FR10::FB2;
4077    pub use super::FR10::FB20;
4078    pub use super::FR10::FB21;
4079    pub use super::FR10::FB22;
4080    pub use super::FR10::FB23;
4081    pub use super::FR10::FB24;
4082    pub use super::FR10::FB25;
4083    pub use super::FR10::FB26;
4084    pub use super::FR10::FB27;
4085    pub use super::FR10::FB28;
4086    pub use super::FR10::FB29;
4087    pub use super::FR10::FB3;
4088    pub use super::FR10::FB30;
4089    pub use super::FR10::FB31;
4090    pub use super::FR10::FB4;
4091    pub use super::FR10::FB5;
4092    pub use super::FR10::FB6;
4093    pub use super::FR10::FB7;
4094    pub use super::FR10::FB8;
4095    pub use super::FR10::FB9;
4096}
4097
4098/// Filter bank 0 register 1
4099pub mod FR14 {
4100    pub use super::FR10::FB0;
4101    pub use super::FR10::FB1;
4102    pub use super::FR10::FB10;
4103    pub use super::FR10::FB11;
4104    pub use super::FR10::FB12;
4105    pub use super::FR10::FB13;
4106    pub use super::FR10::FB14;
4107    pub use super::FR10::FB15;
4108    pub use super::FR10::FB16;
4109    pub use super::FR10::FB17;
4110    pub use super::FR10::FB18;
4111    pub use super::FR10::FB19;
4112    pub use super::FR10::FB2;
4113    pub use super::FR10::FB20;
4114    pub use super::FR10::FB21;
4115    pub use super::FR10::FB22;
4116    pub use super::FR10::FB23;
4117    pub use super::FR10::FB24;
4118    pub use super::FR10::FB25;
4119    pub use super::FR10::FB26;
4120    pub use super::FR10::FB27;
4121    pub use super::FR10::FB28;
4122    pub use super::FR10::FB29;
4123    pub use super::FR10::FB3;
4124    pub use super::FR10::FB30;
4125    pub use super::FR10::FB31;
4126    pub use super::FR10::FB4;
4127    pub use super::FR10::FB5;
4128    pub use super::FR10::FB6;
4129    pub use super::FR10::FB7;
4130    pub use super::FR10::FB8;
4131    pub use super::FR10::FB9;
4132}
4133
4134/// Filter bank 0 register 2
4135pub mod FR24 {
4136    pub use super::FR10::FB0;
4137    pub use super::FR10::FB1;
4138    pub use super::FR10::FB10;
4139    pub use super::FR10::FB11;
4140    pub use super::FR10::FB12;
4141    pub use super::FR10::FB13;
4142    pub use super::FR10::FB14;
4143    pub use super::FR10::FB15;
4144    pub use super::FR10::FB16;
4145    pub use super::FR10::FB17;
4146    pub use super::FR10::FB18;
4147    pub use super::FR10::FB19;
4148    pub use super::FR10::FB2;
4149    pub use super::FR10::FB20;
4150    pub use super::FR10::FB21;
4151    pub use super::FR10::FB22;
4152    pub use super::FR10::FB23;
4153    pub use super::FR10::FB24;
4154    pub use super::FR10::FB25;
4155    pub use super::FR10::FB26;
4156    pub use super::FR10::FB27;
4157    pub use super::FR10::FB28;
4158    pub use super::FR10::FB29;
4159    pub use super::FR10::FB3;
4160    pub use super::FR10::FB30;
4161    pub use super::FR10::FB31;
4162    pub use super::FR10::FB4;
4163    pub use super::FR10::FB5;
4164    pub use super::FR10::FB6;
4165    pub use super::FR10::FB7;
4166    pub use super::FR10::FB8;
4167    pub use super::FR10::FB9;
4168}
4169
4170/// Filter bank 0 register 1
4171pub mod FR15 {
4172    pub use super::FR10::FB0;
4173    pub use super::FR10::FB1;
4174    pub use super::FR10::FB10;
4175    pub use super::FR10::FB11;
4176    pub use super::FR10::FB12;
4177    pub use super::FR10::FB13;
4178    pub use super::FR10::FB14;
4179    pub use super::FR10::FB15;
4180    pub use super::FR10::FB16;
4181    pub use super::FR10::FB17;
4182    pub use super::FR10::FB18;
4183    pub use super::FR10::FB19;
4184    pub use super::FR10::FB2;
4185    pub use super::FR10::FB20;
4186    pub use super::FR10::FB21;
4187    pub use super::FR10::FB22;
4188    pub use super::FR10::FB23;
4189    pub use super::FR10::FB24;
4190    pub use super::FR10::FB25;
4191    pub use super::FR10::FB26;
4192    pub use super::FR10::FB27;
4193    pub use super::FR10::FB28;
4194    pub use super::FR10::FB29;
4195    pub use super::FR10::FB3;
4196    pub use super::FR10::FB30;
4197    pub use super::FR10::FB31;
4198    pub use super::FR10::FB4;
4199    pub use super::FR10::FB5;
4200    pub use super::FR10::FB6;
4201    pub use super::FR10::FB7;
4202    pub use super::FR10::FB8;
4203    pub use super::FR10::FB9;
4204}
4205
4206/// Filter bank 0 register 2
4207pub mod FR25 {
4208    pub use super::FR10::FB0;
4209    pub use super::FR10::FB1;
4210    pub use super::FR10::FB10;
4211    pub use super::FR10::FB11;
4212    pub use super::FR10::FB12;
4213    pub use super::FR10::FB13;
4214    pub use super::FR10::FB14;
4215    pub use super::FR10::FB15;
4216    pub use super::FR10::FB16;
4217    pub use super::FR10::FB17;
4218    pub use super::FR10::FB18;
4219    pub use super::FR10::FB19;
4220    pub use super::FR10::FB2;
4221    pub use super::FR10::FB20;
4222    pub use super::FR10::FB21;
4223    pub use super::FR10::FB22;
4224    pub use super::FR10::FB23;
4225    pub use super::FR10::FB24;
4226    pub use super::FR10::FB25;
4227    pub use super::FR10::FB26;
4228    pub use super::FR10::FB27;
4229    pub use super::FR10::FB28;
4230    pub use super::FR10::FB29;
4231    pub use super::FR10::FB3;
4232    pub use super::FR10::FB30;
4233    pub use super::FR10::FB31;
4234    pub use super::FR10::FB4;
4235    pub use super::FR10::FB5;
4236    pub use super::FR10::FB6;
4237    pub use super::FR10::FB7;
4238    pub use super::FR10::FB8;
4239    pub use super::FR10::FB9;
4240}
4241
4242/// Filter bank 0 register 1
4243pub mod FR16 {
4244    pub use super::FR10::FB0;
4245    pub use super::FR10::FB1;
4246    pub use super::FR10::FB10;
4247    pub use super::FR10::FB11;
4248    pub use super::FR10::FB12;
4249    pub use super::FR10::FB13;
4250    pub use super::FR10::FB14;
4251    pub use super::FR10::FB15;
4252    pub use super::FR10::FB16;
4253    pub use super::FR10::FB17;
4254    pub use super::FR10::FB18;
4255    pub use super::FR10::FB19;
4256    pub use super::FR10::FB2;
4257    pub use super::FR10::FB20;
4258    pub use super::FR10::FB21;
4259    pub use super::FR10::FB22;
4260    pub use super::FR10::FB23;
4261    pub use super::FR10::FB24;
4262    pub use super::FR10::FB25;
4263    pub use super::FR10::FB26;
4264    pub use super::FR10::FB27;
4265    pub use super::FR10::FB28;
4266    pub use super::FR10::FB29;
4267    pub use super::FR10::FB3;
4268    pub use super::FR10::FB30;
4269    pub use super::FR10::FB31;
4270    pub use super::FR10::FB4;
4271    pub use super::FR10::FB5;
4272    pub use super::FR10::FB6;
4273    pub use super::FR10::FB7;
4274    pub use super::FR10::FB8;
4275    pub use super::FR10::FB9;
4276}
4277
4278/// Filter bank 0 register 2
4279pub mod FR26 {
4280    pub use super::FR10::FB0;
4281    pub use super::FR10::FB1;
4282    pub use super::FR10::FB10;
4283    pub use super::FR10::FB11;
4284    pub use super::FR10::FB12;
4285    pub use super::FR10::FB13;
4286    pub use super::FR10::FB14;
4287    pub use super::FR10::FB15;
4288    pub use super::FR10::FB16;
4289    pub use super::FR10::FB17;
4290    pub use super::FR10::FB18;
4291    pub use super::FR10::FB19;
4292    pub use super::FR10::FB2;
4293    pub use super::FR10::FB20;
4294    pub use super::FR10::FB21;
4295    pub use super::FR10::FB22;
4296    pub use super::FR10::FB23;
4297    pub use super::FR10::FB24;
4298    pub use super::FR10::FB25;
4299    pub use super::FR10::FB26;
4300    pub use super::FR10::FB27;
4301    pub use super::FR10::FB28;
4302    pub use super::FR10::FB29;
4303    pub use super::FR10::FB3;
4304    pub use super::FR10::FB30;
4305    pub use super::FR10::FB31;
4306    pub use super::FR10::FB4;
4307    pub use super::FR10::FB5;
4308    pub use super::FR10::FB6;
4309    pub use super::FR10::FB7;
4310    pub use super::FR10::FB8;
4311    pub use super::FR10::FB9;
4312}
4313
4314/// Filter bank 0 register 1
4315pub mod FR17 {
4316    pub use super::FR10::FB0;
4317    pub use super::FR10::FB1;
4318    pub use super::FR10::FB10;
4319    pub use super::FR10::FB11;
4320    pub use super::FR10::FB12;
4321    pub use super::FR10::FB13;
4322    pub use super::FR10::FB14;
4323    pub use super::FR10::FB15;
4324    pub use super::FR10::FB16;
4325    pub use super::FR10::FB17;
4326    pub use super::FR10::FB18;
4327    pub use super::FR10::FB19;
4328    pub use super::FR10::FB2;
4329    pub use super::FR10::FB20;
4330    pub use super::FR10::FB21;
4331    pub use super::FR10::FB22;
4332    pub use super::FR10::FB23;
4333    pub use super::FR10::FB24;
4334    pub use super::FR10::FB25;
4335    pub use super::FR10::FB26;
4336    pub use super::FR10::FB27;
4337    pub use super::FR10::FB28;
4338    pub use super::FR10::FB29;
4339    pub use super::FR10::FB3;
4340    pub use super::FR10::FB30;
4341    pub use super::FR10::FB31;
4342    pub use super::FR10::FB4;
4343    pub use super::FR10::FB5;
4344    pub use super::FR10::FB6;
4345    pub use super::FR10::FB7;
4346    pub use super::FR10::FB8;
4347    pub use super::FR10::FB9;
4348}
4349
4350/// Filter bank 0 register 2
4351pub mod FR27 {
4352    pub use super::FR10::FB0;
4353    pub use super::FR10::FB1;
4354    pub use super::FR10::FB10;
4355    pub use super::FR10::FB11;
4356    pub use super::FR10::FB12;
4357    pub use super::FR10::FB13;
4358    pub use super::FR10::FB14;
4359    pub use super::FR10::FB15;
4360    pub use super::FR10::FB16;
4361    pub use super::FR10::FB17;
4362    pub use super::FR10::FB18;
4363    pub use super::FR10::FB19;
4364    pub use super::FR10::FB2;
4365    pub use super::FR10::FB20;
4366    pub use super::FR10::FB21;
4367    pub use super::FR10::FB22;
4368    pub use super::FR10::FB23;
4369    pub use super::FR10::FB24;
4370    pub use super::FR10::FB25;
4371    pub use super::FR10::FB26;
4372    pub use super::FR10::FB27;
4373    pub use super::FR10::FB28;
4374    pub use super::FR10::FB29;
4375    pub use super::FR10::FB3;
4376    pub use super::FR10::FB30;
4377    pub use super::FR10::FB31;
4378    pub use super::FR10::FB4;
4379    pub use super::FR10::FB5;
4380    pub use super::FR10::FB6;
4381    pub use super::FR10::FB7;
4382    pub use super::FR10::FB8;
4383    pub use super::FR10::FB9;
4384}
4385
4386/// Filter bank 0 register 1
4387pub mod FR18 {
4388    pub use super::FR10::FB0;
4389    pub use super::FR10::FB1;
4390    pub use super::FR10::FB10;
4391    pub use super::FR10::FB11;
4392    pub use super::FR10::FB12;
4393    pub use super::FR10::FB13;
4394    pub use super::FR10::FB14;
4395    pub use super::FR10::FB15;
4396    pub use super::FR10::FB16;
4397    pub use super::FR10::FB17;
4398    pub use super::FR10::FB18;
4399    pub use super::FR10::FB19;
4400    pub use super::FR10::FB2;
4401    pub use super::FR10::FB20;
4402    pub use super::FR10::FB21;
4403    pub use super::FR10::FB22;
4404    pub use super::FR10::FB23;
4405    pub use super::FR10::FB24;
4406    pub use super::FR10::FB25;
4407    pub use super::FR10::FB26;
4408    pub use super::FR10::FB27;
4409    pub use super::FR10::FB28;
4410    pub use super::FR10::FB29;
4411    pub use super::FR10::FB3;
4412    pub use super::FR10::FB30;
4413    pub use super::FR10::FB31;
4414    pub use super::FR10::FB4;
4415    pub use super::FR10::FB5;
4416    pub use super::FR10::FB6;
4417    pub use super::FR10::FB7;
4418    pub use super::FR10::FB8;
4419    pub use super::FR10::FB9;
4420}
4421
4422/// Filter bank 0 register 2
4423pub mod FR28 {
4424    pub use super::FR10::FB0;
4425    pub use super::FR10::FB1;
4426    pub use super::FR10::FB10;
4427    pub use super::FR10::FB11;
4428    pub use super::FR10::FB12;
4429    pub use super::FR10::FB13;
4430    pub use super::FR10::FB14;
4431    pub use super::FR10::FB15;
4432    pub use super::FR10::FB16;
4433    pub use super::FR10::FB17;
4434    pub use super::FR10::FB18;
4435    pub use super::FR10::FB19;
4436    pub use super::FR10::FB2;
4437    pub use super::FR10::FB20;
4438    pub use super::FR10::FB21;
4439    pub use super::FR10::FB22;
4440    pub use super::FR10::FB23;
4441    pub use super::FR10::FB24;
4442    pub use super::FR10::FB25;
4443    pub use super::FR10::FB26;
4444    pub use super::FR10::FB27;
4445    pub use super::FR10::FB28;
4446    pub use super::FR10::FB29;
4447    pub use super::FR10::FB3;
4448    pub use super::FR10::FB30;
4449    pub use super::FR10::FB31;
4450    pub use super::FR10::FB4;
4451    pub use super::FR10::FB5;
4452    pub use super::FR10::FB6;
4453    pub use super::FR10::FB7;
4454    pub use super::FR10::FB8;
4455    pub use super::FR10::FB9;
4456}
4457
4458/// Filter bank 0 register 1
4459pub mod FR19 {
4460    pub use super::FR10::FB0;
4461    pub use super::FR10::FB1;
4462    pub use super::FR10::FB10;
4463    pub use super::FR10::FB11;
4464    pub use super::FR10::FB12;
4465    pub use super::FR10::FB13;
4466    pub use super::FR10::FB14;
4467    pub use super::FR10::FB15;
4468    pub use super::FR10::FB16;
4469    pub use super::FR10::FB17;
4470    pub use super::FR10::FB18;
4471    pub use super::FR10::FB19;
4472    pub use super::FR10::FB2;
4473    pub use super::FR10::FB20;
4474    pub use super::FR10::FB21;
4475    pub use super::FR10::FB22;
4476    pub use super::FR10::FB23;
4477    pub use super::FR10::FB24;
4478    pub use super::FR10::FB25;
4479    pub use super::FR10::FB26;
4480    pub use super::FR10::FB27;
4481    pub use super::FR10::FB28;
4482    pub use super::FR10::FB29;
4483    pub use super::FR10::FB3;
4484    pub use super::FR10::FB30;
4485    pub use super::FR10::FB31;
4486    pub use super::FR10::FB4;
4487    pub use super::FR10::FB5;
4488    pub use super::FR10::FB6;
4489    pub use super::FR10::FB7;
4490    pub use super::FR10::FB8;
4491    pub use super::FR10::FB9;
4492}
4493
4494/// Filter bank 0 register 2
4495pub mod FR29 {
4496    pub use super::FR10::FB0;
4497    pub use super::FR10::FB1;
4498    pub use super::FR10::FB10;
4499    pub use super::FR10::FB11;
4500    pub use super::FR10::FB12;
4501    pub use super::FR10::FB13;
4502    pub use super::FR10::FB14;
4503    pub use super::FR10::FB15;
4504    pub use super::FR10::FB16;
4505    pub use super::FR10::FB17;
4506    pub use super::FR10::FB18;
4507    pub use super::FR10::FB19;
4508    pub use super::FR10::FB2;
4509    pub use super::FR10::FB20;
4510    pub use super::FR10::FB21;
4511    pub use super::FR10::FB22;
4512    pub use super::FR10::FB23;
4513    pub use super::FR10::FB24;
4514    pub use super::FR10::FB25;
4515    pub use super::FR10::FB26;
4516    pub use super::FR10::FB27;
4517    pub use super::FR10::FB28;
4518    pub use super::FR10::FB29;
4519    pub use super::FR10::FB3;
4520    pub use super::FR10::FB30;
4521    pub use super::FR10::FB31;
4522    pub use super::FR10::FB4;
4523    pub use super::FR10::FB5;
4524    pub use super::FR10::FB6;
4525    pub use super::FR10::FB7;
4526    pub use super::FR10::FB8;
4527    pub use super::FR10::FB9;
4528}
4529
4530/// Filter bank 0 register 1
4531pub mod FR110 {
4532    pub use super::FR10::FB0;
4533    pub use super::FR10::FB1;
4534    pub use super::FR10::FB10;
4535    pub use super::FR10::FB11;
4536    pub use super::FR10::FB12;
4537    pub use super::FR10::FB13;
4538    pub use super::FR10::FB14;
4539    pub use super::FR10::FB15;
4540    pub use super::FR10::FB16;
4541    pub use super::FR10::FB17;
4542    pub use super::FR10::FB18;
4543    pub use super::FR10::FB19;
4544    pub use super::FR10::FB2;
4545    pub use super::FR10::FB20;
4546    pub use super::FR10::FB21;
4547    pub use super::FR10::FB22;
4548    pub use super::FR10::FB23;
4549    pub use super::FR10::FB24;
4550    pub use super::FR10::FB25;
4551    pub use super::FR10::FB26;
4552    pub use super::FR10::FB27;
4553    pub use super::FR10::FB28;
4554    pub use super::FR10::FB29;
4555    pub use super::FR10::FB3;
4556    pub use super::FR10::FB30;
4557    pub use super::FR10::FB31;
4558    pub use super::FR10::FB4;
4559    pub use super::FR10::FB5;
4560    pub use super::FR10::FB6;
4561    pub use super::FR10::FB7;
4562    pub use super::FR10::FB8;
4563    pub use super::FR10::FB9;
4564}
4565
4566/// Filter bank 0 register 2
4567pub mod FR210 {
4568    pub use super::FR10::FB0;
4569    pub use super::FR10::FB1;
4570    pub use super::FR10::FB10;
4571    pub use super::FR10::FB11;
4572    pub use super::FR10::FB12;
4573    pub use super::FR10::FB13;
4574    pub use super::FR10::FB14;
4575    pub use super::FR10::FB15;
4576    pub use super::FR10::FB16;
4577    pub use super::FR10::FB17;
4578    pub use super::FR10::FB18;
4579    pub use super::FR10::FB19;
4580    pub use super::FR10::FB2;
4581    pub use super::FR10::FB20;
4582    pub use super::FR10::FB21;
4583    pub use super::FR10::FB22;
4584    pub use super::FR10::FB23;
4585    pub use super::FR10::FB24;
4586    pub use super::FR10::FB25;
4587    pub use super::FR10::FB26;
4588    pub use super::FR10::FB27;
4589    pub use super::FR10::FB28;
4590    pub use super::FR10::FB29;
4591    pub use super::FR10::FB3;
4592    pub use super::FR10::FB30;
4593    pub use super::FR10::FB31;
4594    pub use super::FR10::FB4;
4595    pub use super::FR10::FB5;
4596    pub use super::FR10::FB6;
4597    pub use super::FR10::FB7;
4598    pub use super::FR10::FB8;
4599    pub use super::FR10::FB9;
4600}
4601
4602/// Filter bank 0 register 1
4603pub mod FR111 {
4604    pub use super::FR10::FB0;
4605    pub use super::FR10::FB1;
4606    pub use super::FR10::FB10;
4607    pub use super::FR10::FB11;
4608    pub use super::FR10::FB12;
4609    pub use super::FR10::FB13;
4610    pub use super::FR10::FB14;
4611    pub use super::FR10::FB15;
4612    pub use super::FR10::FB16;
4613    pub use super::FR10::FB17;
4614    pub use super::FR10::FB18;
4615    pub use super::FR10::FB19;
4616    pub use super::FR10::FB2;
4617    pub use super::FR10::FB20;
4618    pub use super::FR10::FB21;
4619    pub use super::FR10::FB22;
4620    pub use super::FR10::FB23;
4621    pub use super::FR10::FB24;
4622    pub use super::FR10::FB25;
4623    pub use super::FR10::FB26;
4624    pub use super::FR10::FB27;
4625    pub use super::FR10::FB28;
4626    pub use super::FR10::FB29;
4627    pub use super::FR10::FB3;
4628    pub use super::FR10::FB30;
4629    pub use super::FR10::FB31;
4630    pub use super::FR10::FB4;
4631    pub use super::FR10::FB5;
4632    pub use super::FR10::FB6;
4633    pub use super::FR10::FB7;
4634    pub use super::FR10::FB8;
4635    pub use super::FR10::FB9;
4636}
4637
4638/// Filter bank 0 register 2
4639pub mod FR211 {
4640    pub use super::FR10::FB0;
4641    pub use super::FR10::FB1;
4642    pub use super::FR10::FB10;
4643    pub use super::FR10::FB11;
4644    pub use super::FR10::FB12;
4645    pub use super::FR10::FB13;
4646    pub use super::FR10::FB14;
4647    pub use super::FR10::FB15;
4648    pub use super::FR10::FB16;
4649    pub use super::FR10::FB17;
4650    pub use super::FR10::FB18;
4651    pub use super::FR10::FB19;
4652    pub use super::FR10::FB2;
4653    pub use super::FR10::FB20;
4654    pub use super::FR10::FB21;
4655    pub use super::FR10::FB22;
4656    pub use super::FR10::FB23;
4657    pub use super::FR10::FB24;
4658    pub use super::FR10::FB25;
4659    pub use super::FR10::FB26;
4660    pub use super::FR10::FB27;
4661    pub use super::FR10::FB28;
4662    pub use super::FR10::FB29;
4663    pub use super::FR10::FB3;
4664    pub use super::FR10::FB30;
4665    pub use super::FR10::FB31;
4666    pub use super::FR10::FB4;
4667    pub use super::FR10::FB5;
4668    pub use super::FR10::FB6;
4669    pub use super::FR10::FB7;
4670    pub use super::FR10::FB8;
4671    pub use super::FR10::FB9;
4672}
4673
4674/// Filter bank 0 register 1
4675pub mod FR112 {
4676    pub use super::FR10::FB0;
4677    pub use super::FR10::FB1;
4678    pub use super::FR10::FB10;
4679    pub use super::FR10::FB11;
4680    pub use super::FR10::FB12;
4681    pub use super::FR10::FB13;
4682    pub use super::FR10::FB14;
4683    pub use super::FR10::FB15;
4684    pub use super::FR10::FB16;
4685    pub use super::FR10::FB17;
4686    pub use super::FR10::FB18;
4687    pub use super::FR10::FB19;
4688    pub use super::FR10::FB2;
4689    pub use super::FR10::FB20;
4690    pub use super::FR10::FB21;
4691    pub use super::FR10::FB22;
4692    pub use super::FR10::FB23;
4693    pub use super::FR10::FB24;
4694    pub use super::FR10::FB25;
4695    pub use super::FR10::FB26;
4696    pub use super::FR10::FB27;
4697    pub use super::FR10::FB28;
4698    pub use super::FR10::FB29;
4699    pub use super::FR10::FB3;
4700    pub use super::FR10::FB30;
4701    pub use super::FR10::FB31;
4702    pub use super::FR10::FB4;
4703    pub use super::FR10::FB5;
4704    pub use super::FR10::FB6;
4705    pub use super::FR10::FB7;
4706    pub use super::FR10::FB8;
4707    pub use super::FR10::FB9;
4708}
4709
4710/// Filter bank 0 register 2
4711pub mod FR212 {
4712    pub use super::FR10::FB0;
4713    pub use super::FR10::FB1;
4714    pub use super::FR10::FB10;
4715    pub use super::FR10::FB11;
4716    pub use super::FR10::FB12;
4717    pub use super::FR10::FB13;
4718    pub use super::FR10::FB14;
4719    pub use super::FR10::FB15;
4720    pub use super::FR10::FB16;
4721    pub use super::FR10::FB17;
4722    pub use super::FR10::FB18;
4723    pub use super::FR10::FB19;
4724    pub use super::FR10::FB2;
4725    pub use super::FR10::FB20;
4726    pub use super::FR10::FB21;
4727    pub use super::FR10::FB22;
4728    pub use super::FR10::FB23;
4729    pub use super::FR10::FB24;
4730    pub use super::FR10::FB25;
4731    pub use super::FR10::FB26;
4732    pub use super::FR10::FB27;
4733    pub use super::FR10::FB28;
4734    pub use super::FR10::FB29;
4735    pub use super::FR10::FB3;
4736    pub use super::FR10::FB30;
4737    pub use super::FR10::FB31;
4738    pub use super::FR10::FB4;
4739    pub use super::FR10::FB5;
4740    pub use super::FR10::FB6;
4741    pub use super::FR10::FB7;
4742    pub use super::FR10::FB8;
4743    pub use super::FR10::FB9;
4744}
4745
4746/// Filter bank 0 register 1
4747pub mod FR113 {
4748    pub use super::FR10::FB0;
4749    pub use super::FR10::FB1;
4750    pub use super::FR10::FB10;
4751    pub use super::FR10::FB11;
4752    pub use super::FR10::FB12;
4753    pub use super::FR10::FB13;
4754    pub use super::FR10::FB14;
4755    pub use super::FR10::FB15;
4756    pub use super::FR10::FB16;
4757    pub use super::FR10::FB17;
4758    pub use super::FR10::FB18;
4759    pub use super::FR10::FB19;
4760    pub use super::FR10::FB2;
4761    pub use super::FR10::FB20;
4762    pub use super::FR10::FB21;
4763    pub use super::FR10::FB22;
4764    pub use super::FR10::FB23;
4765    pub use super::FR10::FB24;
4766    pub use super::FR10::FB25;
4767    pub use super::FR10::FB26;
4768    pub use super::FR10::FB27;
4769    pub use super::FR10::FB28;
4770    pub use super::FR10::FB29;
4771    pub use super::FR10::FB3;
4772    pub use super::FR10::FB30;
4773    pub use super::FR10::FB31;
4774    pub use super::FR10::FB4;
4775    pub use super::FR10::FB5;
4776    pub use super::FR10::FB6;
4777    pub use super::FR10::FB7;
4778    pub use super::FR10::FB8;
4779    pub use super::FR10::FB9;
4780}
4781
4782/// Filter bank 0 register 2
4783pub mod FR213 {
4784    pub use super::FR10::FB0;
4785    pub use super::FR10::FB1;
4786    pub use super::FR10::FB10;
4787    pub use super::FR10::FB11;
4788    pub use super::FR10::FB12;
4789    pub use super::FR10::FB13;
4790    pub use super::FR10::FB14;
4791    pub use super::FR10::FB15;
4792    pub use super::FR10::FB16;
4793    pub use super::FR10::FB17;
4794    pub use super::FR10::FB18;
4795    pub use super::FR10::FB19;
4796    pub use super::FR10::FB2;
4797    pub use super::FR10::FB20;
4798    pub use super::FR10::FB21;
4799    pub use super::FR10::FB22;
4800    pub use super::FR10::FB23;
4801    pub use super::FR10::FB24;
4802    pub use super::FR10::FB25;
4803    pub use super::FR10::FB26;
4804    pub use super::FR10::FB27;
4805    pub use super::FR10::FB28;
4806    pub use super::FR10::FB29;
4807    pub use super::FR10::FB3;
4808    pub use super::FR10::FB30;
4809    pub use super::FR10::FB31;
4810    pub use super::FR10::FB4;
4811    pub use super::FR10::FB5;
4812    pub use super::FR10::FB6;
4813    pub use super::FR10::FB7;
4814    pub use super::FR10::FB8;
4815    pub use super::FR10::FB9;
4816}
4817
4818/// Filter bank 0 register 1
4819pub mod FR114 {
4820    pub use super::FR10::FB0;
4821    pub use super::FR10::FB1;
4822    pub use super::FR10::FB10;
4823    pub use super::FR10::FB11;
4824    pub use super::FR10::FB12;
4825    pub use super::FR10::FB13;
4826    pub use super::FR10::FB14;
4827    pub use super::FR10::FB15;
4828    pub use super::FR10::FB16;
4829    pub use super::FR10::FB17;
4830    pub use super::FR10::FB18;
4831    pub use super::FR10::FB19;
4832    pub use super::FR10::FB2;
4833    pub use super::FR10::FB20;
4834    pub use super::FR10::FB21;
4835    pub use super::FR10::FB22;
4836    pub use super::FR10::FB23;
4837    pub use super::FR10::FB24;
4838    pub use super::FR10::FB25;
4839    pub use super::FR10::FB26;
4840    pub use super::FR10::FB27;
4841    pub use super::FR10::FB28;
4842    pub use super::FR10::FB29;
4843    pub use super::FR10::FB3;
4844    pub use super::FR10::FB30;
4845    pub use super::FR10::FB31;
4846    pub use super::FR10::FB4;
4847    pub use super::FR10::FB5;
4848    pub use super::FR10::FB6;
4849    pub use super::FR10::FB7;
4850    pub use super::FR10::FB8;
4851    pub use super::FR10::FB9;
4852}
4853
4854/// Filter bank 0 register 2
4855pub mod FR214 {
4856    pub use super::FR10::FB0;
4857    pub use super::FR10::FB1;
4858    pub use super::FR10::FB10;
4859    pub use super::FR10::FB11;
4860    pub use super::FR10::FB12;
4861    pub use super::FR10::FB13;
4862    pub use super::FR10::FB14;
4863    pub use super::FR10::FB15;
4864    pub use super::FR10::FB16;
4865    pub use super::FR10::FB17;
4866    pub use super::FR10::FB18;
4867    pub use super::FR10::FB19;
4868    pub use super::FR10::FB2;
4869    pub use super::FR10::FB20;
4870    pub use super::FR10::FB21;
4871    pub use super::FR10::FB22;
4872    pub use super::FR10::FB23;
4873    pub use super::FR10::FB24;
4874    pub use super::FR10::FB25;
4875    pub use super::FR10::FB26;
4876    pub use super::FR10::FB27;
4877    pub use super::FR10::FB28;
4878    pub use super::FR10::FB29;
4879    pub use super::FR10::FB3;
4880    pub use super::FR10::FB30;
4881    pub use super::FR10::FB31;
4882    pub use super::FR10::FB4;
4883    pub use super::FR10::FB5;
4884    pub use super::FR10::FB6;
4885    pub use super::FR10::FB7;
4886    pub use super::FR10::FB8;
4887    pub use super::FR10::FB9;
4888}
4889
4890/// Filter bank 0 register 1
4891pub mod FR115 {
4892    pub use super::FR10::FB0;
4893    pub use super::FR10::FB1;
4894    pub use super::FR10::FB10;
4895    pub use super::FR10::FB11;
4896    pub use super::FR10::FB12;
4897    pub use super::FR10::FB13;
4898    pub use super::FR10::FB14;
4899    pub use super::FR10::FB15;
4900    pub use super::FR10::FB16;
4901    pub use super::FR10::FB17;
4902    pub use super::FR10::FB18;
4903    pub use super::FR10::FB19;
4904    pub use super::FR10::FB2;
4905    pub use super::FR10::FB20;
4906    pub use super::FR10::FB21;
4907    pub use super::FR10::FB22;
4908    pub use super::FR10::FB23;
4909    pub use super::FR10::FB24;
4910    pub use super::FR10::FB25;
4911    pub use super::FR10::FB26;
4912    pub use super::FR10::FB27;
4913    pub use super::FR10::FB28;
4914    pub use super::FR10::FB29;
4915    pub use super::FR10::FB3;
4916    pub use super::FR10::FB30;
4917    pub use super::FR10::FB31;
4918    pub use super::FR10::FB4;
4919    pub use super::FR10::FB5;
4920    pub use super::FR10::FB6;
4921    pub use super::FR10::FB7;
4922    pub use super::FR10::FB8;
4923    pub use super::FR10::FB9;
4924}
4925
4926/// Filter bank 0 register 2
4927pub mod FR215 {
4928    pub use super::FR10::FB0;
4929    pub use super::FR10::FB1;
4930    pub use super::FR10::FB10;
4931    pub use super::FR10::FB11;
4932    pub use super::FR10::FB12;
4933    pub use super::FR10::FB13;
4934    pub use super::FR10::FB14;
4935    pub use super::FR10::FB15;
4936    pub use super::FR10::FB16;
4937    pub use super::FR10::FB17;
4938    pub use super::FR10::FB18;
4939    pub use super::FR10::FB19;
4940    pub use super::FR10::FB2;
4941    pub use super::FR10::FB20;
4942    pub use super::FR10::FB21;
4943    pub use super::FR10::FB22;
4944    pub use super::FR10::FB23;
4945    pub use super::FR10::FB24;
4946    pub use super::FR10::FB25;
4947    pub use super::FR10::FB26;
4948    pub use super::FR10::FB27;
4949    pub use super::FR10::FB28;
4950    pub use super::FR10::FB29;
4951    pub use super::FR10::FB3;
4952    pub use super::FR10::FB30;
4953    pub use super::FR10::FB31;
4954    pub use super::FR10::FB4;
4955    pub use super::FR10::FB5;
4956    pub use super::FR10::FB6;
4957    pub use super::FR10::FB7;
4958    pub use super::FR10::FB8;
4959    pub use super::FR10::FB9;
4960}
4961
4962/// Filter bank 0 register 1
4963pub mod FR116 {
4964    pub use super::FR10::FB0;
4965    pub use super::FR10::FB1;
4966    pub use super::FR10::FB10;
4967    pub use super::FR10::FB11;
4968    pub use super::FR10::FB12;
4969    pub use super::FR10::FB13;
4970    pub use super::FR10::FB14;
4971    pub use super::FR10::FB15;
4972    pub use super::FR10::FB16;
4973    pub use super::FR10::FB17;
4974    pub use super::FR10::FB18;
4975    pub use super::FR10::FB19;
4976    pub use super::FR10::FB2;
4977    pub use super::FR10::FB20;
4978    pub use super::FR10::FB21;
4979    pub use super::FR10::FB22;
4980    pub use super::FR10::FB23;
4981    pub use super::FR10::FB24;
4982    pub use super::FR10::FB25;
4983    pub use super::FR10::FB26;
4984    pub use super::FR10::FB27;
4985    pub use super::FR10::FB28;
4986    pub use super::FR10::FB29;
4987    pub use super::FR10::FB3;
4988    pub use super::FR10::FB30;
4989    pub use super::FR10::FB31;
4990    pub use super::FR10::FB4;
4991    pub use super::FR10::FB5;
4992    pub use super::FR10::FB6;
4993    pub use super::FR10::FB7;
4994    pub use super::FR10::FB8;
4995    pub use super::FR10::FB9;
4996}
4997
4998/// Filter bank 0 register 2
4999pub mod FR216 {
5000    pub use super::FR10::FB0;
5001    pub use super::FR10::FB1;
5002    pub use super::FR10::FB10;
5003    pub use super::FR10::FB11;
5004    pub use super::FR10::FB12;
5005    pub use super::FR10::FB13;
5006    pub use super::FR10::FB14;
5007    pub use super::FR10::FB15;
5008    pub use super::FR10::FB16;
5009    pub use super::FR10::FB17;
5010    pub use super::FR10::FB18;
5011    pub use super::FR10::FB19;
5012    pub use super::FR10::FB2;
5013    pub use super::FR10::FB20;
5014    pub use super::FR10::FB21;
5015    pub use super::FR10::FB22;
5016    pub use super::FR10::FB23;
5017    pub use super::FR10::FB24;
5018    pub use super::FR10::FB25;
5019    pub use super::FR10::FB26;
5020    pub use super::FR10::FB27;
5021    pub use super::FR10::FB28;
5022    pub use super::FR10::FB29;
5023    pub use super::FR10::FB3;
5024    pub use super::FR10::FB30;
5025    pub use super::FR10::FB31;
5026    pub use super::FR10::FB4;
5027    pub use super::FR10::FB5;
5028    pub use super::FR10::FB6;
5029    pub use super::FR10::FB7;
5030    pub use super::FR10::FB8;
5031    pub use super::FR10::FB9;
5032}
5033
5034/// Filter bank 0 register 1
5035pub mod FR117 {
5036    pub use super::FR10::FB0;
5037    pub use super::FR10::FB1;
5038    pub use super::FR10::FB10;
5039    pub use super::FR10::FB11;
5040    pub use super::FR10::FB12;
5041    pub use super::FR10::FB13;
5042    pub use super::FR10::FB14;
5043    pub use super::FR10::FB15;
5044    pub use super::FR10::FB16;
5045    pub use super::FR10::FB17;
5046    pub use super::FR10::FB18;
5047    pub use super::FR10::FB19;
5048    pub use super::FR10::FB2;
5049    pub use super::FR10::FB20;
5050    pub use super::FR10::FB21;
5051    pub use super::FR10::FB22;
5052    pub use super::FR10::FB23;
5053    pub use super::FR10::FB24;
5054    pub use super::FR10::FB25;
5055    pub use super::FR10::FB26;
5056    pub use super::FR10::FB27;
5057    pub use super::FR10::FB28;
5058    pub use super::FR10::FB29;
5059    pub use super::FR10::FB3;
5060    pub use super::FR10::FB30;
5061    pub use super::FR10::FB31;
5062    pub use super::FR10::FB4;
5063    pub use super::FR10::FB5;
5064    pub use super::FR10::FB6;
5065    pub use super::FR10::FB7;
5066    pub use super::FR10::FB8;
5067    pub use super::FR10::FB9;
5068}
5069
5070/// Filter bank 0 register 2
5071pub mod FR217 {
5072    pub use super::FR10::FB0;
5073    pub use super::FR10::FB1;
5074    pub use super::FR10::FB10;
5075    pub use super::FR10::FB11;
5076    pub use super::FR10::FB12;
5077    pub use super::FR10::FB13;
5078    pub use super::FR10::FB14;
5079    pub use super::FR10::FB15;
5080    pub use super::FR10::FB16;
5081    pub use super::FR10::FB17;
5082    pub use super::FR10::FB18;
5083    pub use super::FR10::FB19;
5084    pub use super::FR10::FB2;
5085    pub use super::FR10::FB20;
5086    pub use super::FR10::FB21;
5087    pub use super::FR10::FB22;
5088    pub use super::FR10::FB23;
5089    pub use super::FR10::FB24;
5090    pub use super::FR10::FB25;
5091    pub use super::FR10::FB26;
5092    pub use super::FR10::FB27;
5093    pub use super::FR10::FB28;
5094    pub use super::FR10::FB29;
5095    pub use super::FR10::FB3;
5096    pub use super::FR10::FB30;
5097    pub use super::FR10::FB31;
5098    pub use super::FR10::FB4;
5099    pub use super::FR10::FB5;
5100    pub use super::FR10::FB6;
5101    pub use super::FR10::FB7;
5102    pub use super::FR10::FB8;
5103    pub use super::FR10::FB9;
5104}
5105
5106/// Filter bank 0 register 1
5107pub mod FR118 {
5108    pub use super::FR10::FB0;
5109    pub use super::FR10::FB1;
5110    pub use super::FR10::FB10;
5111    pub use super::FR10::FB11;
5112    pub use super::FR10::FB12;
5113    pub use super::FR10::FB13;
5114    pub use super::FR10::FB14;
5115    pub use super::FR10::FB15;
5116    pub use super::FR10::FB16;
5117    pub use super::FR10::FB17;
5118    pub use super::FR10::FB18;
5119    pub use super::FR10::FB19;
5120    pub use super::FR10::FB2;
5121    pub use super::FR10::FB20;
5122    pub use super::FR10::FB21;
5123    pub use super::FR10::FB22;
5124    pub use super::FR10::FB23;
5125    pub use super::FR10::FB24;
5126    pub use super::FR10::FB25;
5127    pub use super::FR10::FB26;
5128    pub use super::FR10::FB27;
5129    pub use super::FR10::FB28;
5130    pub use super::FR10::FB29;
5131    pub use super::FR10::FB3;
5132    pub use super::FR10::FB30;
5133    pub use super::FR10::FB31;
5134    pub use super::FR10::FB4;
5135    pub use super::FR10::FB5;
5136    pub use super::FR10::FB6;
5137    pub use super::FR10::FB7;
5138    pub use super::FR10::FB8;
5139    pub use super::FR10::FB9;
5140}
5141
5142/// Filter bank 0 register 2
5143pub mod FR218 {
5144    pub use super::FR10::FB0;
5145    pub use super::FR10::FB1;
5146    pub use super::FR10::FB10;
5147    pub use super::FR10::FB11;
5148    pub use super::FR10::FB12;
5149    pub use super::FR10::FB13;
5150    pub use super::FR10::FB14;
5151    pub use super::FR10::FB15;
5152    pub use super::FR10::FB16;
5153    pub use super::FR10::FB17;
5154    pub use super::FR10::FB18;
5155    pub use super::FR10::FB19;
5156    pub use super::FR10::FB2;
5157    pub use super::FR10::FB20;
5158    pub use super::FR10::FB21;
5159    pub use super::FR10::FB22;
5160    pub use super::FR10::FB23;
5161    pub use super::FR10::FB24;
5162    pub use super::FR10::FB25;
5163    pub use super::FR10::FB26;
5164    pub use super::FR10::FB27;
5165    pub use super::FR10::FB28;
5166    pub use super::FR10::FB29;
5167    pub use super::FR10::FB3;
5168    pub use super::FR10::FB30;
5169    pub use super::FR10::FB31;
5170    pub use super::FR10::FB4;
5171    pub use super::FR10::FB5;
5172    pub use super::FR10::FB6;
5173    pub use super::FR10::FB7;
5174    pub use super::FR10::FB8;
5175    pub use super::FR10::FB9;
5176}
5177
5178/// Filter bank 0 register 1
5179pub mod FR119 {
5180    pub use super::FR10::FB0;
5181    pub use super::FR10::FB1;
5182    pub use super::FR10::FB10;
5183    pub use super::FR10::FB11;
5184    pub use super::FR10::FB12;
5185    pub use super::FR10::FB13;
5186    pub use super::FR10::FB14;
5187    pub use super::FR10::FB15;
5188    pub use super::FR10::FB16;
5189    pub use super::FR10::FB17;
5190    pub use super::FR10::FB18;
5191    pub use super::FR10::FB19;
5192    pub use super::FR10::FB2;
5193    pub use super::FR10::FB20;
5194    pub use super::FR10::FB21;
5195    pub use super::FR10::FB22;
5196    pub use super::FR10::FB23;
5197    pub use super::FR10::FB24;
5198    pub use super::FR10::FB25;
5199    pub use super::FR10::FB26;
5200    pub use super::FR10::FB27;
5201    pub use super::FR10::FB28;
5202    pub use super::FR10::FB29;
5203    pub use super::FR10::FB3;
5204    pub use super::FR10::FB30;
5205    pub use super::FR10::FB31;
5206    pub use super::FR10::FB4;
5207    pub use super::FR10::FB5;
5208    pub use super::FR10::FB6;
5209    pub use super::FR10::FB7;
5210    pub use super::FR10::FB8;
5211    pub use super::FR10::FB9;
5212}
5213
5214/// Filter bank 0 register 2
5215pub mod FR219 {
5216    pub use super::FR10::FB0;
5217    pub use super::FR10::FB1;
5218    pub use super::FR10::FB10;
5219    pub use super::FR10::FB11;
5220    pub use super::FR10::FB12;
5221    pub use super::FR10::FB13;
5222    pub use super::FR10::FB14;
5223    pub use super::FR10::FB15;
5224    pub use super::FR10::FB16;
5225    pub use super::FR10::FB17;
5226    pub use super::FR10::FB18;
5227    pub use super::FR10::FB19;
5228    pub use super::FR10::FB2;
5229    pub use super::FR10::FB20;
5230    pub use super::FR10::FB21;
5231    pub use super::FR10::FB22;
5232    pub use super::FR10::FB23;
5233    pub use super::FR10::FB24;
5234    pub use super::FR10::FB25;
5235    pub use super::FR10::FB26;
5236    pub use super::FR10::FB27;
5237    pub use super::FR10::FB28;
5238    pub use super::FR10::FB29;
5239    pub use super::FR10::FB3;
5240    pub use super::FR10::FB30;
5241    pub use super::FR10::FB31;
5242    pub use super::FR10::FB4;
5243    pub use super::FR10::FB5;
5244    pub use super::FR10::FB6;
5245    pub use super::FR10::FB7;
5246    pub use super::FR10::FB8;
5247    pub use super::FR10::FB9;
5248}
5249
5250/// Filter bank 0 register 1
5251pub mod FR120 {
5252    pub use super::FR10::FB0;
5253    pub use super::FR10::FB1;
5254    pub use super::FR10::FB10;
5255    pub use super::FR10::FB11;
5256    pub use super::FR10::FB12;
5257    pub use super::FR10::FB13;
5258    pub use super::FR10::FB14;
5259    pub use super::FR10::FB15;
5260    pub use super::FR10::FB16;
5261    pub use super::FR10::FB17;
5262    pub use super::FR10::FB18;
5263    pub use super::FR10::FB19;
5264    pub use super::FR10::FB2;
5265    pub use super::FR10::FB20;
5266    pub use super::FR10::FB21;
5267    pub use super::FR10::FB22;
5268    pub use super::FR10::FB23;
5269    pub use super::FR10::FB24;
5270    pub use super::FR10::FB25;
5271    pub use super::FR10::FB26;
5272    pub use super::FR10::FB27;
5273    pub use super::FR10::FB28;
5274    pub use super::FR10::FB29;
5275    pub use super::FR10::FB3;
5276    pub use super::FR10::FB30;
5277    pub use super::FR10::FB31;
5278    pub use super::FR10::FB4;
5279    pub use super::FR10::FB5;
5280    pub use super::FR10::FB6;
5281    pub use super::FR10::FB7;
5282    pub use super::FR10::FB8;
5283    pub use super::FR10::FB9;
5284}
5285
5286/// Filter bank 0 register 2
5287pub mod FR220 {
5288    pub use super::FR10::FB0;
5289    pub use super::FR10::FB1;
5290    pub use super::FR10::FB10;
5291    pub use super::FR10::FB11;
5292    pub use super::FR10::FB12;
5293    pub use super::FR10::FB13;
5294    pub use super::FR10::FB14;
5295    pub use super::FR10::FB15;
5296    pub use super::FR10::FB16;
5297    pub use super::FR10::FB17;
5298    pub use super::FR10::FB18;
5299    pub use super::FR10::FB19;
5300    pub use super::FR10::FB2;
5301    pub use super::FR10::FB20;
5302    pub use super::FR10::FB21;
5303    pub use super::FR10::FB22;
5304    pub use super::FR10::FB23;
5305    pub use super::FR10::FB24;
5306    pub use super::FR10::FB25;
5307    pub use super::FR10::FB26;
5308    pub use super::FR10::FB27;
5309    pub use super::FR10::FB28;
5310    pub use super::FR10::FB29;
5311    pub use super::FR10::FB3;
5312    pub use super::FR10::FB30;
5313    pub use super::FR10::FB31;
5314    pub use super::FR10::FB4;
5315    pub use super::FR10::FB5;
5316    pub use super::FR10::FB6;
5317    pub use super::FR10::FB7;
5318    pub use super::FR10::FB8;
5319    pub use super::FR10::FB9;
5320}
5321
5322/// Filter bank 0 register 1
5323pub mod FR121 {
5324    pub use super::FR10::FB0;
5325    pub use super::FR10::FB1;
5326    pub use super::FR10::FB10;
5327    pub use super::FR10::FB11;
5328    pub use super::FR10::FB12;
5329    pub use super::FR10::FB13;
5330    pub use super::FR10::FB14;
5331    pub use super::FR10::FB15;
5332    pub use super::FR10::FB16;
5333    pub use super::FR10::FB17;
5334    pub use super::FR10::FB18;
5335    pub use super::FR10::FB19;
5336    pub use super::FR10::FB2;
5337    pub use super::FR10::FB20;
5338    pub use super::FR10::FB21;
5339    pub use super::FR10::FB22;
5340    pub use super::FR10::FB23;
5341    pub use super::FR10::FB24;
5342    pub use super::FR10::FB25;
5343    pub use super::FR10::FB26;
5344    pub use super::FR10::FB27;
5345    pub use super::FR10::FB28;
5346    pub use super::FR10::FB29;
5347    pub use super::FR10::FB3;
5348    pub use super::FR10::FB30;
5349    pub use super::FR10::FB31;
5350    pub use super::FR10::FB4;
5351    pub use super::FR10::FB5;
5352    pub use super::FR10::FB6;
5353    pub use super::FR10::FB7;
5354    pub use super::FR10::FB8;
5355    pub use super::FR10::FB9;
5356}
5357
5358/// Filter bank 0 register 2
5359pub mod FR221 {
5360    pub use super::FR10::FB0;
5361    pub use super::FR10::FB1;
5362    pub use super::FR10::FB10;
5363    pub use super::FR10::FB11;
5364    pub use super::FR10::FB12;
5365    pub use super::FR10::FB13;
5366    pub use super::FR10::FB14;
5367    pub use super::FR10::FB15;
5368    pub use super::FR10::FB16;
5369    pub use super::FR10::FB17;
5370    pub use super::FR10::FB18;
5371    pub use super::FR10::FB19;
5372    pub use super::FR10::FB2;
5373    pub use super::FR10::FB20;
5374    pub use super::FR10::FB21;
5375    pub use super::FR10::FB22;
5376    pub use super::FR10::FB23;
5377    pub use super::FR10::FB24;
5378    pub use super::FR10::FB25;
5379    pub use super::FR10::FB26;
5380    pub use super::FR10::FB27;
5381    pub use super::FR10::FB28;
5382    pub use super::FR10::FB29;
5383    pub use super::FR10::FB3;
5384    pub use super::FR10::FB30;
5385    pub use super::FR10::FB31;
5386    pub use super::FR10::FB4;
5387    pub use super::FR10::FB5;
5388    pub use super::FR10::FB6;
5389    pub use super::FR10::FB7;
5390    pub use super::FR10::FB8;
5391    pub use super::FR10::FB9;
5392}
5393
5394/// Filter bank 0 register 1
5395pub mod FR122 {
5396    pub use super::FR10::FB0;
5397    pub use super::FR10::FB1;
5398    pub use super::FR10::FB10;
5399    pub use super::FR10::FB11;
5400    pub use super::FR10::FB12;
5401    pub use super::FR10::FB13;
5402    pub use super::FR10::FB14;
5403    pub use super::FR10::FB15;
5404    pub use super::FR10::FB16;
5405    pub use super::FR10::FB17;
5406    pub use super::FR10::FB18;
5407    pub use super::FR10::FB19;
5408    pub use super::FR10::FB2;
5409    pub use super::FR10::FB20;
5410    pub use super::FR10::FB21;
5411    pub use super::FR10::FB22;
5412    pub use super::FR10::FB23;
5413    pub use super::FR10::FB24;
5414    pub use super::FR10::FB25;
5415    pub use super::FR10::FB26;
5416    pub use super::FR10::FB27;
5417    pub use super::FR10::FB28;
5418    pub use super::FR10::FB29;
5419    pub use super::FR10::FB3;
5420    pub use super::FR10::FB30;
5421    pub use super::FR10::FB31;
5422    pub use super::FR10::FB4;
5423    pub use super::FR10::FB5;
5424    pub use super::FR10::FB6;
5425    pub use super::FR10::FB7;
5426    pub use super::FR10::FB8;
5427    pub use super::FR10::FB9;
5428}
5429
5430/// Filter bank 0 register 2
5431pub mod FR222 {
5432    pub use super::FR10::FB0;
5433    pub use super::FR10::FB1;
5434    pub use super::FR10::FB10;
5435    pub use super::FR10::FB11;
5436    pub use super::FR10::FB12;
5437    pub use super::FR10::FB13;
5438    pub use super::FR10::FB14;
5439    pub use super::FR10::FB15;
5440    pub use super::FR10::FB16;
5441    pub use super::FR10::FB17;
5442    pub use super::FR10::FB18;
5443    pub use super::FR10::FB19;
5444    pub use super::FR10::FB2;
5445    pub use super::FR10::FB20;
5446    pub use super::FR10::FB21;
5447    pub use super::FR10::FB22;
5448    pub use super::FR10::FB23;
5449    pub use super::FR10::FB24;
5450    pub use super::FR10::FB25;
5451    pub use super::FR10::FB26;
5452    pub use super::FR10::FB27;
5453    pub use super::FR10::FB28;
5454    pub use super::FR10::FB29;
5455    pub use super::FR10::FB3;
5456    pub use super::FR10::FB30;
5457    pub use super::FR10::FB31;
5458    pub use super::FR10::FB4;
5459    pub use super::FR10::FB5;
5460    pub use super::FR10::FB6;
5461    pub use super::FR10::FB7;
5462    pub use super::FR10::FB8;
5463    pub use super::FR10::FB9;
5464}
5465
5466/// Filter bank 0 register 1
5467pub mod FR123 {
5468    pub use super::FR10::FB0;
5469    pub use super::FR10::FB1;
5470    pub use super::FR10::FB10;
5471    pub use super::FR10::FB11;
5472    pub use super::FR10::FB12;
5473    pub use super::FR10::FB13;
5474    pub use super::FR10::FB14;
5475    pub use super::FR10::FB15;
5476    pub use super::FR10::FB16;
5477    pub use super::FR10::FB17;
5478    pub use super::FR10::FB18;
5479    pub use super::FR10::FB19;
5480    pub use super::FR10::FB2;
5481    pub use super::FR10::FB20;
5482    pub use super::FR10::FB21;
5483    pub use super::FR10::FB22;
5484    pub use super::FR10::FB23;
5485    pub use super::FR10::FB24;
5486    pub use super::FR10::FB25;
5487    pub use super::FR10::FB26;
5488    pub use super::FR10::FB27;
5489    pub use super::FR10::FB28;
5490    pub use super::FR10::FB29;
5491    pub use super::FR10::FB3;
5492    pub use super::FR10::FB30;
5493    pub use super::FR10::FB31;
5494    pub use super::FR10::FB4;
5495    pub use super::FR10::FB5;
5496    pub use super::FR10::FB6;
5497    pub use super::FR10::FB7;
5498    pub use super::FR10::FB8;
5499    pub use super::FR10::FB9;
5500}
5501
5502/// Filter bank 0 register 2
5503pub mod FR223 {
5504    pub use super::FR10::FB0;
5505    pub use super::FR10::FB1;
5506    pub use super::FR10::FB10;
5507    pub use super::FR10::FB11;
5508    pub use super::FR10::FB12;
5509    pub use super::FR10::FB13;
5510    pub use super::FR10::FB14;
5511    pub use super::FR10::FB15;
5512    pub use super::FR10::FB16;
5513    pub use super::FR10::FB17;
5514    pub use super::FR10::FB18;
5515    pub use super::FR10::FB19;
5516    pub use super::FR10::FB2;
5517    pub use super::FR10::FB20;
5518    pub use super::FR10::FB21;
5519    pub use super::FR10::FB22;
5520    pub use super::FR10::FB23;
5521    pub use super::FR10::FB24;
5522    pub use super::FR10::FB25;
5523    pub use super::FR10::FB26;
5524    pub use super::FR10::FB27;
5525    pub use super::FR10::FB28;
5526    pub use super::FR10::FB29;
5527    pub use super::FR10::FB3;
5528    pub use super::FR10::FB30;
5529    pub use super::FR10::FB31;
5530    pub use super::FR10::FB4;
5531    pub use super::FR10::FB5;
5532    pub use super::FR10::FB6;
5533    pub use super::FR10::FB7;
5534    pub use super::FR10::FB8;
5535    pub use super::FR10::FB9;
5536}
5537
5538/// Filter bank 0 register 1
5539pub mod FR124 {
5540    pub use super::FR10::FB0;
5541    pub use super::FR10::FB1;
5542    pub use super::FR10::FB10;
5543    pub use super::FR10::FB11;
5544    pub use super::FR10::FB12;
5545    pub use super::FR10::FB13;
5546    pub use super::FR10::FB14;
5547    pub use super::FR10::FB15;
5548    pub use super::FR10::FB16;
5549    pub use super::FR10::FB17;
5550    pub use super::FR10::FB18;
5551    pub use super::FR10::FB19;
5552    pub use super::FR10::FB2;
5553    pub use super::FR10::FB20;
5554    pub use super::FR10::FB21;
5555    pub use super::FR10::FB22;
5556    pub use super::FR10::FB23;
5557    pub use super::FR10::FB24;
5558    pub use super::FR10::FB25;
5559    pub use super::FR10::FB26;
5560    pub use super::FR10::FB27;
5561    pub use super::FR10::FB28;
5562    pub use super::FR10::FB29;
5563    pub use super::FR10::FB3;
5564    pub use super::FR10::FB30;
5565    pub use super::FR10::FB31;
5566    pub use super::FR10::FB4;
5567    pub use super::FR10::FB5;
5568    pub use super::FR10::FB6;
5569    pub use super::FR10::FB7;
5570    pub use super::FR10::FB8;
5571    pub use super::FR10::FB9;
5572}
5573
5574/// Filter bank 0 register 2
5575pub mod FR224 {
5576    pub use super::FR10::FB0;
5577    pub use super::FR10::FB1;
5578    pub use super::FR10::FB10;
5579    pub use super::FR10::FB11;
5580    pub use super::FR10::FB12;
5581    pub use super::FR10::FB13;
5582    pub use super::FR10::FB14;
5583    pub use super::FR10::FB15;
5584    pub use super::FR10::FB16;
5585    pub use super::FR10::FB17;
5586    pub use super::FR10::FB18;
5587    pub use super::FR10::FB19;
5588    pub use super::FR10::FB2;
5589    pub use super::FR10::FB20;
5590    pub use super::FR10::FB21;
5591    pub use super::FR10::FB22;
5592    pub use super::FR10::FB23;
5593    pub use super::FR10::FB24;
5594    pub use super::FR10::FB25;
5595    pub use super::FR10::FB26;
5596    pub use super::FR10::FB27;
5597    pub use super::FR10::FB28;
5598    pub use super::FR10::FB29;
5599    pub use super::FR10::FB3;
5600    pub use super::FR10::FB30;
5601    pub use super::FR10::FB31;
5602    pub use super::FR10::FB4;
5603    pub use super::FR10::FB5;
5604    pub use super::FR10::FB6;
5605    pub use super::FR10::FB7;
5606    pub use super::FR10::FB8;
5607    pub use super::FR10::FB9;
5608}
5609
5610/// Filter bank 0 register 1
5611pub mod FR125 {
5612    pub use super::FR10::FB0;
5613    pub use super::FR10::FB1;
5614    pub use super::FR10::FB10;
5615    pub use super::FR10::FB11;
5616    pub use super::FR10::FB12;
5617    pub use super::FR10::FB13;
5618    pub use super::FR10::FB14;
5619    pub use super::FR10::FB15;
5620    pub use super::FR10::FB16;
5621    pub use super::FR10::FB17;
5622    pub use super::FR10::FB18;
5623    pub use super::FR10::FB19;
5624    pub use super::FR10::FB2;
5625    pub use super::FR10::FB20;
5626    pub use super::FR10::FB21;
5627    pub use super::FR10::FB22;
5628    pub use super::FR10::FB23;
5629    pub use super::FR10::FB24;
5630    pub use super::FR10::FB25;
5631    pub use super::FR10::FB26;
5632    pub use super::FR10::FB27;
5633    pub use super::FR10::FB28;
5634    pub use super::FR10::FB29;
5635    pub use super::FR10::FB3;
5636    pub use super::FR10::FB30;
5637    pub use super::FR10::FB31;
5638    pub use super::FR10::FB4;
5639    pub use super::FR10::FB5;
5640    pub use super::FR10::FB6;
5641    pub use super::FR10::FB7;
5642    pub use super::FR10::FB8;
5643    pub use super::FR10::FB9;
5644}
5645
5646/// Filter bank 0 register 2
5647pub mod FR225 {
5648    pub use super::FR10::FB0;
5649    pub use super::FR10::FB1;
5650    pub use super::FR10::FB10;
5651    pub use super::FR10::FB11;
5652    pub use super::FR10::FB12;
5653    pub use super::FR10::FB13;
5654    pub use super::FR10::FB14;
5655    pub use super::FR10::FB15;
5656    pub use super::FR10::FB16;
5657    pub use super::FR10::FB17;
5658    pub use super::FR10::FB18;
5659    pub use super::FR10::FB19;
5660    pub use super::FR10::FB2;
5661    pub use super::FR10::FB20;
5662    pub use super::FR10::FB21;
5663    pub use super::FR10::FB22;
5664    pub use super::FR10::FB23;
5665    pub use super::FR10::FB24;
5666    pub use super::FR10::FB25;
5667    pub use super::FR10::FB26;
5668    pub use super::FR10::FB27;
5669    pub use super::FR10::FB28;
5670    pub use super::FR10::FB29;
5671    pub use super::FR10::FB3;
5672    pub use super::FR10::FB30;
5673    pub use super::FR10::FB31;
5674    pub use super::FR10::FB4;
5675    pub use super::FR10::FB5;
5676    pub use super::FR10::FB6;
5677    pub use super::FR10::FB7;
5678    pub use super::FR10::FB8;
5679    pub use super::FR10::FB9;
5680}
5681
5682/// Filter bank 0 register 1
5683pub mod FR126 {
5684    pub use super::FR10::FB0;
5685    pub use super::FR10::FB1;
5686    pub use super::FR10::FB10;
5687    pub use super::FR10::FB11;
5688    pub use super::FR10::FB12;
5689    pub use super::FR10::FB13;
5690    pub use super::FR10::FB14;
5691    pub use super::FR10::FB15;
5692    pub use super::FR10::FB16;
5693    pub use super::FR10::FB17;
5694    pub use super::FR10::FB18;
5695    pub use super::FR10::FB19;
5696    pub use super::FR10::FB2;
5697    pub use super::FR10::FB20;
5698    pub use super::FR10::FB21;
5699    pub use super::FR10::FB22;
5700    pub use super::FR10::FB23;
5701    pub use super::FR10::FB24;
5702    pub use super::FR10::FB25;
5703    pub use super::FR10::FB26;
5704    pub use super::FR10::FB27;
5705    pub use super::FR10::FB28;
5706    pub use super::FR10::FB29;
5707    pub use super::FR10::FB3;
5708    pub use super::FR10::FB30;
5709    pub use super::FR10::FB31;
5710    pub use super::FR10::FB4;
5711    pub use super::FR10::FB5;
5712    pub use super::FR10::FB6;
5713    pub use super::FR10::FB7;
5714    pub use super::FR10::FB8;
5715    pub use super::FR10::FB9;
5716}
5717
5718/// Filter bank 0 register 2
5719pub mod FR226 {
5720    pub use super::FR10::FB0;
5721    pub use super::FR10::FB1;
5722    pub use super::FR10::FB10;
5723    pub use super::FR10::FB11;
5724    pub use super::FR10::FB12;
5725    pub use super::FR10::FB13;
5726    pub use super::FR10::FB14;
5727    pub use super::FR10::FB15;
5728    pub use super::FR10::FB16;
5729    pub use super::FR10::FB17;
5730    pub use super::FR10::FB18;
5731    pub use super::FR10::FB19;
5732    pub use super::FR10::FB2;
5733    pub use super::FR10::FB20;
5734    pub use super::FR10::FB21;
5735    pub use super::FR10::FB22;
5736    pub use super::FR10::FB23;
5737    pub use super::FR10::FB24;
5738    pub use super::FR10::FB25;
5739    pub use super::FR10::FB26;
5740    pub use super::FR10::FB27;
5741    pub use super::FR10::FB28;
5742    pub use super::FR10::FB29;
5743    pub use super::FR10::FB3;
5744    pub use super::FR10::FB30;
5745    pub use super::FR10::FB31;
5746    pub use super::FR10::FB4;
5747    pub use super::FR10::FB5;
5748    pub use super::FR10::FB6;
5749    pub use super::FR10::FB7;
5750    pub use super::FR10::FB8;
5751    pub use super::FR10::FB9;
5752}
5753
5754/// Filter bank 0 register 1
5755pub mod FR127 {
5756    pub use super::FR10::FB0;
5757    pub use super::FR10::FB1;
5758    pub use super::FR10::FB10;
5759    pub use super::FR10::FB11;
5760    pub use super::FR10::FB12;
5761    pub use super::FR10::FB13;
5762    pub use super::FR10::FB14;
5763    pub use super::FR10::FB15;
5764    pub use super::FR10::FB16;
5765    pub use super::FR10::FB17;
5766    pub use super::FR10::FB18;
5767    pub use super::FR10::FB19;
5768    pub use super::FR10::FB2;
5769    pub use super::FR10::FB20;
5770    pub use super::FR10::FB21;
5771    pub use super::FR10::FB22;
5772    pub use super::FR10::FB23;
5773    pub use super::FR10::FB24;
5774    pub use super::FR10::FB25;
5775    pub use super::FR10::FB26;
5776    pub use super::FR10::FB27;
5777    pub use super::FR10::FB28;
5778    pub use super::FR10::FB29;
5779    pub use super::FR10::FB3;
5780    pub use super::FR10::FB30;
5781    pub use super::FR10::FB31;
5782    pub use super::FR10::FB4;
5783    pub use super::FR10::FB5;
5784    pub use super::FR10::FB6;
5785    pub use super::FR10::FB7;
5786    pub use super::FR10::FB8;
5787    pub use super::FR10::FB9;
5788}
5789
5790/// Filter bank 0 register 2
5791pub mod FR227 {
5792    pub use super::FR10::FB0;
5793    pub use super::FR10::FB1;
5794    pub use super::FR10::FB10;
5795    pub use super::FR10::FB11;
5796    pub use super::FR10::FB12;
5797    pub use super::FR10::FB13;
5798    pub use super::FR10::FB14;
5799    pub use super::FR10::FB15;
5800    pub use super::FR10::FB16;
5801    pub use super::FR10::FB17;
5802    pub use super::FR10::FB18;
5803    pub use super::FR10::FB19;
5804    pub use super::FR10::FB2;
5805    pub use super::FR10::FB20;
5806    pub use super::FR10::FB21;
5807    pub use super::FR10::FB22;
5808    pub use super::FR10::FB23;
5809    pub use super::FR10::FB24;
5810    pub use super::FR10::FB25;
5811    pub use super::FR10::FB26;
5812    pub use super::FR10::FB27;
5813    pub use super::FR10::FB28;
5814    pub use super::FR10::FB29;
5815    pub use super::FR10::FB3;
5816    pub use super::FR10::FB30;
5817    pub use super::FR10::FB31;
5818    pub use super::FR10::FB4;
5819    pub use super::FR10::FB5;
5820    pub use super::FR10::FB6;
5821    pub use super::FR10::FB7;
5822    pub use super::FR10::FB8;
5823    pub use super::FR10::FB9;
5824}
5825#[repr(C)]
5826pub struct RegisterBlock {
5827    /// master control register
5828    pub MCR: RWRegister<u32>,
5829
5830    /// master status register
5831    pub MSR: RWRegister<u32>,
5832
5833    /// transmit status register
5834    pub TSR: RWRegister<u32>,
5835
5836    /// receive FIFO %s register
5837    pub RF0R: RWRegister<u32>,
5838
5839    /// receive FIFO %s register
5840    pub RF1R: RWRegister<u32>,
5841
5842    /// interrupt enable register
5843    pub IER: RWRegister<u32>,
5844
5845    /// interrupt enable register
5846    pub ESR: RWRegister<u32>,
5847
5848    /// bit timing register
5849    pub BTR: RWRegister<u32>,
5850
5851    _reserved1: [u8; 352],
5852
5853    /// TX mailbox identifier register
5854    pub TIR0: RWRegister<u32>,
5855
5856    /// mailbox data length control and time stamp register
5857    pub TDTR0: RWRegister<u32>,
5858
5859    /// mailbox data low register
5860    pub TDLR0: RWRegister<u32>,
5861
5862    /// mailbox data high register
5863    pub TDHR0: RWRegister<u32>,
5864
5865    /// TX mailbox identifier register
5866    pub TIR1: RWRegister<u32>,
5867
5868    /// mailbox data length control and time stamp register
5869    pub TDTR1: RWRegister<u32>,
5870
5871    /// mailbox data low register
5872    pub TDLR1: RWRegister<u32>,
5873
5874    /// mailbox data high register
5875    pub TDHR1: RWRegister<u32>,
5876
5877    /// TX mailbox identifier register
5878    pub TIR2: RWRegister<u32>,
5879
5880    /// mailbox data length control and time stamp register
5881    pub TDTR2: RWRegister<u32>,
5882
5883    /// mailbox data low register
5884    pub TDLR2: RWRegister<u32>,
5885
5886    /// mailbox data high register
5887    pub TDHR2: RWRegister<u32>,
5888
5889    /// receive FIFO mailbox identifier register
5890    pub RIR0: RORegister<u32>,
5891
5892    /// mailbox data high register
5893    pub RDTR0: RORegister<u32>,
5894
5895    /// mailbox data high register
5896    pub RDLR0: RORegister<u32>,
5897
5898    /// receive FIFO mailbox data high register
5899    pub RDHR0: RORegister<u32>,
5900
5901    /// receive FIFO mailbox identifier register
5902    pub RIR1: RORegister<u32>,
5903
5904    /// mailbox data high register
5905    pub RDTR1: RORegister<u32>,
5906
5907    /// mailbox data high register
5908    pub RDLR1: RORegister<u32>,
5909
5910    /// receive FIFO mailbox data high register
5911    pub RDHR1: RORegister<u32>,
5912
5913    _reserved2: [u8; 48],
5914
5915    /// filter master register
5916    pub FMR: RWRegister<u32>,
5917
5918    /// filter mode register
5919    pub FM1R: RWRegister<u32>,
5920
5921    _reserved3: [u8; 4],
5922
5923    /// filter scale register
5924    pub FS1R: RWRegister<u32>,
5925
5926    _reserved4: [u8; 4],
5927
5928    /// filter FIFO assignment register
5929    pub FFA1R: RWRegister<u32>,
5930
5931    _reserved5: [u8; 4],
5932
5933    /// filter activation register
5934    pub FA1R: RWRegister<u32>,
5935
5936    _reserved6: [u8; 32],
5937
5938    /// Filter bank 0 register 1
5939    pub FR10: RWRegister<u32>,
5940
5941    /// Filter bank 0 register 2
5942    pub FR20: RWRegister<u32>,
5943
5944    /// Filter bank 0 register 1
5945    pub FR11: RWRegister<u32>,
5946
5947    /// Filter bank 0 register 2
5948    pub FR21: RWRegister<u32>,
5949
5950    /// Filter bank 0 register 1
5951    pub FR12: RWRegister<u32>,
5952
5953    /// Filter bank 0 register 2
5954    pub FR22: RWRegister<u32>,
5955
5956    /// Filter bank 0 register 1
5957    pub FR13: RWRegister<u32>,
5958
5959    /// Filter bank 0 register 2
5960    pub FR23: RWRegister<u32>,
5961
5962    /// Filter bank 0 register 1
5963    pub FR14: RWRegister<u32>,
5964
5965    /// Filter bank 0 register 2
5966    pub FR24: RWRegister<u32>,
5967
5968    /// Filter bank 0 register 1
5969    pub FR15: RWRegister<u32>,
5970
5971    /// Filter bank 0 register 2
5972    pub FR25: RWRegister<u32>,
5973
5974    /// Filter bank 0 register 1
5975    pub FR16: RWRegister<u32>,
5976
5977    /// Filter bank 0 register 2
5978    pub FR26: RWRegister<u32>,
5979
5980    /// Filter bank 0 register 1
5981    pub FR17: RWRegister<u32>,
5982
5983    /// Filter bank 0 register 2
5984    pub FR27: RWRegister<u32>,
5985
5986    /// Filter bank 0 register 1
5987    pub FR18: RWRegister<u32>,
5988
5989    /// Filter bank 0 register 2
5990    pub FR28: RWRegister<u32>,
5991
5992    /// Filter bank 0 register 1
5993    pub FR19: RWRegister<u32>,
5994
5995    /// Filter bank 0 register 2
5996    pub FR29: RWRegister<u32>,
5997
5998    /// Filter bank 0 register 1
5999    pub FR110: RWRegister<u32>,
6000
6001    /// Filter bank 0 register 2
6002    pub FR210: RWRegister<u32>,
6003
6004    /// Filter bank 0 register 1
6005    pub FR111: RWRegister<u32>,
6006
6007    /// Filter bank 0 register 2
6008    pub FR211: RWRegister<u32>,
6009
6010    /// Filter bank 0 register 1
6011    pub FR112: RWRegister<u32>,
6012
6013    /// Filter bank 0 register 2
6014    pub FR212: RWRegister<u32>,
6015
6016    /// Filter bank 0 register 1
6017    pub FR113: RWRegister<u32>,
6018
6019    /// Filter bank 0 register 2
6020    pub FR213: RWRegister<u32>,
6021
6022    /// Filter bank 0 register 1
6023    pub FR114: RWRegister<u32>,
6024
6025    /// Filter bank 0 register 2
6026    pub FR214: RWRegister<u32>,
6027
6028    /// Filter bank 0 register 1
6029    pub FR115: RWRegister<u32>,
6030
6031    /// Filter bank 0 register 2
6032    pub FR215: RWRegister<u32>,
6033
6034    /// Filter bank 0 register 1
6035    pub FR116: RWRegister<u32>,
6036
6037    /// Filter bank 0 register 2
6038    pub FR216: RWRegister<u32>,
6039
6040    /// Filter bank 0 register 1
6041    pub FR117: RWRegister<u32>,
6042
6043    /// Filter bank 0 register 2
6044    pub FR217: RWRegister<u32>,
6045
6046    /// Filter bank 0 register 1
6047    pub FR118: RWRegister<u32>,
6048
6049    /// Filter bank 0 register 2
6050    pub FR218: RWRegister<u32>,
6051
6052    /// Filter bank 0 register 1
6053    pub FR119: RWRegister<u32>,
6054
6055    /// Filter bank 0 register 2
6056    pub FR219: RWRegister<u32>,
6057
6058    /// Filter bank 0 register 1
6059    pub FR120: RWRegister<u32>,
6060
6061    /// Filter bank 0 register 2
6062    pub FR220: RWRegister<u32>,
6063
6064    /// Filter bank 0 register 1
6065    pub FR121: RWRegister<u32>,
6066
6067    /// Filter bank 0 register 2
6068    pub FR221: RWRegister<u32>,
6069
6070    /// Filter bank 0 register 1
6071    pub FR122: RWRegister<u32>,
6072
6073    /// Filter bank 0 register 2
6074    pub FR222: RWRegister<u32>,
6075
6076    /// Filter bank 0 register 1
6077    pub FR123: RWRegister<u32>,
6078
6079    /// Filter bank 0 register 2
6080    pub FR223: RWRegister<u32>,
6081
6082    /// Filter bank 0 register 1
6083    pub FR124: RWRegister<u32>,
6084
6085    /// Filter bank 0 register 2
6086    pub FR224: RWRegister<u32>,
6087
6088    /// Filter bank 0 register 1
6089    pub FR125: RWRegister<u32>,
6090
6091    /// Filter bank 0 register 2
6092    pub FR225: RWRegister<u32>,
6093
6094    /// Filter bank 0 register 1
6095    pub FR126: RWRegister<u32>,
6096
6097    /// Filter bank 0 register 2
6098    pub FR226: RWRegister<u32>,
6099
6100    /// Filter bank 0 register 1
6101    pub FR127: RWRegister<u32>,
6102
6103    /// Filter bank 0 register 2
6104    pub FR227: RWRegister<u32>,
6105}
6106pub struct ResetValues {
6107    pub MCR: u32,
6108    pub MSR: u32,
6109    pub TSR: u32,
6110    pub RF0R: u32,
6111    pub RF1R: u32,
6112    pub IER: u32,
6113    pub ESR: u32,
6114    pub BTR: u32,
6115    pub TIR0: u32,
6116    pub TDTR0: u32,
6117    pub TDLR0: u32,
6118    pub TDHR0: u32,
6119    pub TIR1: u32,
6120    pub TDTR1: u32,
6121    pub TDLR1: u32,
6122    pub TDHR1: u32,
6123    pub TIR2: u32,
6124    pub TDTR2: u32,
6125    pub TDLR2: u32,
6126    pub TDHR2: u32,
6127    pub RIR0: u32,
6128    pub RDTR0: u32,
6129    pub RDLR0: u32,
6130    pub RDHR0: u32,
6131    pub RIR1: u32,
6132    pub RDTR1: u32,
6133    pub RDLR1: u32,
6134    pub RDHR1: u32,
6135    pub FMR: u32,
6136    pub FM1R: u32,
6137    pub FS1R: u32,
6138    pub FFA1R: u32,
6139    pub FA1R: u32,
6140    pub FR10: u32,
6141    pub FR20: u32,
6142    pub FR11: u32,
6143    pub FR21: u32,
6144    pub FR12: u32,
6145    pub FR22: u32,
6146    pub FR13: u32,
6147    pub FR23: u32,
6148    pub FR14: u32,
6149    pub FR24: u32,
6150    pub FR15: u32,
6151    pub FR25: u32,
6152    pub FR16: u32,
6153    pub FR26: u32,
6154    pub FR17: u32,
6155    pub FR27: u32,
6156    pub FR18: u32,
6157    pub FR28: u32,
6158    pub FR19: u32,
6159    pub FR29: u32,
6160    pub FR110: u32,
6161    pub FR210: u32,
6162    pub FR111: u32,
6163    pub FR211: u32,
6164    pub FR112: u32,
6165    pub FR212: u32,
6166    pub FR113: u32,
6167    pub FR213: u32,
6168    pub FR114: u32,
6169    pub FR214: u32,
6170    pub FR115: u32,
6171    pub FR215: u32,
6172    pub FR116: u32,
6173    pub FR216: u32,
6174    pub FR117: u32,
6175    pub FR217: u32,
6176    pub FR118: u32,
6177    pub FR218: u32,
6178    pub FR119: u32,
6179    pub FR219: u32,
6180    pub FR120: u32,
6181    pub FR220: u32,
6182    pub FR121: u32,
6183    pub FR221: u32,
6184    pub FR122: u32,
6185    pub FR222: u32,
6186    pub FR123: u32,
6187    pub FR223: u32,
6188    pub FR124: u32,
6189    pub FR224: u32,
6190    pub FR125: u32,
6191    pub FR225: u32,
6192    pub FR126: u32,
6193    pub FR226: u32,
6194    pub FR127: u32,
6195    pub FR227: u32,
6196}
6197#[cfg(not(feature = "nosync"))]
6198pub struct Instance {
6199    pub(crate) addr: u32,
6200    pub(crate) _marker: PhantomData<*const RegisterBlock>,
6201}
6202#[cfg(not(feature = "nosync"))]
6203impl ::core::ops::Deref for Instance {
6204    type Target = RegisterBlock;
6205    #[inline(always)]
6206    fn deref(&self) -> &RegisterBlock {
6207        unsafe { &*(self.addr as *const _) }
6208    }
6209}
6210#[cfg(feature = "rtic")]
6211unsafe impl Send for Instance {}
6212
6213/// Access functions for the CAN1 peripheral instance
6214pub mod CAN1 {
6215    use super::ResetValues;
6216
6217    #[cfg(not(feature = "nosync"))]
6218    use super::Instance;
6219
6220    #[cfg(not(feature = "nosync"))]
6221    const INSTANCE: Instance = Instance {
6222        addr: 0x40006400,
6223        _marker: ::core::marker::PhantomData,
6224    };
6225
6226    /// Reset values for each field in CAN1
6227    pub const reset: ResetValues = ResetValues {
6228        MCR: 0x00010002,
6229        MSR: 0x00000C02,
6230        TSR: 0x1C000000,
6231        RF0R: 0x00000000,
6232        RF1R: 0x00000000,
6233        IER: 0x00000000,
6234        ESR: 0x00000000,
6235        BTR: 0x00000000,
6236        FMR: 0x2A1C0E01,
6237        FM1R: 0x00000000,
6238        FS1R: 0x00000000,
6239        FFA1R: 0x00000000,
6240        FA1R: 0x00000000,
6241        TIR0: 0x00000000,
6242        TDTR0: 0x00000000,
6243        TDLR0: 0x00000000,
6244        TDHR0: 0x00000000,
6245        TIR1: 0x00000000,
6246        TDTR1: 0x00000000,
6247        TDLR1: 0x00000000,
6248        TDHR1: 0x00000000,
6249        TIR2: 0x00000000,
6250        TDTR2: 0x00000000,
6251        TDLR2: 0x00000000,
6252        TDHR2: 0x00000000,
6253        RIR0: 0x00000000,
6254        RDTR0: 0x00000000,
6255        RDLR0: 0x00000000,
6256        RDHR0: 0x00000000,
6257        RIR1: 0x00000000,
6258        RDTR1: 0x00000000,
6259        RDLR1: 0x00000000,
6260        RDHR1: 0x00000000,
6261        FR10: 0x00000000,
6262        FR20: 0x00000000,
6263        FR11: 0x00000000,
6264        FR21: 0x00000000,
6265        FR12: 0x00000000,
6266        FR22: 0x00000000,
6267        FR13: 0x00000000,
6268        FR23: 0x00000000,
6269        FR14: 0x00000000,
6270        FR24: 0x00000000,
6271        FR15: 0x00000000,
6272        FR25: 0x00000000,
6273        FR16: 0x00000000,
6274        FR26: 0x00000000,
6275        FR17: 0x00000000,
6276        FR27: 0x00000000,
6277        FR18: 0x00000000,
6278        FR28: 0x00000000,
6279        FR19: 0x00000000,
6280        FR29: 0x00000000,
6281        FR110: 0x00000000,
6282        FR210: 0x00000000,
6283        FR111: 0x00000000,
6284        FR211: 0x00000000,
6285        FR112: 0x00000000,
6286        FR212: 0x00000000,
6287        FR113: 0x00000000,
6288        FR213: 0x00000000,
6289        FR114: 0x00000000,
6290        FR214: 0x00000000,
6291        FR115: 0x00000000,
6292        FR215: 0x00000000,
6293        FR116: 0x00000000,
6294        FR216: 0x00000000,
6295        FR117: 0x00000000,
6296        FR217: 0x00000000,
6297        FR118: 0x00000000,
6298        FR218: 0x00000000,
6299        FR119: 0x00000000,
6300        FR219: 0x00000000,
6301        FR120: 0x00000000,
6302        FR220: 0x00000000,
6303        FR121: 0x00000000,
6304        FR221: 0x00000000,
6305        FR122: 0x00000000,
6306        FR222: 0x00000000,
6307        FR123: 0x00000000,
6308        FR223: 0x00000000,
6309        FR124: 0x00000000,
6310        FR224: 0x00000000,
6311        FR125: 0x00000000,
6312        FR225: 0x00000000,
6313        FR126: 0x00000000,
6314        FR226: 0x00000000,
6315        FR127: 0x00000000,
6316        FR227: 0x00000000,
6317    };
6318
6319    #[cfg(not(feature = "nosync"))]
6320    #[allow(renamed_and_removed_lints)]
6321    #[allow(private_no_mangle_statics)]
6322    #[no_mangle]
6323    static mut CAN1_TAKEN: bool = false;
6324
6325    /// Safe access to CAN1
6326    ///
6327    /// This function returns `Some(Instance)` if this instance is not
6328    /// currently taken, and `None` if it is. This ensures that if you
6329    /// do get `Some(Instance)`, you are ensured unique access to
6330    /// the peripheral and there cannot be data races (unless other
6331    /// code uses `unsafe`, of course). You can then pass the
6332    /// `Instance` around to other functions as required. When you're
6333    /// done with it, you can call `release(instance)` to return it.
6334    ///
6335    /// `Instance` itself dereferences to a `RegisterBlock`, which
6336    /// provides access to the peripheral's registers.
6337    #[cfg(not(feature = "nosync"))]
6338    #[inline]
6339    pub fn take() -> Option<Instance> {
6340        external_cortex_m::interrupt::free(|_| unsafe {
6341            if CAN1_TAKEN {
6342                None
6343            } else {
6344                CAN1_TAKEN = true;
6345                Some(INSTANCE)
6346            }
6347        })
6348    }
6349
6350    /// Release exclusive access to CAN1
6351    ///
6352    /// This function allows you to return an `Instance` so that it
6353    /// is available to `take()` again. This function will panic if
6354    /// you return a different `Instance` or if this instance is not
6355    /// already taken.
6356    #[cfg(not(feature = "nosync"))]
6357    #[inline]
6358    pub fn release(inst: Instance) {
6359        external_cortex_m::interrupt::free(|_| unsafe {
6360            if CAN1_TAKEN && inst.addr == INSTANCE.addr {
6361                CAN1_TAKEN = false;
6362            } else {
6363                panic!("Released a peripheral which was not taken");
6364            }
6365        });
6366    }
6367
6368    /// Unsafely steal CAN1
6369    ///
6370    /// This function is similar to take() but forcibly takes the
6371    /// Instance, marking it as taken irregardless of its previous
6372    /// state.
6373    #[cfg(not(feature = "nosync"))]
6374    #[inline]
6375    pub unsafe fn steal() -> Instance {
6376        CAN1_TAKEN = true;
6377        INSTANCE
6378    }
6379}
6380
6381/// Raw pointer to CAN1
6382///
6383/// Dereferencing this is unsafe because you are not ensured unique
6384/// access to the peripheral, so you may encounter data races with
6385/// other users of this peripheral. It is up to you to ensure you
6386/// will not cause data races.
6387///
6388/// This constant is provided for ease of use in unsafe code: you can
6389/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
6390pub const CAN1: *const RegisterBlock = 0x40006400 as *const _;
6391
6392/// Access functions for the CAN2 peripheral instance
6393pub mod CAN2 {
6394    use super::ResetValues;
6395
6396    #[cfg(not(feature = "nosync"))]
6397    use super::Instance;
6398
6399    #[cfg(not(feature = "nosync"))]
6400    const INSTANCE: Instance = Instance {
6401        addr: 0x40006800,
6402        _marker: ::core::marker::PhantomData,
6403    };
6404
6405    /// Reset values for each field in CAN2
6406    pub const reset: ResetValues = ResetValues {
6407        MCR: 0x00010002,
6408        MSR: 0x00000C02,
6409        TSR: 0x1C000000,
6410        RF0R: 0x00000000,
6411        RF1R: 0x00000000,
6412        IER: 0x00000000,
6413        ESR: 0x00000000,
6414        BTR: 0x00000000,
6415        FMR: 0x2A1C0E01,
6416        FM1R: 0x00000000,
6417        FS1R: 0x00000000,
6418        FFA1R: 0x00000000,
6419        FA1R: 0x00000000,
6420        TIR0: 0x00000000,
6421        TDTR0: 0x00000000,
6422        TDLR0: 0x00000000,
6423        TDHR0: 0x00000000,
6424        TIR1: 0x00000000,
6425        TDTR1: 0x00000000,
6426        TDLR1: 0x00000000,
6427        TDHR1: 0x00000000,
6428        TIR2: 0x00000000,
6429        TDTR2: 0x00000000,
6430        TDLR2: 0x00000000,
6431        TDHR2: 0x00000000,
6432        RIR0: 0x00000000,
6433        RDTR0: 0x00000000,
6434        RDLR0: 0x00000000,
6435        RDHR0: 0x00000000,
6436        RIR1: 0x00000000,
6437        RDTR1: 0x00000000,
6438        RDLR1: 0x00000000,
6439        RDHR1: 0x00000000,
6440        FR10: 0x00000000,
6441        FR20: 0x00000000,
6442        FR11: 0x00000000,
6443        FR21: 0x00000000,
6444        FR12: 0x00000000,
6445        FR22: 0x00000000,
6446        FR13: 0x00000000,
6447        FR23: 0x00000000,
6448        FR14: 0x00000000,
6449        FR24: 0x00000000,
6450        FR15: 0x00000000,
6451        FR25: 0x00000000,
6452        FR16: 0x00000000,
6453        FR26: 0x00000000,
6454        FR17: 0x00000000,
6455        FR27: 0x00000000,
6456        FR18: 0x00000000,
6457        FR28: 0x00000000,
6458        FR19: 0x00000000,
6459        FR29: 0x00000000,
6460        FR110: 0x00000000,
6461        FR210: 0x00000000,
6462        FR111: 0x00000000,
6463        FR211: 0x00000000,
6464        FR112: 0x00000000,
6465        FR212: 0x00000000,
6466        FR113: 0x00000000,
6467        FR213: 0x00000000,
6468        FR114: 0x00000000,
6469        FR214: 0x00000000,
6470        FR115: 0x00000000,
6471        FR215: 0x00000000,
6472        FR116: 0x00000000,
6473        FR216: 0x00000000,
6474        FR117: 0x00000000,
6475        FR217: 0x00000000,
6476        FR118: 0x00000000,
6477        FR218: 0x00000000,
6478        FR119: 0x00000000,
6479        FR219: 0x00000000,
6480        FR120: 0x00000000,
6481        FR220: 0x00000000,
6482        FR121: 0x00000000,
6483        FR221: 0x00000000,
6484        FR122: 0x00000000,
6485        FR222: 0x00000000,
6486        FR123: 0x00000000,
6487        FR223: 0x00000000,
6488        FR124: 0x00000000,
6489        FR224: 0x00000000,
6490        FR125: 0x00000000,
6491        FR225: 0x00000000,
6492        FR126: 0x00000000,
6493        FR226: 0x00000000,
6494        FR127: 0x00000000,
6495        FR227: 0x00000000,
6496    };
6497
6498    #[cfg(not(feature = "nosync"))]
6499    #[allow(renamed_and_removed_lints)]
6500    #[allow(private_no_mangle_statics)]
6501    #[no_mangle]
6502    static mut CAN2_TAKEN: bool = false;
6503
6504    /// Safe access to CAN2
6505    ///
6506    /// This function returns `Some(Instance)` if this instance is not
6507    /// currently taken, and `None` if it is. This ensures that if you
6508    /// do get `Some(Instance)`, you are ensured unique access to
6509    /// the peripheral and there cannot be data races (unless other
6510    /// code uses `unsafe`, of course). You can then pass the
6511    /// `Instance` around to other functions as required. When you're
6512    /// done with it, you can call `release(instance)` to return it.
6513    ///
6514    /// `Instance` itself dereferences to a `RegisterBlock`, which
6515    /// provides access to the peripheral's registers.
6516    #[cfg(not(feature = "nosync"))]
6517    #[inline]
6518    pub fn take() -> Option<Instance> {
6519        external_cortex_m::interrupt::free(|_| unsafe {
6520            if CAN2_TAKEN {
6521                None
6522            } else {
6523                CAN2_TAKEN = true;
6524                Some(INSTANCE)
6525            }
6526        })
6527    }
6528
6529    /// Release exclusive access to CAN2
6530    ///
6531    /// This function allows you to return an `Instance` so that it
6532    /// is available to `take()` again. This function will panic if
6533    /// you return a different `Instance` or if this instance is not
6534    /// already taken.
6535    #[cfg(not(feature = "nosync"))]
6536    #[inline]
6537    pub fn release(inst: Instance) {
6538        external_cortex_m::interrupt::free(|_| unsafe {
6539            if CAN2_TAKEN && inst.addr == INSTANCE.addr {
6540                CAN2_TAKEN = false;
6541            } else {
6542                panic!("Released a peripheral which was not taken");
6543            }
6544        });
6545    }
6546
6547    /// Unsafely steal CAN2
6548    ///
6549    /// This function is similar to take() but forcibly takes the
6550    /// Instance, marking it as taken irregardless of its previous
6551    /// state.
6552    #[cfg(not(feature = "nosync"))]
6553    #[inline]
6554    pub unsafe fn steal() -> Instance {
6555        CAN2_TAKEN = true;
6556        INSTANCE
6557    }
6558}
6559
6560/// Raw pointer to CAN2
6561///
6562/// Dereferencing this is unsafe because you are not ensured unique
6563/// access to the peripheral, so you may encounter data races with
6564/// other users of this peripheral. It is up to you to ensure you
6565/// will not cause data races.
6566///
6567/// This constant is provided for ease of use in unsafe code: you can
6568/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
6569pub const CAN2: *const RegisterBlock = 0x40006800 as *const _;
stm32ral/stm32f7/stm32f750/can.rs

stm32ral/stm32f7/stm32f750/
can.rs
