stm32ral/stm32f0/stm32f0x0/dbgmcu.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Debug support
4
5use crate::{RORegister, RWRegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// MCU Device ID Code Register
10pub mod IDCODE {
11
12 /// Device Identifier
13 pub mod DEV_ID {
14 /// Offset (0 bits)
15 pub const offset: u32 = 0;
16 /// Mask (12 bits: 0xfff << 0)
17 pub const mask: u32 = 0xfff << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25
26 /// Division Identifier
27 pub mod DIV_ID {
28 /// Offset (12 bits)
29 pub const offset: u32 = 12;
30 /// Mask (4 bits: 0b1111 << 12)
31 pub const mask: u32 = 0b1111 << offset;
32 /// Read-only values (empty)
33 pub mod R {}
34 /// Write-only values (empty)
35 pub mod W {}
36 /// Read-write values (empty)
37 pub mod RW {}
38 }
39
40 /// Revision Identifier
41 pub mod REV_ID {
42 /// Offset (16 bits)
43 pub const offset: u32 = 16;
44 /// Mask (16 bits: 0xffff << 16)
45 pub const mask: u32 = 0xffff << offset;
46 /// Read-only values (empty)
47 pub mod R {}
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53}
54
55/// Debug MCU Configuration Register
56pub mod CR {
57
58 /// Debug Stop Mode
59 pub mod DBG_STOP {
60 /// Offset (1 bits)
61 pub const offset: u32 = 1;
62 /// Mask (1 bit: 1 << 1)
63 pub const mask: u32 = 1 << offset;
64 /// Read-only values (empty)
65 pub mod R {}
66 /// Write-only values (empty)
67 pub mod W {}
68 /// Read-write values (empty)
69 pub mod RW {}
70 }
71
72 /// Debug Standby Mode
73 pub mod DBG_STANDBY {
74 /// Offset (2 bits)
75 pub const offset: u32 = 2;
76 /// Mask (1 bit: 1 << 2)
77 pub const mask: u32 = 1 << offset;
78 /// Read-only values (empty)
79 pub mod R {}
80 /// Write-only values (empty)
81 pub mod W {}
82 /// Read-write values (empty)
83 pub mod RW {}
84 }
85}
86
87/// Debug MCU APB1 freeze register
88pub mod APB1_FZ {
89
90 /// TIM3 counter stopped when core is halted
91 pub mod DBG_TIM3_STOP {
92 /// Offset (1 bits)
93 pub const offset: u32 = 1;
94 /// Mask (1 bit: 1 << 1)
95 pub const mask: u32 = 1 << offset;
96 /// Read-only values (empty)
97 pub mod R {}
98 /// Write-only values (empty)
99 pub mod W {}
100 /// Read-write values (empty)
101 pub mod RW {}
102 }
103
104 /// TIM6 counter stopped when core is halted
105 pub mod DBG_TIM6_STOP {
106 /// Offset (4 bits)
107 pub const offset: u32 = 4;
108 /// Mask (1 bit: 1 << 4)
109 pub const mask: u32 = 1 << offset;
110 /// Read-only values (empty)
111 pub mod R {}
112 /// Write-only values (empty)
113 pub mod W {}
114 /// Read-write values (empty)
115 pub mod RW {}
116 }
117
118 /// TIM7 counter stopped when core is halted
119 pub mod DBG_TIM7_STOP {
120 /// Offset (5 bits)
121 pub const offset: u32 = 5;
122 /// Mask (1 bit: 1 << 5)
123 pub const mask: u32 = 1 << offset;
124 /// Read-only values (empty)
125 pub mod R {}
126 /// Write-only values (empty)
127 pub mod W {}
128 /// Read-write values (empty)
129 pub mod RW {}
130 }
131
132 /// TIM14 counter stopped when core is halted
133 pub mod DBG_TIM14_STOP {
134 /// Offset (8 bits)
135 pub const offset: u32 = 8;
136 /// Mask (1 bit: 1 << 8)
137 pub const mask: u32 = 1 << offset;
138 /// Read-only values (empty)
139 pub mod R {}
140 /// Write-only values (empty)
141 pub mod W {}
142 /// Read-write values (empty)
143 pub mod RW {}
144 }
145
146 /// Debug window watchdog stopped when core is halted
147 pub mod DBG_WWDG_STOP {
148 /// Offset (11 bits)
149 pub const offset: u32 = 11;
150 /// Mask (1 bit: 1 << 11)
151 pub const mask: u32 = 1 << offset;
152 /// Read-only values (empty)
153 pub mod R {}
154 /// Write-only values (empty)
155 pub mod W {}
156 /// Read-write values (empty)
157 pub mod RW {}
158 }
159
160 /// Debug independent watchdog stopped when core is halted
161 pub mod DBG_IWDG_STOP {
162 /// Offset (12 bits)
163 pub const offset: u32 = 12;
164 /// Mask (1 bit: 1 << 12)
165 pub const mask: u32 = 1 << offset;
166 /// Read-only values (empty)
167 pub mod R {}
168 /// Write-only values (empty)
169 pub mod W {}
170 /// Read-write values (empty)
171 pub mod RW {}
172 }
173
174 /// SMBUS timeout mode stopped when core is halted
175 pub mod DBG_I2C1_SMBUS_TIMEOUT {
176 /// Offset (21 bits)
177 pub const offset: u32 = 21;
178 /// Mask (1 bit: 1 << 21)
179 pub const mask: u32 = 1 << offset;
180 /// Read-only values (empty)
181 pub mod R {}
182 /// Write-only values (empty)
183 pub mod W {}
184 /// Read-write values (empty)
185 pub mod RW {}
186 }
187}
188
189/// Debug MCU APB2 freeze register
190pub mod APB2_FZ {
191
192 /// TIM1 counter stopped when core is halted
193 pub mod DBG_TIM1_STOP {
194 /// Offset (11 bits)
195 pub const offset: u32 = 11;
196 /// Mask (1 bit: 1 << 11)
197 pub const mask: u32 = 1 << offset;
198 /// Read-only values (empty)
199 pub mod R {}
200 /// Write-only values (empty)
201 pub mod W {}
202 /// Read-write values (empty)
203 pub mod RW {}
204 }
205
206 /// TIM15 counter stopped when core is halted
207 pub mod DBG_TIM15_STOP {
208 /// Offset (16 bits)
209 pub const offset: u32 = 16;
210 /// Mask (1 bit: 1 << 16)
211 pub const mask: u32 = 1 << offset;
212 /// Read-only values (empty)
213 pub mod R {}
214 /// Write-only values (empty)
215 pub mod W {}
216 /// Read-write values (empty)
217 pub mod RW {}
218 }
219
220 /// TIM16 counter stopped when core is halted
221 pub mod DBG_TIM16_STOP {
222 /// Offset (17 bits)
223 pub const offset: u32 = 17;
224 /// Mask (1 bit: 1 << 17)
225 pub const mask: u32 = 1 << offset;
226 /// Read-only values (empty)
227 pub mod R {}
228 /// Write-only values (empty)
229 pub mod W {}
230 /// Read-write values (empty)
231 pub mod RW {}
232 }
233
234 /// TIM17 counter stopped when core is halted
235 pub mod DBG_TIM17_STOP {
236 /// Offset (18 bits)
237 pub const offset: u32 = 18;
238 /// Mask (1 bit: 1 << 18)
239 pub const mask: u32 = 1 << offset;
240 /// Read-only values (empty)
241 pub mod R {}
242 /// Write-only values (empty)
243 pub mod W {}
244 /// Read-write values (empty)
245 pub mod RW {}
246 }
247}
248#[repr(C)]
249pub struct RegisterBlock {
250 /// MCU Device ID Code Register
251 pub IDCODE: RORegister<u32>,
252
253 /// Debug MCU Configuration Register
254 pub CR: RWRegister<u32>,
255
256 /// Debug MCU APB1 freeze register
257 pub APB1_FZ: RWRegister<u32>,
258
259 /// Debug MCU APB2 freeze register
260 pub APB2_FZ: RWRegister<u32>,
261}
262pub struct ResetValues {
263 pub IDCODE: u32,
264 pub CR: u32,
265 pub APB1_FZ: u32,
266 pub APB2_FZ: u32,
267}
268#[cfg(not(feature = "nosync"))]
269pub struct Instance {
270 pub(crate) addr: u32,
271 pub(crate) _marker: PhantomData<*const RegisterBlock>,
272}
273#[cfg(not(feature = "nosync"))]
274impl ::core::ops::Deref for Instance {
275 type Target = RegisterBlock;
276 #[inline(always)]
277 fn deref(&self) -> &RegisterBlock {
278 unsafe { &*(self.addr as *const _) }
279 }
280}
281#[cfg(feature = "rtic")]
282unsafe impl Send for Instance {}
283
284/// Access functions for the DBGMCU peripheral instance
285pub mod DBGMCU {
286 use super::ResetValues;
287
288 #[cfg(not(feature = "nosync"))]
289 use super::Instance;
290
291 #[cfg(not(feature = "nosync"))]
292 const INSTANCE: Instance = Instance {
293 addr: 0x40015800,
294 _marker: ::core::marker::PhantomData,
295 };
296
297 /// Reset values for each field in DBGMCU
298 pub const reset: ResetValues = ResetValues {
299 IDCODE: 0x00000000,
300 CR: 0x00000000,
301 APB1_FZ: 0x00000000,
302 APB2_FZ: 0x00000000,
303 };
304
305 #[cfg(not(feature = "nosync"))]
306 #[allow(renamed_and_removed_lints)]
307 #[allow(private_no_mangle_statics)]
308 #[no_mangle]
309 static mut DBGMCU_TAKEN: bool = false;
310
311 /// Safe access to DBGMCU
312 ///
313 /// This function returns `Some(Instance)` if this instance is not
314 /// currently taken, and `None` if it is. This ensures that if you
315 /// do get `Some(Instance)`, you are ensured unique access to
316 /// the peripheral and there cannot be data races (unless other
317 /// code uses `unsafe`, of course). You can then pass the
318 /// `Instance` around to other functions as required. When you're
319 /// done with it, you can call `release(instance)` to return it.
320 ///
321 /// `Instance` itself dereferences to a `RegisterBlock`, which
322 /// provides access to the peripheral's registers.
323 #[cfg(not(feature = "nosync"))]
324 #[inline]
325 pub fn take() -> Option<Instance> {
326 external_cortex_m::interrupt::free(|_| unsafe {
327 if DBGMCU_TAKEN {
328 None
329 } else {
330 DBGMCU_TAKEN = true;
331 Some(INSTANCE)
332 }
333 })
334 }
335
336 /// Release exclusive access to DBGMCU
337 ///
338 /// This function allows you to return an `Instance` so that it
339 /// is available to `take()` again. This function will panic if
340 /// you return a different `Instance` or if this instance is not
341 /// already taken.
342 #[cfg(not(feature = "nosync"))]
343 #[inline]
344 pub fn release(inst: Instance) {
345 external_cortex_m::interrupt::free(|_| unsafe {
346 if DBGMCU_TAKEN && inst.addr == INSTANCE.addr {
347 DBGMCU_TAKEN = false;
348 } else {
349 panic!("Released a peripheral which was not taken");
350 }
351 });
352 }
353
354 /// Unsafely steal DBGMCU
355 ///
356 /// This function is similar to take() but forcibly takes the
357 /// Instance, marking it as taken irregardless of its previous
358 /// state.
359 #[cfg(not(feature = "nosync"))]
360 #[inline]
361 pub unsafe fn steal() -> Instance {
362 DBGMCU_TAKEN = true;
363 INSTANCE
364 }
365}
366
367/// Raw pointer to DBGMCU
368///
369/// Dereferencing this is unsafe because you are not ensured unique
370/// access to the peripheral, so you may encounter data races with
371/// other users of this peripheral. It is up to you to ensure you
372/// will not cause data races.
373///
374/// This constant is provided for ease of use in unsafe code: you can
375/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
376pub const DBGMCU: *const RegisterBlock = 0x40015800 as *const _;